CN117810318B - High-voltage Micro-LED chip and preparation method thereof - Google Patents
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Abstract
The invention discloses a high-voltage Micro-LED chip and a preparation method thereof, and relates to the technical field of light emitting diodes. The preparation method comprises the following steps: providing a first epitaxial wafer, sequentially forming a first N-type electrode, a first P-type electrode and a first bonding layer, and etching to expose the first N-type electrode and the first P-type electrode to obtain a first intermediate; providing a second epitaxial wafer, sequentially forming an intermediate electrode and a second bonding layer, and etching to expose the intermediate electrode to obtain a second intermediate; bonding the first intermediate and the second intermediate, and stripping the second substrate to obtain an intermediate chip; and sequentially forming a passivation layer, a second N-type electrode and a second P-type electrode on the middle chip, and stripping the first substrate to obtain a high-voltage Micro-LED chip finished product. By implementing the method, the Micro-LED chip with high working voltage and high luminous efficiency can be prepared.
Description
Technical Field
The invention relates to the technical field of light emitting diodes, in particular to a high-voltage Micro-LED chip and a preparation method thereof.
Background
The Micro-LED Micro display technology has self-luminous characteristics, and each pixel can independently drive to emit light, and has the advantages of high brightness, low power consumption, small volume, ultrahigh resolution, color saturation and the like. Compared with the OLED technology which is self-luminous display, the Micro LED has the advantages of higher efficiency, longer service life, less possibility of being influenced by environment and relatively stable material, and capability of avoiding the generation of the afterimage phenomenon, so that the Micro-LED display technology is a future development trend and has a great market prospect.
The light efficiency of the Micro-LED chip can change along with the change of the current density, and when the current density is smaller than a certain specific value, the larger the current density is, the higher the light efficiency is; above a certain value, the greater the current density, the lower the light effect, i.e. the light effect has the highest value at a certain current density. The applied current density of Micro-LED chips is often relatively small, resulting in low light efficiency. Referring to fig. 1, in a conventional LED chip, positive and negative connection of two chips may be achieved by penetrating N electrodes through the adjacent two chips, thereby forming a high voltage LED chip. However, if the Micro-LED adopts this structure, the current blocking layer B under the N electrode a will be broken when the substrate is peeled off later, and a high-voltage structure with the anode and the cathode connected cannot be formed.
Disclosure of Invention
The technical problem to be solved by the invention is to provide the high-voltage Micro-LED chip and the preparation method thereof, which can effectively improve the working voltage of the Micro-LED chip and the luminous efficiency of the Micro-LED chip.
In order to solve the technical problems, the invention provides a preparation method of a high-voltage Micro-LED chip, which comprises the following steps:
S1, providing a first epitaxial wafer, wherein the first epitaxial wafer comprises a first substrate, and a first N-type semiconductor layer, a first MQW layer and a first P-type semiconductor layer which are sequentially laminated on the first substrate;
S2, forming a first N-type hole etched to the first N-type semiconductor layer on the first epitaxial wafer;
s3, forming a first N-type electrode and a first P-type electrode on the first epitaxial wafer obtained in the step S2, wherein the first N-type electrode is connected with the first N-type semiconductor layer through the first N-type hole;
s4, forming a first bonding layer on the first epitaxial wafer obtained in the step S3, and etching and exposing the first N-type electrode and the first P-type electrode to obtain a first intermediate;
s5, providing a second epitaxial wafer, wherein the second epitaxial wafer comprises a second substrate, and a second N-type semiconductor layer, a second MQW layer and a second P-type semiconductor layer which are sequentially laminated on the second substrate;
S6, forming an intermediate electrode on the second P-type semiconductor layer;
s7, forming a second bonding layer on the second epitaxial wafer obtained in the step S6, and etching to expose the intermediate electrode to obtain a second intermediate;
s8, bonding the first intermediate and the second intermediate, and stripping the second substrate to expose the second N-type semiconductor layer to obtain an intermediate chip; wherein, after bonding, the intermediate electrode and the first N-type electrode form electric connection;
s9, forming a first P-type hole exposing the first P-type electrode on the middle chip;
s10, forming a passivation layer on the intermediate chip obtained in the step S9, and forming a second N-type hole and a second P-type hole by respectively forming holes above the second N-type semiconductor layer and the first P-type electrode;
S11, forming a second N-type electrode and a second P-type electrode on the intermediate chip obtained in the step S10, wherein the second N-type electrode is connected with the second N-type semiconductor layer through the second N-type hole, and the second P-type electrode is connected with the first P-type electrode through the second P-type hole;
s12, stripping the first substrate to obtain a finished product of the high-voltage Micro-LED chip.
As an improvement of the above technical solution, the first N-type electrode and the intermediate electrode each include a third bonding layer to bond the first N-type electrode and the intermediate electrode;
the difference between the widths of the first N-type electrode and the intermediate electrode is less than or equal to 10 mu m.
As an improvement of the above technical solution, step S8 includes:
S81, bonding the first N-type electrode and the intermediate electrode, wherein the bonding temperature is 200-350 ℃, the bonding pressure is 0.5-4 MPa, and the bonding time is 7-25 min;
s82, bonding the first bonding layer and the second bonding layer, wherein the bonding temperature is 350-500 ℃, the bonding pressure is 1-7 kN, and the bonding time is 10-30 min;
S83, stripping the second substrate by laser, and removing the second U-shaped semiconductor layer by alkali liquor corrosion;
s84, removing the damaged surface of the second N-type semiconductor layer by dry etching, wherein the etching thickness is 0.3-0.8 mu m.
As an improvement of the above technical solution, the upper surface of the first bonding layer on the first P-type semiconductor layer, the upper surface of the first P-type electrode and the upper surface of the first N-type electrode are flush;
The upper surface of the second bonding layer on the second P-type semiconductor layer is flush with the upper surface of the intermediate electrode.
As an improvement of the above technical solution, the first bonding layer and the second bonding layer are both made of insulating materials.
As an improvement of the technical scheme, the first bonding layer is a laminated structure formed by one or two of an AlO x layer and an SiO x layer, and the thickness of the first bonding layer is 0.8-3 mu m;
The second bonding layer is of a laminated structure formed by one or two of an AlO x layer and a SiO x layer, and the thickness of the second bonding layer is 0.8-3 mu m.
As an improvement of the above technical solution, the first N-type electrode includes a first ohmic contact layer, a first reflective layer, a first cladding layer, and a third bonding layer sequentially stacked;
the first ohmic contact layer is a laminated structure formed by one or more of a Cr layer, a Ni layer and a Ti layer, and the thickness of the first ohmic contact layer is 25A-200A;
The first reflecting layer is a laminated structure formed by one or two of an Al layer and an Ag layer, and the thickness of the first reflecting layer is 500A-2500A;
the first coating layer is of a laminated structure formed by one or more of a Ti layer, a Ni layer and a Pt layer, and the thickness of the first coating layer is 300-1500 nm;
The third bonding layer is a laminated structure composed of one or more of a Ni layer, an In layer, a Cu layer and an Au layer, and the thickness of the third bonding layer is 1-5 mu m;
The first P-type electrode comprises a second ohmic contact layer, a second reflecting layer, a second cladding layer and an etching barrier layer which are sequentially laminated;
the second ohmic contact layer is a laminated structure formed by one or more of a Cr layer, a Ni layer and a Ti layer, and the thickness of the second ohmic contact layer is 25A-200A;
The second reflecting layer is a laminated structure formed by one or two of an Al layer and an Ag layer, and the thickness of the second reflecting layer is 500A-2500A;
The second coating layer is a laminated structure formed by one or more of a Ti layer, a Ni layer and a Pt layer, and the thickness of the second coating layer is 300-1500 nm;
The etching barrier layer is a laminated structure formed by one or two of a Pt layer and an Au layer, and the thickness of the etching barrier layer is 2000A-5000A.
As an improvement of the above technical solution, the intermediate electrode includes a third ohmic contact layer, a third clad layer, and a third bonding layer sequentially stacked;
the third ohmic contact layer is a laminated structure formed by one or more of a Cr layer, a Ni layer and a Ti layer, and the thickness of the third ohmic contact layer is 25A-200A;
the third coating layer is of a laminated structure formed by one or more of a Ti layer, a Ni layer and a Pt layer, and the thickness of the third coating layer is 300-1500 nm;
The third bonding layer is a laminated structure composed of one or more of a Ni layer, an In layer, a Cu layer and an Au layer, and the thickness of the third bonding layer is 1-5 mu m.
As an improvement of the technical scheme, the passivation layer is of a laminated structure formed by one or two of an AlO x layer and a SiO x layer, and the thickness of the passivation layer is 500A-5000A.
Correspondingly, the invention also discloses a high-voltage Micro-LED chip, which is prepared by the preparation method of the high-voltage Micro-LED chip.
The implementation of the invention has the following beneficial effects:
In the preparation method of the high-voltage Micro-LED chip, a first N-type electrode, a first P-type electrode and a first bonding layer are sequentially formed on a first epitaxial wafer, and the first N-type electrode and the first P-type electrode are exposed through etching to obtain a first intermediate; sequentially forming an intermediate electrode and a second bonding layer on the second epitaxial wafer, and etching to expose the intermediate electrode to obtain a second intermediate; bonding the first intermediate and the second intermediate, and stripping the second substrate to obtain an intermediate chip; and forming a passivation layer, a second N-type electrode and a second P-type electrode on the middle chip in sequence, and finally stripping the first substrate to obtain a high-voltage Micro-LED chip finished product. Based on the process, two Micro-LED chip units can be connected together, so that the working voltage is effectively increased, in addition, the structure formed based on the preparation method can promote the uniform distribution of current, weaken the quantum efficiency attenuation effect and improve the luminous efficiency.
Drawings
Fig. 1 is a schematic diagram of a structure of a high voltage LED chip in the prior art;
FIG. 2 is a flow chart of a method of fabricating a high voltage Micro-LED chip according to an embodiment of the invention;
Fig. 3 is a schematic structural diagram of the first epitaxial wafer after step S2;
Fig. 4 is a schematic structural diagram of the first epitaxial wafer after step S3;
FIG. 5 is a schematic diagram of a first N-type electrode according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a first P-type electrode according to an embodiment of the invention;
FIG. 7 is a schematic structural diagram of the first intermediate after step S4;
FIG. 8 is a schematic diagram of the structure of the second intermediate after step S7;
FIG. 9 is a schematic diagram of an intermediate electrode according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of the structure of the intermediate chip after step S8;
FIG. 11 is a schematic diagram of the structure of the intermediate chip after step S9;
FIG. 12 is a schematic diagram of the structure of the intermediate chip after step S11;
FIG. 13 is a schematic diagram of a high voltage Micro-LED chip according to an embodiment of the present invention;
In the figure, 1 is a first epitaxial wafer, 11 is a first substrate, 12 is a first N-type semiconductor layer, 13 is a first MQW layer, 14 is a first P-type semiconductor layer, 15 is a first U-type semiconductor layer, 16 is a first N-type hole, 10 is a first intermediate, 2 is a first N-type electrode, 21 is a first ohmic contact layer, 22 is a first reflective layer, 23 is a first clad layer, 24 is a third bonding layer, 3 is a first P-type electrode, 31 is a second ohmic contact layer, 32 is a second reflective layer, 33 is a second clad layer, 34 is an etching barrier layer, 40 is an intermediate chip, 41 is a first bonding layer, 42 is a second bonding layer, 43 is a first P-type hole, 5 is a second epitaxial wafer, 51 is a second substrate, 52 is a second N-type semiconductor layer, 53 is a second MQW layer, 54 is a second P-type semiconductor layer, 55 is a second U-type semiconductor layer, 50 is a second intermediate, 6 is a third intermediate, 61 is a third electrode, 62 is a third P-type electrode, and 71 is a second P-type electrode, and 72 is a second P-type hole.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It is only stated that the terms of orientation such as up, down, left, right, front, back, inner, outer, etc. used in this document or the imminent present invention, are used only with reference to the drawings of the present invention, and are not meant to be limiting in any way.
Referring to fig. 2, the invention provides a method for preparing a high-voltage Micro-LED chip, which comprises the following steps:
s1: providing a first epitaxial wafer;
In which, referring to fig. 3, the first epitaxial wafer 1 includes a first substrate 11 and a first N-type semiconductor layer 12, a first MQW layer 13, and a first P-type semiconductor layer 14 sequentially stacked on the first substrate 11. The first substrate 11 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. The first N-type semiconductor layer 12 may be an N-type GaN layer, an N-type AlGaN layer, an N-type GaAs layer, but is not limited thereto. The first MQW layer 13 may be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The first P-type semiconductor layer 14 may be a P-type GaN layer, a P-type AlGaN layer, a P-type GaAs layer, but is not limited thereto. Preferably, the first substrate 11 is a sapphire substrate, which is more easily peeled off at a later stage.
Preferably, in one embodiment of the present invention, the first epitaxial wafer 1 further includes a first U-shaped semiconductor layer 15 disposed between the first substrate 11 and the first N-shaped semiconductor layer 12. More preferably, the first epitaxial wafer may further include one or more of a buffer layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer, which are common in the art, but is not limited thereto.
S2: forming a first N-type hole etched to the first N-type semiconductor layer on the first epitaxial wafer;
Wherein the first N-type hole 16 may be formed by a photolithography-etching process. The etching process may be dry etching or wet etching, but is not limited thereto. A dry etching process (e.g., ICP or RIE) is preferred, which better ensures the inclination angle of the sidewalls of the first N-type holes 16.
S3: s2, forming a first N-type electrode and a first P-type electrode on the first epitaxial wafer;
Specifically, the first N-type electrode 2 and the first P-type electrode 3 may be formed by PVD, evaporation, or the like, but are not limited thereto. The first N-type electrode 2 and the first P-type electrode 3 may have the same or different compositions, that is, the first N-type electrode 2 and the first P-type electrode 3 may be formed simultaneously or separately in the same electrode forming process. When the first N-type electrode 2 and the first P-type electrode 3 are formed stepwise, the order of formation of the two is not particularly limited.
Specifically, referring to fig. 4, the first N-type electrode 2 is electrically connected to the first N-type semiconductor layer 12 through the first N-type hole 16. More specifically, the first N-type electrode 2 is formed in the first N-type hole 16 and isolated from the first MQW layer 13 and the first P-type semiconductor layer 14. The first P-type electrode 3 is formed on the first P-type semiconductor layer 14.
In one embodiment of the present invention, the first N-type electrode 2 and the first P-type electrode 3 have different structures. Specifically, referring to fig. 5, the first N-type electrode 2 includes a first ohmic contact layer 21, a first reflective layer 22, a first clad layer 23, and a third bonding layer 24, which are sequentially stacked. Based on the first N-type electrode 2 of the structure, bonding can be formed between the first N-type electrode and the middle electrode 6 in the later stage, and the connection stability between Micro-LEDs is improved.
Specifically, the first ohmic contact layer 21 is a laminated structure composed of one or more of a Cr layer, a Ni layer and a Ti layer, and has a thickness of 25 a to 200 a; the first reflecting layer 22 is an Al layer or an Ag layer or a laminated structure composed of the Al layer and the Ag layer, and the thickness of the first reflecting layer is 500A-2500A; the first coating layer 23 has a laminated structure composed of one or more of a Ti layer, a Ni layer and a Pt layer, and has a thickness of 300nm to 1500nm; the third bonding layer 24 is a laminated structure composed of one or more of Ni layer, in layer, cu layer, and Au layer, and has a thickness of 1 μm to 5 μm. The first N-type electrode 2 based on the material combination not only can form good bonding with the intermediate electrode 6, but also can effectively improve the reliability and luminous efficiency of the Micro-LED chip.
Specifically, referring to fig. 6, the first P-type electrode 3 includes the second ohmic contact layer 31, the second reflective layer 32, the second cladding layer 33, and the etch stopper layer 34 sequentially stacked, and based on the first P-type electrode 3 of this structure, damage to the first P-type electrode 3 when the first bonding layer 41 and the passivation layer 7 are etched at a later stage can be prevented.
Specifically, the second ohmic contact layer 31 is a stacked structure formed by one or more of a Cr layer, a Ni layer, and a Ti layer, and has a thickness of 25 a to 200 a; the second reflection layer 32 is an Al layer or an Ag layer or a laminated structure composed of the Al layer and the Ag layer, and the thickness of the second reflection layer is 500A-2500A; the second coating layer 33 is a laminated structure composed of one or more of a Ti layer, a Ni layer and a Pt layer, and the thickness of the second coating layer is 300-1500 nm; the etching barrier layer 34 is a stacked structure composed of one or two of a Pt layer and an Au layer, and the thickness of the etching barrier layer is 2000A-5000A.
Specifically, the upper surface of the first N-type electrode 2 is flush or not flush with the upper surface of the first P-type electrode 3, and preferably, in one embodiment, the total thickness of the first P-type electrode 3 is controlled to be 0.8 μm to 3 μm. So that the upper surface of the first N-type electrode 2 is flush with the upper surface of the first P-type electrode 3, thereby improving the connection stability.
S4: forming a first bonding layer on the first epitaxial wafer obtained in the step S3, and etching and exposing the first N-type electrode and the first P-type electrode to obtain a first intermediate;
Specifically, the first bonding layer 41 may be formed using PVD, PECVD, MOCVD or the like, but is not limited thereto. Preferably, PVD may be used to form the first bonding layer 41. After the growth of the first bonding layer 41 is completed, the first N-type electrode 2 and the first P-type electrode 3 are exposed through a photolithography etching process.
The first bonding layer 41 may be made of metal material such as Au, cu, ni, etc., but is not limited thereto. The first bonding layer 41 may also be made of a non-metal material. Preferably, the first bonding layer 41 is made of an insulating nonmetallic material, which can be used not only as a bonding layer but also as an insulating passivation layer, protecting the first intermediate 10, and improving the reliability of the Micro-LED chip. More preferably, the first bonding layer 41 has a stacked structure composed of one or two of an AlO x layer and an SiO x layer.
The thickness of the first bonding layer 41 is 0.8 μm to 3 μm, which is the same as or different from the thickness of the first P-type electrode 3. The upper surface of the first bonding layer 41 on the first P-type semiconductor layer 14 and the upper surface of the first P-type electrode 3 are preferably the same, i.e., the same as the upper surface of the first N-type electrode 2, so as to enhance structural stability.
After the formation of the first bonding layer 41 is completed, it is etched by a photolithography etching process to expose the first N-type electrode 2 and the first P-type electrode 3, resulting in the first intermediate 10. Preferably, referring to fig. 7, in one embodiment, the size of the opening is larger than the size of the first N-type electrode 2 and the first P-type electrode 3 to prevent the first N-type electrode 2 and the first P-type electrode 3 from being shorted when the first bonding layer 41 of some conductive material is used.
S5: providing a second epitaxial wafer;
Wherein, referring to fig. 8, the second epitaxial wafer 5 includes a second substrate 51 and a second N-type semiconductor layer 52, a second MQW layer 53, and a second P-type semiconductor layer 54 sequentially stacked on the second substrate 51. The second substrate 51 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. The second N-type semiconductor layer 52 may be an N-type GaN layer, an N-type AlGaN layer, an N-type GaAs layer, but is not limited thereto. The second MQW layer 53 may be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The second P-type semiconductor layer 54 may be a P-type GaN layer, a P-type AlGaN layer, a P-type GaAs layer, but is not limited thereto. Preferably, the second substrate 51 is a sapphire substrate, which is more easily peeled off at a later stage.
Preferably, in one embodiment of the present invention, the second epitaxial wafer 5 further includes a second U-shaped semiconductor layer 55 disposed between the second substrate 51 and the second N-shaped semiconductor layer 52. More preferably, the second epitaxial wafer may further include one or more of a buffer layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer, which are common in the art, but is not limited thereto.
S6: forming an intermediate electrode on the second P-type semiconductor layer;
specifically, the intermediate electrode 6 may be formed by PVD, evaporation, or the like, but is not limited thereto. Referring to fig. 8 and 9, the composition of the intermediate electrode 6 may be the same as or different from the composition of the first N-type electrode 2 and the first P-type electrode 3, but is not limited thereto.
Preferably, in one embodiment, referring to fig. 9, the intermediate electrode 6 includes a third ohmic contact layer 61, a third clad layer 62, and a third bonding layer 24 sequentially stacked; based on this structure, the intermediate electrode 6 can form good bonding and electrical contact with the first N-type electrode 2.
Specifically, the third ohmic contact layer 61 is a stacked structure formed by one or more of a Cr layer, a Ni layer, and a Ti layer, and has a thickness of 25 a to 200 a; the third coating layer 62 has a laminated structure composed of one or more of a Ti layer, a Ni layer and a Pt layer, and has a thickness of 300nm to 1500nm; the third bonding layer 24 is a laminated structure composed of one or more of Ni layer, in layer, cu layer, and Au layer, and has a thickness of 1 μm to 5 μm.
Preferably, in one embodiment, the difference between the widths of the first N-type electrode 2 and the intermediate electrode 6 is controlled to be less than or equal to 10 μm, so as to further improve the connection stability of the first epitaxial wafer 1 and the second epitaxial wafer 5. More preferably, the difference between the widths of the first N-type electrode 2 and the intermediate electrode 6 is 0.5 μm to 5 μm. The first N-type electrode 2 and the intermediate electrode 6 have the same cross-sectional shape, and the width thereof means the width of the cross section. When the cross section is circular, the radius is the same; the cross section is the largest side length when it is other polygons, but is not limited thereto.
S7: forming a second bonding layer on the second epitaxial wafer obtained in the step S6, and etching to expose the intermediate electrode to obtain a second intermediate;
Specifically, the second bonding layer 42 may be formed using PVD, PECVD, MOCVD or the like, but is not limited thereto. Preferably, the second bonding layer 42 may be formed using PVD. After the second bonding layer 42 is grown, the intermediate electrode 6 is exposed by a photolithography etching process.
The second bonding layer 42 may be made of metal, such as Au, cu, ni, etc., but is not limited thereto. The second bonding layer 42 may also be a non-metallic material. Preferably, the second bonding layer 42 is made of an insulating nonmetallic material, which can be used not only as a bonding layer, but also as an insulating passivation layer, protecting the second intermediate 50, and improving the reliability of the Micro-LED chip. More preferably, the second bonding layer 42 is a stacked structure composed of one or two of an AlO x layer and an SiO x layer.
The thickness of the second bonding layer 42 is 0.8 μm to 3 μm, which is the same as the thickness of the intermediate electrode 6. The upper surface of the second bonding layer 42 on the second P-type semiconductor layer 54 is preferably flush with the upper surface of the intermediate electrode 6 to enhance structural stability.
After the second bonding layer 42 is formed, an opening is formed through a photolithography etching process, exposing the intermediate electrode 6, and obtaining a second intermediate 50. Preferably, referring to fig. 8, in one embodiment, the size of the openings is larger than the size of the intermediate electrode 6.
It should be noted that, steps S1 to S4 and steps S5 to S7 are not sequential, S1 to S4 may be implemented first, and then S5 to S7 may be implemented; steps S5 to S7 may be performed first, and steps S1 to S4 may be performed later; steps S1 to S4 and steps S5 to S7 may be performed simultaneously.
S8: bonding the first intermediate and the second intermediate, and stripping the second substrate to expose the second N-type semiconductor layer to obtain an intermediate chip;
Specifically, the first intermediate 10 and the second intermediate 50 may be bonded by eutectic bonding, anodic bonding, thermocompression bonding, direct bonding, or the like to form the intermediate chip 40, but is not limited thereto. Preferably, the two are bonded by thermocompression bonding. Referring to fig. 10, after bonding, the intermediate electrode 6 is electrically connected to the first N-type electrode 2.
After the bonding is completed, the second substrate 51 is peeled off, and more preferably, the second substrate 51 and the second U-shaped semiconductor layer 55 are peeled off, whereby the light emitting efficiency can be improved by peeling off the second U-shaped semiconductor layer 55 having a high dislocation density.
Preferably, in one embodiment of the present invention, step S8 includes:
s81: bonding the first N-type electrode and the intermediate electrode;
Specifically, the first N-type electrode 2 and the intermediate electrode 6 are bonded by eutectic bonding. Wherein the bonding temperature is 200-350 ℃, the bonding pressure is 0.5-4 MPa, and the bonding time is 7-25 min.
S82: bonding the first bonding layer and the second bonding layer;
Specifically, the first bonding layer 41 and the second bonding layer 42 are bonded by thermocompression bonding. Wherein the bonding temperature is 350-500 ℃, the bonding pressure is 1-7 kN, and the bonding time is 10-30 min.
By bonding the first N-type electrode 2 and the intermediate electrode 6 first and then bonding the first bonding layer 41 and the second bonding layer 42, good electrical contact between the first N-type electrode 2 and the intermediate electrode 6 is ensured, and stability after bonding is also improved.
S83: stripping the second substrate by laser, and removing the second U-shaped semiconductor layer by alkali liquor corrosion;
Specifically, the second U-shaped semiconductor layer 55 is removed by adopting KOH solution for corrosion, wherein the corrosion temperature is 50-60 ℃ and the corrosion time is 4-8 min. The KOH solution is a KOH aqueous solution, and the concentration of KOH is 20-40 wt%.
S84: removing the damaged surface of the second N-type semiconductor layer by dry etching;
Since the second N-type semiconductor layer 52 is inevitably damaged by the KOH solution, the damaged surface is removed by dry etching, wherein the etching thickness is 0.3 μm to 0.8 μm.
Preferably, the second N-type semiconductor layer 52 is etched using an ICP etching process. Wherein the upper power (i.e., the plasma source power) is 800W to 1000W, preferably 850W to 920W. The lower power (i.e., bias power) is 100W to 300W, preferably 200W to 300W.
The gas adopted in etching is a mixed gas of Ar, BCl 3 and Cl 2, and the flow rate of Ar is 10 sccm-20 sccm, preferably 12 sccm-18 sccm; the flow rate of the BCl 3 is 10 sccm-20 sccm, preferably 12 sccm-16 sccm; the flow rate of Cl 2 is 250sccm to 400sccm, preferably 280sccm to 350sccm.
S9: forming a first P-type hole exposing the first P-type electrode on the intermediate chip;
Specifically, the first P-type hole 43 may be formed through a photolithography etching process, referring to fig. 11, and the first P-type hole 43 penetrates the second N-type semiconductor layer 52, the second MQW layer 53, the second P-type semiconductor layer 54, and the second bonding layer 42 until the first P-type electrode 3 is exposed. The etching barrier layer 34 of the first P-type electrode 3 effectively protects the first P-type electrode 3 from damage.
S10: forming a passivation layer on the intermediate chip obtained in the step S9, and forming a second N-type hole and a second P-type hole by opening holes above the second N-type semiconductor layer and the first P-type electrode respectively;
Specifically, the passivation layer 7 may be formed by PVD, PECVD, MOCVD or the like, but is not limited thereto. Preferably, the passivation layer 7 is formed by PECVD. The passivation layer 7 may be a stacked structure composed of one or more of an AlO x layer, a SiO x layer and a SiN x layer, and the thickness of the passivation layer 7 is 500-5000A. The passivation layer 7 covers the sidewalls of the first P-type hole 43. The second P-type electrode 9 formed later is prevented from conducting with the second N-type electrode 8.
After the passivation layer 7 is formed, a second N-type hole 71 and a second P-type hole 72 are formed by a photolithography etching process, wherein the second N-type hole 71 is disposed above the second N-type semiconductor layer 52. The second P-type hole 72 is provided above the first P-type electrode 3 in the first P-type hole 43.
S11: forming a second N-type electrode and a second P-type electrode on the intermediate chip obtained in the step S10;
Specifically, the second N-type electrode 8 and the second P-type electrode 9 may be formed by PVD, evaporation, or the like, but are not limited thereto. The second N-type electrode 8 and the second P-type electrode 9 have the same or different compositions. Preferably the same, they may all consist of one or more of Al layer, cr layer, pt layer, ag layer, au layer, as is common in the art.
Specifically, referring to fig. 12, the second N-type electrode 8 is connected to the second N-type semiconductor layer 52 through the second N-type hole 71. The second P-type electrode 9 is connected to the first P-type electrode 3 through the second P-type hole 72. Based on the electrode connection structure, the distribution of current can be optimized, and the luminous efficiency is improved.
S12: and stripping the first substrate to obtain a finished product of the high-voltage Micro-LED chip.
Specifically, the first substrate 11 may be removed by laser lift-off, but is not limited thereto. Preferably, in one embodiment, when the first substrate 11 is removed, the first U-shaped semiconductor layer 15 is also etched away. The high-voltage Micro-LED chip prepared by the preparation method provided by the invention has the advantages that the working voltage is high, the current distribution is optimized, and the luminous efficiency is improved.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (10)
1. The preparation method of the high-voltage Micro-LED chip is characterized by comprising the following steps of:
S1, providing a first epitaxial wafer, wherein the first epitaxial wafer comprises a first substrate, and a first N-type semiconductor layer, a first MQW layer and a first P-type semiconductor layer which are sequentially laminated on the first substrate;
S2, forming a first N-type hole etched to the first N-type semiconductor layer on the first epitaxial wafer;
s3, forming a first N-type electrode and a first P-type electrode on the first epitaxial wafer obtained in the step S2, wherein the first N-type electrode is connected with the first N-type semiconductor layer through the first N-type hole;
s4, forming a first bonding layer on the first epitaxial wafer obtained in the step S3, and etching and exposing the first N-type electrode and the first P-type electrode to obtain a first intermediate;
s5, providing a second epitaxial wafer, wherein the second epitaxial wafer comprises a second substrate, and a second N-type semiconductor layer, a second MQW layer and a second P-type semiconductor layer which are sequentially laminated on the second substrate;
S6, forming an intermediate electrode on the second P-type semiconductor layer;
s7, forming a second bonding layer on the second epitaxial wafer obtained in the step S6, and etching to expose the intermediate electrode to obtain a second intermediate;
s8, bonding the first intermediate and the second intermediate, and stripping the second substrate to expose the second N-type semiconductor layer to obtain an intermediate chip; wherein, after bonding, the intermediate electrode and the first N-type electrode form electric connection;
s9, forming a first P-type hole exposing the first P-type electrode on the middle chip;
s10, forming a passivation layer on the intermediate chip obtained in the step S9, and forming a second N-type hole and a second P-type hole by respectively forming holes above the second N-type semiconductor layer and the first P-type electrode;
S11, forming a second N-type electrode and a second P-type electrode on the intermediate chip obtained in the step S10, wherein the second N-type electrode is connected with the second N-type semiconductor layer through the second N-type hole, and the second P-type electrode is connected with the first P-type electrode through the second P-type hole;
s12, stripping the first substrate to obtain a finished product of the high-voltage Micro-LED chip.
2. The method of manufacturing a high voltage Micro-LED chip of claim 1, wherein the first N-type electrode and the intermediate electrode each comprise a third bonding layer to bond the first N-type electrode and the intermediate electrode;
the difference between the widths of the first N-type electrode and the intermediate electrode is less than or equal to 10 mu m.
3. The method for manufacturing a high voltage Micro-LED chip according to claim 2, wherein step S8 comprises:
S81, bonding the first N-type electrode and the intermediate electrode, wherein the bonding temperature is 200-350 ℃, the bonding pressure is 0.5-4 MPa, and the bonding time is 7-25 min;
s82, bonding the first bonding layer and the second bonding layer, wherein the bonding temperature is 350-500 ℃, the bonding pressure is 1-7 kN, and the bonding time is 10-30 min;
S83, stripping the second substrate by laser, and removing the second U-shaped semiconductor layer by alkali liquor corrosion;
s84, removing the damaged surface of the second N-type semiconductor layer by dry etching, wherein the etching thickness is 0.3-0.8 mu m.
4. The method of manufacturing a high voltage Micro-LED chip of claim 1, wherein the upper surface of the first bonding layer on the first P-type semiconductor layer, the upper surface of the first P-type electrode and the upper surface of the first N-type electrode are flush;
The upper surface of the second bonding layer on the second P-type semiconductor layer is flush with the upper surface of the intermediate electrode.
5. The method of manufacturing a high voltage Micro-LED chip according to claim 1, wherein the first bonding layer and the second bonding layer are made of an insulating material.
6. The method for manufacturing a high-voltage Micro-LED chip according to claim 1, wherein the first bonding layer is a laminated structure composed of one or two of an AlO x layer and a SiO x layer, and the thickness of the first bonding layer is 0.8 μm to 3 μm;
The second bonding layer is of a laminated structure formed by one or two of an AlO x layer and a SiO x layer, and the thickness of the second bonding layer is 0.8-3 mu m.
7. The method of manufacturing a high voltage Micro-LED chip of claim 1, wherein the first N-type electrode comprises a first ohmic contact layer, a first reflective layer, a first cladding layer, and a third bonding layer, which are sequentially stacked;
the first ohmic contact layer is a laminated structure formed by one or more of a Cr layer, a Ni layer and a Ti layer, and the thickness of the first ohmic contact layer is 25A-200A;
The first reflecting layer is a laminated structure formed by one or two of an Al layer and an Ag layer, and the thickness of the first reflecting layer is 500A-2500A;
the first coating layer is of a laminated structure formed by one or more of a Ti layer, a Ni layer and a Pt layer, and the thickness of the first coating layer is 300-1500 nm;
The third bonding layer is a laminated structure composed of one or more of a Ni layer, an In layer, a Cu layer and an Au layer, and the thickness of the third bonding layer is 1-5 mu m;
The first P-type electrode comprises a second ohmic contact layer, a second reflecting layer, a second cladding layer and an etching barrier layer which are sequentially laminated;
the second ohmic contact layer is a laminated structure formed by one or more of a Cr layer, a Ni layer and a Ti layer, and the thickness of the second ohmic contact layer is 25A-200A;
The second reflecting layer is a laminated structure formed by one or two of an Al layer and an Ag layer, and the thickness of the second reflecting layer is 500A-2500A;
The second coating layer is a laminated structure formed by one or more of a Ti layer, a Ni layer and a Pt layer, and the thickness of the second coating layer is 300-1500 nm;
The etching barrier layer is a laminated structure formed by one or two of a Pt layer and an Au layer, and the thickness of the etching barrier layer is 2000A-5000A.
8. The method of manufacturing a high voltage Micro-LED chip of claim 1, wherein the intermediate electrode comprises a third ohmic contact layer, a third clad layer, and a third bonding layer sequentially stacked;
the third ohmic contact layer is a laminated structure formed by one or more of a Cr layer, a Ni layer and a Ti layer, and the thickness of the third ohmic contact layer is 25A-200A;
the third coating layer is of a laminated structure formed by one or more of a Ti layer, a Ni layer and a Pt layer, and the thickness of the third coating layer is 300-1500 nm;
The third bonding layer is a laminated structure composed of one or more of a Ni layer, an In layer, a Cu layer and an Au layer, and the thickness of the third bonding layer is 1-5 mu m.
9. The method for manufacturing a high-voltage Micro-LED chip according to claim 1, wherein the passivation layer is a laminated structure composed of one or two of an AlO x layer and a SiO x layer, and the thickness of the passivation layer is 500 a-5000 a.
10. The high-voltage Micro-LED chip according to any one of claims 1 to 9, wherein the high-voltage Micro-LED chip is manufactured by a method for manufacturing the same.
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