CN114551675A - Red light micro light-emitting diode chip and preparation method thereof - Google Patents

Red light micro light-emitting diode chip and preparation method thereof Download PDF

Info

Publication number
CN114551675A
CN114551675A CN202111651379.9A CN202111651379A CN114551675A CN 114551675 A CN114551675 A CN 114551675A CN 202111651379 A CN202111651379 A CN 202111651379A CN 114551675 A CN114551675 A CN 114551675A
Authority
CN
China
Prior art keywords
layer
electrode
semiconductor layer
substrate
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111651379.9A
Other languages
Chinese (zh)
Inventor
兰叶
王江波
朱广敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HC Semitek Zhejiang Co Ltd
Original Assignee
HC Semitek Zhejiang Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HC Semitek Zhejiang Co Ltd filed Critical HC Semitek Zhejiang Co Ltd
Priority to CN202111651379.9A priority Critical patent/CN114551675A/en
Publication of CN114551675A publication Critical patent/CN114551675A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The present disclosure provides a red light micro light emitting diode chip and a preparation method thereof, which belongs to the technical field of photoelectron manufacturing. The chip includes: the method comprises the following steps: the device comprises a substrate, an epitaxial structure, a first passivation layer, a metal enhancement layer, a first electrode and a second electrode; the epitaxial structure comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially laminated on the substrate, wherein a groove for exposing the first semiconductor layer is formed in the surface of the second semiconductor layer, a first electrode is positioned on the surface of the first semiconductor layer and positioned on the bottom surface of the groove, and a second electrode is positioned on the surface of the second semiconductor layer; the first passivation layer at least covers the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer and the second electrode, the metal enhancement layer is positioned on the first passivation layer, and the orthographic projection of the metal enhancement layer on the substrate is positioned in the orthographic projection of the first passivation layer on the substrate. The embodiment of the disclosure can effectively relieve the problem of chip crack failure caused by stress generated by welding.

Description

Red light micro light-emitting diode chip and preparation method thereof
Technical Field
The disclosure relates to the technical field of photoelectron manufacturing, in particular to a red light micro light-emitting diode chip and a preparation method thereof.
Background
Micro Light Emitting Diode (Micro LED) refers to an ultra-small LED with a side length of 10 μm to 100 μm, and a red Micro LED is a red LED. The micro light emitting diode has small volume, can be arranged more densely to greatly improve the resolution, has self-luminous characteristic, and has the characteristics of high brightness, high contrast, high reactivity and power saving.
In the related art, a red micro led chip generally includes a substrate, an epitaxial structure, a first electrode, a second electrode, a passivation layer, a first pad block, and a second pad block. The epitaxial structure is stacked on the substrate, the first electrode and the second electrode are arranged on one side, far away from the substrate, of the epitaxial structure, and the passivation layer is located on the epitaxial structure and covers the two electrodes. The first welding point block and the second welding point block are positioned on the passivation layer and are respectively connected with the two electrodes through the through holes on the passivation layer.
Two welding point blocks are usually manufactured and formed on the surface of the passivation layer by adopting a laser welding mode, however, the situation that the temperature is sharply increased and decreased exists during the laser welding, so that stress is generated in a chip, and the epitaxial structure in the chip is easily cracked, so that the problem of chip failure is caused.
Disclosure of Invention
The embodiment of the disclosure provides a red light micro light emitting diode chip and a preparation method thereof, which can effectively relieve the problem of chip crack failure caused by stress generated by welding. The technical scheme is as follows:
in one aspect, an embodiment of the present disclosure provides a red light micro light emitting diode chip, where the red light micro light emitting diode chip includes: the device comprises a substrate, an epitaxial structure, a first passivation layer, a metal enhancement layer, a first electrode and a second electrode; the epitaxial structure comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially laminated on the substrate, wherein a groove for exposing the first semiconductor layer is formed in the surface of the second semiconductor layer, the first electrode is positioned on the surface of the first semiconductor layer and is positioned on the bottom surface of the groove, and the second electrode is positioned on the surface of the second semiconductor layer; the first passivation layer at least covers the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer and the second electrode, the metal enhancement layer is positioned on the first passivation layer, and the orthographic projection of the metal enhancement layer on the substrate is positioned in the orthographic projection of the first passivation layer on the substrate.
Optionally, the metal enhancement layer includes a first Ti layer, a first Ni layer, a Pt layer, a second Ni layer, and a second Ti layer sequentially stacked on the surface of the first passivation layer, and a thickness of the Pt layer is not less than half of a total thickness of the metal enhancement layer.
Optionally, the first Ti layer has a thickness of 400 to 600 angstroms, the first Ni layer has a thickness of 800 to 1200 angstroms, the Pt layer has a thickness of 4900 to 5100 angstroms, the second Ni layer has a thickness of 800 to 1200 angstroms, and the second Ti layer has a thickness of 400 to 600 angstroms.
Optionally, the bottom surface of the groove has a protruding structure, and the protruding structure is connected to the side wall of the groove close to the second electrode.
Optionally, protruding structure includes a plurality of ladder blocks, and is a plurality of the ladder block is arranged in proper order along keeping away from the direction of the lateral wall of recess, keeping away from in the direction of the lateral wall of recess, the ladder block is in orthographic projection's on the lateral wall of recess area reduces gradually.
Optionally, there are a plurality of the protruding structures, and the plurality of the protruding structures are arranged at intervals in a direction parallel to the substrate.
Optionally, the bottom surface of the groove far away from the protruding structure is a stepped surface, and the stepped surface is connected with the surface of the groove and the side wall of the groove respectively.
Optionally, the red micro led chip further includes a second passivation layer, where the second passivation layer is located on the metal enhancement layer, and an orthogonal projection of the second passivation layer on the substrate coincides with an orthogonal projection of the first passivation layer on the substrate.
Optionally, the red micro light emitting diode chip further includes: the first welding spot block and the second welding spot block are both positioned on the surface of the second passivation layer; the first welding spot block is connected with the first electrode through a first through hole, the second welding spot block is connected with the second electrode through a second through hole, and the first welding spot block and the second welding spot block are insulated from the metal enhancement layer.
On the other hand, the embodiment of the present disclosure further provides a method for manufacturing a red light micro light emitting diode chip, where the method includes: providing a substrate; forming an epitaxial structure on the substrate, wherein the epitaxial structure comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially laminated on the substrate, and the surface of the second semiconductor layer is provided with a groove for exposing the first semiconductor layer; forming a first electrode and a second electrode on the surface of the epitaxial structure, wherein the first electrode is positioned on the surface of the first semiconductor layer and on the bottom surface of the groove, and the second electrode is positioned on the surface of the second semiconductor layer; forming a first passivation layer and a metal enhancement layer on the epitaxial structure, wherein the first passivation layer at least covers the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer and the second electrode, the metal enhancement layer is located on the first passivation layer, and the orthographic projection of the metal enhancement layer on the substrate is located in the orthographic projection of the first passivation layer on the substrate.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure at least comprise:
in the red light micro light-emitting diode provided by the embodiment of the disclosure, an epitaxial structure is arranged on a substrate, a groove for exposing a first semiconductor layer is arranged on a second semiconductor layer in the epitaxial structure, a first electrode is arranged in the groove and connected with the first semiconductor layer, a second electrode is arranged on the second semiconductor layer, a first passivation layer is covered on the epitaxial structure, the first passivation layer at least covers the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer and the second electrode, a metal enhancement layer is further covered outside the first passivation layer, and the orthographic projection of the metal enhancement layer on the substrate is positioned in the orthographic projection of the first passivation layer on the substrate, so that the metal enhancement layer is prevented from being connected with the two electrodes, and the two electrodes are prevented from being short-circuited. The metal enhancement layer is arranged on the surface of the epitaxial structure, namely, the strength of the epitaxial structure below the metal enhancement layer can be effectively reinforced, so that the metal enhancement layer can resist stress when the temperature is changed violently to generate stress in the chip due to laser welding, and the epitaxial structure in the chip is effectively prevented from cracking and losing efficacy.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a metal reinforcement layer provided in an embodiment of the present disclosure;
fig. 3 is a partial structural schematic view of an epitaxial structure provided by an embodiment of the present disclosure;
FIG. 4 is a top view of a transition step provided by embodiments of the present disclosure;
fig. 5 is a cross-sectional view of another epitaxial structure provided by embodiments of the present disclosure;
fig. 6 is a partial structural schematic view of another epitaxial structure provided by an embodiment of the present disclosure;
fig. 7 is a top view of a micro light emitting diode chip according to an embodiment of the disclosure;
fig. 8 is a flowchart of a method for manufacturing a red micro light emitting diode chip according to an embodiment of the present disclosure;
fig. 9 is a schematic view illustrating a manufacturing process of a red micro light emitting diode chip according to an embodiment of the present disclosure;
fig. 10 is a schematic view of a manufacturing process of a red micro light emitting diode chip according to an embodiment of the present disclosure.
The various symbols in the figure are illustrated as follows:
10. a substrate;
20. an epitaxial structure; 201. a first semiconductor layer; 202. a multiple quantum well layer; 203. a second semiconductor layer;
31. a first passivation layer; 32. a metal reinforcement layer; 321. a first Ti layer; 322. a first Ni layer; 323. a Pt layer; 324. a second Ni layer; 325. a second Ti layer; 33. a second passivation layer;
41. a first electrode; 42. a second electrode;
51. a groove; 53. a raised structure; 530. a step block; 531. a step block; 532. a step surface;
61. a first via hole; 62. a second via hole;
71. a first solder joint block; 72. a second solder joint block;
80. and a protective layer.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a micro light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 1, the red micro led chip includes: the epitaxial structure comprises a substrate 10, an epitaxial structure 20, a first passivation layer 31, a metal enhancement layer 32, a first electrode 41 and a second electrode 42.
As shown in fig. 1, the epitaxial structure 20 includes a first semiconductor layer 201, a multiple quantum well layer 202, and a second semiconductor layer 203 sequentially stacked on a substrate 10, a surface of the second semiconductor layer 203 has a groove 51 exposing the first semiconductor layer 201, a first electrode 41 is located on the surface of the first semiconductor layer 201 and on a bottom surface of the groove 51, and a second electrode 42 is located on a surface of the second semiconductor layer 203.
As shown in fig. 1, the first passivation layer 31 covers at least the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203, and the second electrode 42, the metal enhancement layer 32 is located on the first passivation layer 31, and an orthographic projection of the metal enhancement layer 32 on the substrate 10 is located within an orthographic projection of the first passivation layer 31 on the substrate 10.
In the red micro light emitting diode provided by the embodiment of the disclosure, the epitaxial structure 20 is disposed on the substrate 10, the second semiconductor layer 203 in the epitaxial structure 20 has a groove 51 exposing the first semiconductor layer 201, the first electrode 41 is disposed in the groove 51 and connected to the first semiconductor layer 201, the second electrode 42 is disposed on the second semiconductor layer 203, the epitaxial structure 20 is covered with a first passivation layer 31, the first passivation layer 31 at least covers the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203 and the second electrode 42, the first passivation layer 31 is further covered with a metal enhancement layer 32, and an orthographic projection of the metal enhancement layer 32 on the substrate 10 is located in an orthographic projection of the first passivation layer 31 on the substrate 10, so that the metal enhancement layer 32 is prevented from being connected to two electrodes and causing a short circuit between the two electrodes. Since the metal enhancement layer 32 is disposed on the surface of the epitaxial structure 20, that is, the strength of the underlying epitaxial structure 20 can be effectively reinforced by the metal enhancement layer 32, when the laser welding causes a severe temperature change to generate stress in the chip, the metal enhancement layer 32 can resist the stress, and the crack failure of the epitaxial structure 20 in the chip can be effectively prevented.
Fig. 2 is a schematic structural diagram of a metal reinforcement layer 32 provided in the embodiment of the present disclosure. As shown in fig. 2, the metal enhancement layer 32 includes a first Ti layer 321, a first Ni layer 322, a Pt layer 323, a second Ni layer 324, and a second Ti layer 325, which are sequentially stacked on the surface of the first passivation layer 31, and the thickness of the Pt layer 323 is not less than one-half of the total thickness of the metal enhancement layer 32.
Wherein the first Ti layer 321 is used to improve the adhesion between the first passivation layer 31 and the metal enhancement layer 32; the first Ni layer 322 serves to improve adhesion between the first Ti layer 321 and the Pt layer 323, and may also increase toughness of the metal reinforcing layer 32; the Pt layer 323 serves to enhance the strength of the metal enhancement layer 32, i.e., to resist stress primarily through the Pt layer 323; the second Ni layer 324 serves to improve adhesion between the second Ti layer 325 and the Pt layer 323, and may also increase toughness of the metal reinforcing layer 32; the second Ti layer 325 serves to improve adhesion between the second passivation layer 33 and the metal reinforcement layer 32.
In the above implementation, the thickness of the Pt layer 323 is not less than half of the total thickness of the metal enhancement layer 32, i.e., the Pt layer 323 occupies at least half of the total thickness of the metal enhancement layer 32. Since the Pt layer 323 is for resisting stress, it is ensured that the thickness of the Pt layer 323 is large enough to ensure the effect of the metal reinforcement layer 32 against stress.
Illustratively, the first Ti layer 321 has a thickness of 400 to 600 angstroms. As an example, the first Ti layer 321 has a thickness of 500 angstroms.
Illustratively, the thickness of first Ni layer 322 is 800 angstroms to 1200 angstroms. As an example, the thickness of first Ni layer 322 is 1000 angstroms.
Illustratively, the thickness of the Pt layer 323 is 4900 angstroms to 5100 angstroms. By way of example, the thickness of the Pt layer 323 is 5000 angstroms.
Illustratively, the thickness of the second Ni layer 324 is 800 angstroms to 1200 angstroms. By way of example, the second Ni layer 324 is 1000 angstroms thick.
As an example, the second Ti layer 325 has a thickness of 400 to 600 angstroms. As an example, the second Ti layer 325 is 500 angstroms thick.
Alternatively, as shown in fig. 1, the bottom surface of the groove 51 has a convex structure 53, and the convex structure 53 is connected to the sidewall of the groove 51 near the second electrode 42.
In the above implementation, the convex structure 53 is formed on the bottom surface of the groove 51. Therefore, the vertical plane connecting the surface of the second semiconductor and the bottom surface of the groove 51 on the epitaxial structure 20 can form a stepped zigzag surface, so that the transmission path of the stress can be prolonged to release the stress at the position of the vertical plane, and the surface of the epitaxial structure 20 is effectively prevented from cracking.
Fig. 3 is a partial structural schematic diagram of an epitaxial structure 20 provided in an embodiment of the present disclosure. Fig. 4 is a top view of a protrusion 53 provided in an embodiment of the present disclosure. As shown in fig. 3 and 4, the protruding structure 53 includes a plurality of step blocks 531, the step blocks 531 are sequentially arranged along a direction away from the side wall of the groove 51, and an area of an orthographic projection of the step blocks 531 on the side wall of the groove 51 is gradually reduced in the direction away from the side wall of the groove 51.
In the above implementation, the protruding structure 53 includes a plurality of step blocks 531 arranged in sequence, and the area of each step block 531 arranged in sequence is gradually reduced. The protruding structure 53 obtained by stacking the plurality of step blocks 531 in this way can form a step-shaped structure, that is, the cross section of the protruding structure 53 in the direction parallel to the substrate 10 is a step-shaped cross section, which can extend the transmission path of the stress to release the stress at the position of the vertical plane, thereby avoiding the occurrence of cracks on the surface of the epitaxial structure 20.
Illustratively, as shown in fig. 4, the protruding structure 53 includes three step blocks 531, the three step blocks 531 are sequentially arranged in a direction away from the side wall of the groove 51, and each step block 531 is located in a middle portion of a previous step block 531. In this way, the protruding structure 53 forms a symmetrical step structure, and forms a step-shaped cross section, so as to further extend the transmission path of the stress, so as to release the stress at the position of the vertical plane, and avoid the occurrence of cracks on the surface of the epitaxial structure 20.
Alternatively, as shown in fig. 3, there are a plurality of the convex structures 53, and the plurality of convex structures 53 are arranged at intervals in a direction parallel to the substrate 10.
By arranging the plurality of convex structures 53 arranged at intervals, the cross sections of the convex structures 53 in the direction parallel to the substrate 10 are intermittently arranged block-shaped cross sections, and compared with the long-strip-shaped and non-separated convex structures, the stress transmission path can be extended, so that the stress at the position of the vertical plane is released, and the surface of the epitaxial structure 20 is prevented from cracking.
As an example, in the embodiment of the present disclosure, as shown in fig. 3, the protruding structure 53 includes two protruding structures 53 arranged at intervals in a direction parallel to the substrate 10.
Fig. 5 is a cross-sectional view of another epitaxial structure 20 provided by embodiments of the present disclosure. As shown in fig. 5, the bottom surface of the protruding structure 53 away from the groove 51 is a stepped surface 532, and the stepped surface 532 is connected to the surface of the groove 51 and the side wall of the groove 51.
The bottom surface of the protruding structure 53 far away from the groove 51 is set to be the stepped surface 532, so that the vertical plane of the surface of the second semiconductor and the bottom surface of the groove 51 is connected to the epitaxial structure 20, a more dense stepped zigzag surface can be formed, the stress transmission path can be prolonged, the stress at the position of the vertical plane is released, and the surface of the epitaxial structure 20 is effectively prevented from cracking.
As an example, as shown in fig. 3, the protruding structure 53 includes a plurality of step blocks 530, and the structure of each step block 530 may be a protruding structure including a plurality of step blocks 531 as illustrated in fig. 3. Therefore, the convex structures 53 can form a step-shaped zigzag surface in the direction perpendicular to the substrate 10 or in the direction parallel to the substrate 10, so as to extend the transmission path of the stress and facilitate the stress release.
As an example, fig. 6 is a partial structural schematic diagram of another epitaxial structure provided in the embodiment of the present disclosure. As shown in fig. 6, the protruding structure 53 includes a plurality of step blocks 530, and each step block 530 may be a rectangular block shape, i.e., a plurality of step blocks 530 are combined to form the protruding structure 53 having a step shape. The structure is simpler, and the processing and the preparation are convenient.
Optionally, as shown in fig. 1, the red micro light emitting diode chip further includes a second passivation layer 33, the second passivation layer 33 is located on the metal enhancement layer 32, and an orthogonal projection of the second passivation layer 33 on the substrate 10 coincides with an orthogonal projection of the first passivation layer 31 on the substrate 10. The metal enhancement layer 32 is coated by the first passivation layer 31 and the second passivation layer 33, so that the problem that the metal enhancement layer 32 is exposed and connected with an electrode to cause short circuit is avoided.
Illustratively, the second passivation layer 33 may be a DBR (Distributed Bragg reflector) layer including a plurality of SiO layers alternately stacked periodically2Layer and TiO2And (3) a layer. And the number of DBR layers may be between 20 and 50 cycles. For example, the number of DBR layers cycles is 36.
Wherein, SiO in the DBR layer2The layer may be 800 to 1200 angstroms thick, TiO2The thickness of the layer may be 500 angstroms to 900 angstroms.
The DBR layer, in addition to having a passivation function, is also used to reflect light emitted from the multiple quantum well layer 202 to the second passivation layer 33 to the substrate 10, thereby improving the light extraction effect.
Optionally, as shown in fig. 1, the red micro led chip further includes: first and second pad blocks 71 and 72, and the first and second pad blocks 71 and 72 are located on a surface of the second passivation layer 33.
As shown in fig. 1, the surface of the second passivation layer 33 has a first via 61 exposing the first electrode 41, the surface of the second passivation layer 33 has a second via 62 exposing the second electrode 42, the first pad block 71 is connected to the first electrode 41 through the first via 61, the second pad block 72 is connected to the second electrode 42 through the second via 62, and both the first pad block 71 and the second pad block 72 are insulated from the metal reinforcement layer 32.
The electrical connection of the first electrode 41 is facilitated by providing the first pad block 71 connected to the first electrode 41 on the surface of the second passivation layer 33; a second pad bump 72 connected to the second electrode 42 is provided on the surface of the second passivation layer 33 to facilitate electrical connection of the second electrode 42.
Fig. 7 is a top view of a micro light emitting diode chip according to an embodiment of the disclosure. As shown in fig. 7, the first pad block 71 and the second pad block 72 are rectangular blocks, which increase the area and facilitate electrical conduction. And the first and second pad blocks 71 and 72 are spaced apart on the surface of the second passivation layer 33.
Optionally, substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, i.e., the substrate 10 is a transparent substrate 10. And the sapphire material is hard, the chemical property is stable, and the red light-emitting diode has good light-emitting effect and stability.
In the embodiment of the present disclosure, one of the first semiconductor layer 201 and the second semiconductor layer 203 is a p-type layer, and the other of the first semiconductor layer 201 and the second semiconductor layer 203 is an n-type layer.
As an example, the first semiconductor layer 201 is an n-type layer, and the first electrode 41 is an n-type electrode. The second semiconductor layer 203 is a p-type layer and the second electrode 42 is a p-type electrode.
Optionally, the first semiconductor layer 201 is an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
Alternatively, the multiple quantum well layer 202 includes AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately grown. Here, the mqw layer 202 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked, and the Al content of the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different.
As an example, in the embodiment of the present disclosure, the multiple quantum well layer 202 includes 5 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.
Alternatively, the thickness of the multiple quantum well layer 202 may be 150nm to 200 nm.
Optionally, the second semiconductor layer 203 is a p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
Fig. 8 is a flowchart of a method for manufacturing a red micro light emitting diode chip according to an embodiment of the present disclosure. The method is used for preparing the red light micro light-emitting diode chip shown in figure 1. As shown in fig. 8, the preparation method includes:
s11: a substrate 10 is provided.
S12: an epitaxial structure 20 is formed on the substrate 10.
The epitaxial structure 20 includes a first semiconductor layer 201, a multiple quantum well layer 202, and a second semiconductor layer 203 sequentially stacked on the substrate 10, and a surface of the second semiconductor layer 203 has a groove 51 exposing the first semiconductor layer 201.
S13: a first electrode 41 and a second electrode 42 are formed on the surface of the epitaxial structure 20.
Wherein a first electrode 41 and a second electrode 42 are formed on the surface of the epitaxial structure 20.
S14: a first passivation layer 31 and a metal enhancement layer 32 are formed on the epitaxial structure 20.
The first passivation layer 31 at least covers the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203 and the second electrode 42, the metal enhancement layer 32 is located on the first passivation layer 31, and an orthographic projection of the metal enhancement layer 32 on the substrate 10 is located in an orthographic projection of the first passivation layer 31 on the substrate 10.
In the red micro light emitting diode provided by the embodiment of the disclosure, the epitaxial structure 20 is disposed on the substrate 10, the second semiconductor layer 203 in the epitaxial structure 20 has a groove 51 exposing the first semiconductor layer 201, the first electrode 41 is disposed in the groove 51 and connected to the first semiconductor layer 201, the second electrode 42 is disposed on the second semiconductor layer 203, the epitaxial structure 20 is covered with a first passivation layer 31, the first passivation layer 31 at least covers the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203 and the second electrode 42, the first passivation layer 31 is further covered with a metal enhancement layer 32, and an orthographic projection of the metal enhancement layer 32 on the substrate 10 is located in an orthographic projection of the first passivation layer 31 on the substrate 10, so that the metal enhancement layer 32 is prevented from being connected to two electrodes and causing a short circuit between the two electrodes. Since the metal enhancement layer 32 is disposed on the surface of the epitaxial structure 20, that is, the strength of the underlying epitaxial structure 20 can be effectively reinforced by the metal enhancement layer 32, when the laser welding causes a severe temperature change to generate stress in the chip, the metal enhancement layer 32 can resist the stress, and the crack failure of the epitaxial structure 20 in the chip can be effectively prevented.
Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, i.e., the substrate 10 is a transparent substrate 10. And the sapphire material is hard, the chemical property is stable, and the red light micro light-emitting diode chip has good light-emitting effect and stability.
As shown in fig. 9, the epitaxial structure 20 grown in step S12 includes: a first semiconductor layer 201, a multiple quantum well layer 202, and a second semiconductor layer 203. The first semiconductor layer 201, the multiple quantum well layer 202, and the second semiconductor layer 203 are sequentially stacked on the substrate 10, and the surface of the second semiconductor layer 203 has a groove 51 exposing the first semiconductor layer 201.
The process of growing the epitaxial structure 20 may include: an etch stop layer, a first semiconductor, an AlInP carrier confinement layer, a multiple quantum well layer 202, a second semiconductor layer 203, and a window layer are sequentially grown on a GaAs substrate.
After the epitaxial structure 20 is grown on the GaAs substrate, the epitaxial structure 20 is bonded to the substrate 10 at a bonding temperature of 300 ℃, and the GaAs substrate is removed.
As shown in fig. 9, after the bonding is completed, the groove 51 exposing the first semiconductor layer 201 is etched on the surface of the second semiconductor layer 203, that is, the process of forming the epitaxial structure 20 on the substrate 10 in step S12 is completed.
The method specifically comprises the following steps: and etching a partial area of the second semiconductor layer 203 by adopting a dry etching mode until the first semiconductor layer 201 is exposed. The etching depth is 1 μm to 2 μm, for example, 1.5 μm.
Illustratively, the first semiconductor layer 201 is an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
Illustratively, the multiple quantum well layer 202 includes AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately grown. The mqw layer 202 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately, and the Al content of the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different.
As an example, in the embodiment of the present disclosure, the multiple quantum well layer 202 includes 5 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.
Alternatively, the thickness of the multiple quantum well layer 202 may be 150nm to 200 nm.
Optionally, the second semiconductor layer 203 is a p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
The second semiconductor layer 203 is a p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
Illustratively, the window layer may be a GaP layer having a thickness of 2 μm to 5 μm. As an example, the GaP layer is 3 μm.
Before forming the two electrodes in step S13 may include: and etching the transition step groove on the surface of the second semiconductor layer 203 by adopting a dry etching mode to form a convex structure 53 between the surface of the transition step groove and the surface of the groove 51.
Wherein, the transition step groove extends from the surface of the second semiconductor layer 203 to the first semiconductor layer 201, and the distance between the transition step groove and the substrate 10 is greater than the distance between the groove 51 and the substrate 10.
In step S13, as shown in fig. 10, forming the first electrode 41 and the second electrode 42 may include: and respectively processing the first electrode 41 and the second electrode 42 by negative glue stripping.
As shown in fig. 10, the second electrode 42 is located on the surface of the second semiconductor layer 203, and the first electrode 41 is located on the surface of the recess 51.
The first electrode 41 is formed by vapor deposition using gold and germanium as a base material, and the evaporation power is ensured when the gold and germanium alloy is evaporated, so that the evaporation time is prevented from exceeding 5 seconds, thereby preventing the alloy components from deviating, and annealing is performed. The second electrode 42 is evaporated by using gold beryllium as a base material.
As shown in fig. 10, the forming of the first passivation layer 31 on the epitaxial structure 20 in step S14 may include: a first passivation layer 31 is formed on the surfaces of the first semiconductor layer 201, the first electrode 41, the second semiconductor layer 203, the second electrode 42 and the groove 51, and a first via hole 61 exposing the first electrode 41 and a second via hole 62 exposing the second electrode 42 are formed on the first passivation layer 31 where current extraction is required.
Wherein the thickness of the first passivation layer 31 may be 2000 to 5000 angstroms. The thickness of the first passivation layer 31 is 3000 angstroms, for example.
Next, the metal reinforcement layer 32 is formed on the first passivation layer 31, and the metal reinforcement layer 32 is not disposed at the first and second via holes 61 and 62.
After step S14, a fabricated second passivation layer 33 may also be included, as shown in fig. 1.
Wherein the second passivation layer 33 may be a DBR layer including a plurality of periodically and alternately laminated SiO layers2Layer and TiO2And (3) a layer. And the number of DBR layer cycles may be between 20 and 50. For example, the number of DBR layers cycles is 36.
Wherein, SiO in the DBR layer2The layer may be 800 to 1200 angstroms thick, TiO2The thickness of the layer may be 500 angstroms to 900 angstroms.
The manufacturing of the second passivation layer 33 may further include: forming a first via hole 61 and a second via hole 62 on the second passivation layer 33, and forming a first pad block 71 on the surface of the second passivation layer 33 by photolithography, such that the first pad block 71 is connected to the first semiconductor layer 201 through the first via hole 61; then, a second pad block 72 is formed on the surface of the second passivation layer 33 using a photolithography method such that the second pad block 72 is connected to the second semiconductor layer 203 through the second via hole 62.
Wherein, both the two welding spot blocks can comprise a Cr layer, an Al layer, a Ti layer, a Ni layer and an Au layer which are sequentially laminated.
Illustratively, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 2000 angstroms, and the thickness of the Au layer is 90000 angstroms.
As shown in fig. 1, after forming the first pad blocks 71 and the second pad blocks 72, a protective layer 80 may be formed on the surface of the second passivation layer 33, and the protective layer 80 extends from the surface of the second passivation layer 33 to the substrate 10.
Illustratively, in the embodiments of the present disclosure, the protective layer 80 may be a silicon oxide layer having a thickness of 2000 angstroms.
It should be noted that after the passivation layer 80 is grown on the surface of the second passivation layer 33, a photolithography technique may be used to etch through holes on the surface of the passivation layer 80 to expose the pad blocks, so as to facilitate electrical connection.
And finally, thinning the sapphire substrate 10 to the final thickness of 80 microns, and then carrying out invisible cutting and scribing on the sapphire, wherein the invisible cutting and scribing can well reduce the loss of brightness. Then, testing to obtain the micro light-emitting diode chip.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims (10)

1. The red light micro light emitting diode chip is characterized by comprising: the epitaxial structure comprises a substrate (10), an epitaxial structure (20), a first passivation layer (31), a metal enhancement layer (32), a first electrode (41) and a second electrode (42);
the epitaxial structure (20) comprises a first semiconductor layer (201), a multiple quantum well layer (202) and a second semiconductor layer (203) which are sequentially laminated on the substrate (10), wherein the surface of the second semiconductor layer (203) is provided with a groove (51) exposing the first semiconductor layer (201), the first electrode (41) is positioned on the surface of the first semiconductor layer (201) and positioned on the bottom surface of the groove (51), and the second electrode (42) is positioned on the surface of the second semiconductor layer (203);
the first passivation layer (31) covers at least the surfaces of the first semiconductor layer (201), the first electrode (41), the groove (51), the second semiconductor layer (203), and the second electrode (42), the metal enhancement layer (32) is located on the first passivation layer (31), and an orthographic projection of the metal enhancement layer (32) on the substrate (10) is located within an orthographic projection of the first passivation layer (31) on the substrate (10).
2. The red micro led chip according to claim 1, wherein the metal enhancement layer (32) comprises a first Ti layer (321), a first Ni layer (322), a Pt layer (323), a second Ni layer (324), and a second Ti layer (325) sequentially stacked on a surface of the first passivation layer (31), and a thickness of the Pt layer (323) is not less than half of a total thickness of the metal enhancement layer (32).
3. The red micro led chip of claim 2, wherein the first Ti layer (321) has a thickness of 400 to 600 angstroms, the first Ni layer (322) has a thickness of 800 to 1200 angstroms, the Pt layer (323) has a thickness of 4900 to 5100 angstroms, the second Ni layer (324) has a thickness of 800 to 1200 angstroms, and the second Ti layer (325) has a thickness of 400 to 600 angstroms.
4. The red micro led chip according to claim 1, wherein the bottom surface of the recess (51) has a raised structure (53), and the raised structure (53) is connected to the sidewall of the recess (51) near the second electrode (42).
5. The red micro led chip of claim 4, wherein the bump structure (53) comprises a plurality of step blocks (531), the step blocks (531) are sequentially arranged in a direction away from the side wall of the groove (51), and the area of the orthographic projection of the step blocks (531) on the side wall of the groove (51) is gradually reduced in the direction away from the side wall of the groove (51).
6. The red micro led chip according to claim 5, wherein the number of the bump structures (53) is plural, and the plural bump structures (53) are arranged at intervals in a direction parallel to the substrate (10).
7. The red micro led chip according to claim 4, wherein the bottom surface of the bump structure (53) away from the recess (51) is a stepped surface (532), and the stepped surface (532) is connected to the surface of the recess (51) and the side wall of the recess (51), respectively.
8. The red micro light-emitting diode chip according to any one of claims 1 to 7, further comprising a second passivation layer (33), wherein the second passivation layer (33) is located on the metal enhancement layer (32), and an orthographic projection of the second passivation layer (33) on the substrate (10) coincides with an orthographic projection of the first passivation layer (31) on the substrate (10).
9. The red micro led chip of claim 8, wherein the red micro led chip further comprises: a first pad block (71) and a second pad block (72), the first pad block (71) and the second pad block (72) both being located on a surface of the second passivation layer (33);
the first welding point block (71) is connected with the first electrode (41) through a first through hole (61), the second welding point block (72) is connected with the second electrode (42) through a second through hole (62), and the first welding point block (71) and the second welding point block (72) are insulated from the metal enhancement layer (32).
10. A preparation method of a red light micro light-emitting diode chip is characterized by comprising the following steps:
providing a substrate;
forming an epitaxial structure on the substrate, wherein the epitaxial structure comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially laminated on the substrate, and the surface of the second semiconductor layer is provided with a groove for exposing the first semiconductor layer;
forming a first electrode and a second electrode on the surface of the epitaxial structure, wherein the first electrode is positioned on the surface of the first semiconductor layer and on the bottom surface of the groove, and the second electrode is positioned on the surface of the second semiconductor layer;
forming a first passivation layer and a metal enhancement layer on the epitaxial structure, wherein the first passivation layer at least covers the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer and the second electrode, the metal enhancement layer is located on the first passivation layer, and the orthographic projection of the metal enhancement layer on the substrate is located in the orthographic projection of the first passivation layer on the substrate.
CN202111651379.9A 2021-12-30 2021-12-30 Red light micro light-emitting diode chip and preparation method thereof Pending CN114551675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111651379.9A CN114551675A (en) 2021-12-30 2021-12-30 Red light micro light-emitting diode chip and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111651379.9A CN114551675A (en) 2021-12-30 2021-12-30 Red light micro light-emitting diode chip and preparation method thereof

Publications (1)

Publication Number Publication Date
CN114551675A true CN114551675A (en) 2022-05-27

Family

ID=81670498

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111651379.9A Pending CN114551675A (en) 2021-12-30 2021-12-30 Red light micro light-emitting diode chip and preparation method thereof

Country Status (1)

Country Link
CN (1) CN114551675A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114883469A (en) * 2022-07-07 2022-08-09 华灿光电（浙江）有限公司 Light emitting diode chip for improving current conduction and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114883469A (en) * 2022-07-07 2022-08-09 华灿光电（浙江）有限公司 Light emitting diode chip for improving current conduction and preparation method thereof
CN114883469B (en) * 2022-07-07 2022-11-29 华灿光电（浙江）有限公司 Light emitting diode chip for improving current conduction and preparation method thereof

Similar Documents

Publication Publication Date Title
US9142729B2 (en) Light emitting element
JP5368957B2 (en) Manufacturing method of semiconductor laser chip
US7893450B2 (en) Semiconductor light-emitting element and semiconductor light-emitting element manufacturing method
JP3724620B2 (en) Manufacturing method of light emitting diode
JP2011216882A (en) High-efficiency light emitting diode, and method for fabricating the same
JP5056799B2 (en) Group III nitride semiconductor light emitting device and method of manufacturing the same
JP4371956B2 (en) Nitride-based compound semiconductor light-emitting device and method for manufacturing the same
JP6410870B2 (en) Light emitting diode
WO2007097411A1 (en) Double wavelength semiconductor light emitting device and method for manufacturing same
KR100504178B1 (en) Light emitting diode and method of manufacturing the same
WO2015141166A1 (en) Semiconductor light-emitting device and method for manufacturing same
US20230395765A1 (en) Light-emitting device
KR101262226B1 (en) Manufacturing method of semiconductor light emitting element
JP3239061B2 (en) Light emitting diode and method of manufacturing the same
CN114551675A (en) Red light micro light-emitting diode chip and preparation method thereof
WO2009107621A1 (en) Semiconductor laser element and method of manufacturing the same
WO2005067067A1 (en) Semiconductor light emitting element
JPH10223930A (en) Semiconductor light emitting element
JP4836410B2 (en) Nitride semiconductor light emitting device and manufacturing method thereof
CN106981553B (en) Light emitting element and method for manufacturing the same
TW201725660A (en) Light-emitting device and manufacturing method thereof
JP5404808B2 (en) Light emitting element
WO2020019326A1 (en) Semiconductor luminous element
CN114639761A (en) AlGaInP-based red light-emitting diode chip and preparation method thereof
KR101521574B1 (en) Method of manufacturing semiconductor light emitting device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination