CN114709299A - High-voltage chip with vertical series structure and manufacturing method thereof - Google Patents
High-voltage chip with vertical series structure and manufacturing method thereof Download PDFInfo
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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Abstract
The invention provides a high-voltage chip with a vertical series structure and a manufacturing method thereof, wherein the method comprises the following steps: growing a plurality of epitaxial wafers with high-doped layers at the PN regions, wherein the epitaxial wafers are provided with a first high-doped layer close to the substrate and a second high-doped layer far away from the substrate; temporarily bonding a second high-doping layer in the epitaxial wafer with the silicon wafer; removing the substrate in the epitaxial wafer after temporary bonding until the first high-doping layer is exposed; carrying out plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer, relatively attaching a first high-doping layer in the epitaxial wafer with the substrate removed and a second high-doping layer in the other epitaxial wafer, and placing the epitaxial wafer and the other epitaxial wafer into a bonding machine for bonding; removing the temporary bonding of the bonded epitaxial wafer; and carrying out a chip manufacturing process on the epitaxial wafer after the temporary bonding is removed until the manufacturing is finished to obtain the high-voltage chip. The invention solves the problem of high process requirement of the existing high-voltage chip.
Description
Technical Field
The invention relates to the technical field of photoelectricity, in particular to a high-voltage chip with a vertical series structure and a manufacturing method thereof.
Background
In the LED chip industry, a high voltage chip is a brand new variety, and a common method is to connect packaged low power LED chips in series or to integrate the packaged low power LED chips in series during the manufacturing of the LED chips.
The high-voltage chip formed by connecting the chips at the packaging end in series is large in size, the high-voltage chip integrated by connecting the chips at the LED chip end in series achieves the function of the high-voltage chip by transversely connecting the electrodes in series, however, the mode has higher requirements on the grooving process, the connection electrode and the insulation effect of the chip end, and simultaneously, the traditional high-voltage chip connected in series transversely has the problem of slightly low compound efficiency.
Disclosure of Invention
Based on this, the invention aims to provide a high-voltage chip with a vertical series structure and a manufacturing method thereof, so as to fundamentally solve the problem of high process requirement of the existing high-voltage chip.
According to the embodiment of the invention, the method for manufacturing the high-voltage chip with the vertical series structure comprises the following steps:
growing a plurality of epitaxial wafers with high-doped layers at the PN regions, wherein the epitaxial wafers are provided with a first high-doped layer close to the substrate and a second high-doped layer far away from the substrate;
temporarily bonding a second high-doping layer in the epitaxial wafer with the silicon wafer;
removing the substrate in the epitaxial wafer after temporary bonding until the first high-doping layer is exposed;
Carrying out plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer, relatively attaching a first high-doping layer in the epitaxial wafer with the substrate removed and a second high-doping layer in the other epitaxial wafer, and placing the epitaxial wafer and the second high-doping layer in the bonding machine for bonding;
removing the temporary bonding of the bonded epitaxial wafer;
and carrying out a chip manufacturing process on the epitaxial wafer after the temporary bonding is removed until the manufacturing is finished to obtain the high-voltage chip.
In addition, the method for manufacturing the high-voltage chip with the vertical series structure according to the embodiment of the invention may further have the following additional technical features:
further, before the step of performing the chip manufacturing process on the epitaxial wafer after the temporary bonding is released, at least one of the following steps is further performed:
performing ion bombardment activation on the epitaxial wafer with the other substrate removed and the epitaxial wafer with the temporary bonding removed, relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the epitaxial wafer with the temporary bonding removed, and placing the epitaxial wafer and the second high-doping layer in a bonding machine for bonding again;
and releasing the temporary bonding of the epitaxial wafer after the secondary bonding.
Further, before the step of releasing the temporary bonding of the bonded epitaxial wafer, at least one time of the following steps is also executed:
Removing the substrate in the bonded epitaxial wafer until the first high-doping layer is exposed;
and carrying out plasma bombardment activation on the epitaxial wafer and the other epitaxial wafer after bonding and substrate removal, relatively attaching the first high-doping layer in the epitaxial wafer and the second high-doping layer in the other epitaxial wafer after bonding and substrate removal, and placing the epitaxial wafer and the other epitaxial wafer into a bonding machine for bonding.
Further, the step of temporarily bonding the second highly doped layer in the epitaxial wafer to the silicon wafer comprises:
waxing is carried out on the surface of the second high-doping layer in the epitaxial wafer and/or the surface of the silicon wafer;
and aligning the epitaxial wafer and the silicon wafer and putting the epitaxial wafer and the silicon wafer into a temporary bonding machine for pressure bonding, wherein the bonding pressure is 3000 kgf-6000 kgf, and the temporary bonding temperature is determined according to the temperature of the wax hot melting flow point.
Further, the step of performing plasma bombardment activation on the epitaxial wafer with the other epitaxial wafer after one substrate is removed comprises:
carrying out plasma bombardment activation on the epitaxial wafer with the substrate removed and another epitaxial wafer by using a plasma cleaning machine, wherein bombardment ions are Ar ions, and the bombardment time is 5-20 min;
and bonding the first high-doping layer in the epitaxial wafer after the substrate is removed and the second high-doping layer in the other epitaxial wafer at the bonding pressure of 12000kgf for 60-120 min, wherein the bonding temperature is determined according to the temperature at which the used wax cannot be melted and flow.
Furthermore, the doping concentration of the first high-doping layer and the second high-doping layer in the grown epitaxial wafer is larger than 1e19, and the thickness reaches 5000A.
Further, after the step of growing the plurality of epitaxial wafers each having a highly doped layer at the PN region, the method further includes:
carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt;
and polishing the second high-doping layer in the epitaxial wafer after the organic cleaning until the thickness is more than or equal to 50A and less than or equal to 100A.
Further, the step of removing the substrate in the temporarily bonded epitaxial wafer until the first high-doping layer is exposed comprises:
removing the substrate in the epitaxial wafer after temporary bonding;
and polishing the first high-doping layer exposed in the epitaxial wafer after the substrate is removed until the thickness is greater than or equal to 50A and less than or equal to 100A.
According to the embodiment of the invention, the high-voltage chip with the vertical series structure comprises:
the GaAs substrate, buffer layer, cut-off layer and repeat the epitaxial structure of the lamination at least twice stacked on said GaAs substrate sequentially;
the epitaxial structure comprises a highly-doped N-type contact layer, an N-type transition layer, an N-type current expansion layer, an N-type limiting layer, an N-type blocking layer, a multi-quantum well layer, a P-type blocking layer, a P-type limiting layer, a P-type transition layer and a highly-doped P-type current expansion layer which are stacked in sequence.
In addition, the high-voltage chip with the vertical series structure according to the above embodiment of the invention may further have the following additional technical features:
the buffer layer is a GaAs layer, the stop layer is a GaInP layer, the highly doped N-type contact layer is a GaAs layer, the N-type transition layer is a GaInP layer, the N-type current expansion layer is an AlGaInP layer, the N-type limiting layer is an AlInP layer, the N-type blocking layer is an AlGaInP layer, the P-type limiting layer is an AlInP layer, the P-type transition layer is an AlGaInP layer, and the highly doped P-type current expansion layer is a GaP layer;
the doping concentration of the highly doped N-type contact layer and the highly doped P-type current expansion layer is larger than 1e19, and the thickness of the highly doped N-type contact layer and the highly doped P-type current expansion layer is larger than or equal to 50A and smaller than or equal to 100A.
Compared with the prior art: the epitaxial layer can be transferred to the silicon wafer by adopting temporary bonding, so that the epitaxial layer is prevented from being cracked and the next bonding process is facilitated; the multilayer epitaxial wafers can be connected in series in the vertical direction through a vertical bonding mode, so that a high-voltage chip with a vertical structure is formed, the chip area is greatly reduced, the problems of difficulty in slotting the chip, growing an insulating layer and manufacturing a connecting electrode in the prior art are solved, and the problem of high process requirement of the prior high-voltage chip is solved. Meanwhile, the PN regions of the epitaxial wafer are highly doped, so that a tunneling junction can be formed after the epitaxial wafer is bonded, the current carriers can longitudinally migrate through a tunneling effect, the chip compounding efficiency is improved, and the problem that the compounding efficiency of a high-voltage chip with a transverse series structure is slightly low is solved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a high-voltage chip with a vertical series structure according to a first embodiment of the invention;
FIG. 2 is a flowchart illustrating a method for fabricating a high-voltage chip with a vertical serial structure according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for fabricating a high-voltage chip with a vertical serial structure according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a high voltage chip with a vertical series structure in a fourth embodiment of the present invention;
the following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Several embodiments of the invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example one
Referring to fig. 1, a method for manufacturing a high voltage chip with a vertical serial structure in a first embodiment of the invention is shown, and the method specifically includes steps S01-S05.
Step S01, growing a plurality of epitaxial wafers having highly doped layers in the PN region, wherein the epitaxial wafer has a first highly doped layer near the substrate and a second highly doped layer far from the substrate.
In an embodiment of the present invention, the epitaxial wafer may be a conventional epitaxial wafer in the prior art, which requires high doping treatment on both the P layer and the N layer in the epitaxial wafer, and at this time, it is required that the doping concentration in the highly doped film layer is greater than 1e19, and the thickness reaches about 5000A (angstrom, 1A ^ 10^ -10 m).
Specifically, in an example of the present invention, a red and yellow GaAs (gallium arsenide) epitaxial wafer is taken as an example, and a growth process of the red and yellow GaAs epitaxial wafer is shown, in which a double-side polished N-type GaAs single crystal wafer is used as a substrate, and then a GaAs buffer layer, a GaInP (indium gallium phosphide) stop layer, an N-type GaAs contact layer, an N-type GaInP transition layer, an N-type AlGaInP (aluminum indium phosphide) current spreading layer, an N-type AlInP (aluminum indium phosphide) limiting layer, an N-type AlGaInP barrier layer, an MQW multi-quantum well layer, a P-type AlGaInP barrier layer, a P-type AlInP limiting layer, a P-type AlGaInP transition layer, and a P-type GaP (gallium phosphide) current spreading layer are sequentially deposited on an upper surface of the GaAs substrate by using MOCVD (Metal-organic Chemical Vapor Deposition), and finally the red and yellow GaAs epitaxial wafer is grown.
Specifically, the P layer and the N layer are highly doped during the growth process of the epitaxial wafer, that is, the N type GaAs contact layer and the P type GaP extension current layer are highly doped or heavily doped, and the doping concentration of the commonly doped N type GaAs contact layer and the P type GaP extension current layer is about 1e 15-1 e 18. Therefore, when the grown epitaxial wafer is a GaAs epitaxial wafer, the first high-doped layer close to the substrate is an N-type GaAs contact layer (i.e., GaAs layer), and the second high-doped layer far from the substrate is a P-type GaP extension current layer (i.e., GaP layer).
It should be noted that, in other examples of the present invention, the specific structure in the epitaxial wafer may be disposed with more or less film layers or film layers with different sequences or different material compositions than in this example, and the arrangement is not limited in detail herein according to the actual use requirement. However, the structure of the epitaxial wafer can be substantially simplified into a substrate, an N-type high doping layer, an N layer, an MQW multi-quantum well layer, a P layer and a P-type high doping layer, wherein the N-type high doping layer is a GaAs layer, and the P-type high doping layer is a GaP layer.
It is understood that in other embodiments of the present invention, it is also possible to use other kinds of substrates to produce corresponding epitaxial wafers, such as GaN (gallium nitride) epitaxial wafers; it is also possible to use other types of substrates, such as P-type substrates, so that a substantially simplified structure of P-type high doped layer, P layer, MQW multi-quantum well layer, N layer, and N-type high doped layer is grown on the P-type substrate. At this time, the first high-doped layer close to the substrate is a P-type high-doped layer, and the second high-doped layer far from the substrate is an N-type high-doped layer, so in the embodiment of the present invention, specific types and types of the first high-doped layer and the second high-doped layer are not explicitly indicated, and the determination is performed according to the position relationship between the substrate according to the actual use and production requirements, which is not limited herein.
Further, in the doping process, the N layer is usually doped with a doping impurity containing an element of Si (silicon) or C (carbon), and the P layer is usually doped with a doping impurity containing an element of Mg (magnesium) or Zn (zinc), specifically, for example, in the case of an external growth, the N layer is doped with SiH4 (silane), and the P layer is doped with Cp2Mg (magnesium metallocene, Mg (C5H5) 2).
Further, the step S01 is followed by:
carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt;
and polishing the second high-doping layer in the epitaxial wafer after the organic cleaning until the thickness is more than or equal to 50A and less than or equal to 100A.
Specifically, the grown epitaxial wafer is organically cleaned, so that surface impurities and dirt of the epitaxial wafer can be removed, the purity of the surface of the epitaxial wafer is improved, meanwhile, the second high-doping layer in the epitaxial wafer after organic cleaning is polished until the residual thickness of the polished second high-doping layer is greater than or equal to 50A and less than or equal to 100A, the purity and the flatness of the second high-doping layer are maintained, and a proper thickness dimension can be provided for subsequent bonding treatment.
And step S02, temporarily bonding the second high-doping layer in the epitaxial wafer and the silicon wafer.
The temporary bonding of the second high-doped layer in the epitaxial wafer and the silicon wafer can be realized through the following steps:
waxing is carried out on the surface of the second high-doping layer in the epitaxial wafer and/or the surface of the silicon wafer;
and aligning the epitaxial wafer and the silicon wafer, and putting the epitaxial wafer and the silicon wafer into a temporary bonding machine for pressure bonding, wherein the bonding pressure is 3000 kgf-6000 kgf, and the temporary bonding temperature is determined according to the temperature of the wax hot melting flow point.
Specifically, high-temperature wax is coated on the surface of a silicon wafer or an epitaxial wafer or both the silicon wafer and the epitaxial wafer, the silicon wafer and the epitaxial wafer are aligned and placed in a temporary bonding machine for pressing, the temperature is mainly the flow point of the used temporary bonding wax, and it is pointed out that the high-temperature wax can bear a certain degree of temperature, for example, the temperature at the flow point of the high-temperature wax is 270 ℃, the temporary bonding temperature can be set to be 250-260 ℃, the pressure is 3000 kgf-6000 kgf (kilogram-force), and the epitaxial wafer and the silicon wafer are temporarily bonded through the high-temperature wax.
It should be noted that, because the epitaxial layer of the epitaxial wafer after the substrate is removed is very thin, generally, it is several micrometers or ten and several micrometers, after the substrate is removed, the epitaxial layer can not exist effectively alone, and is easy to crack, at this moment, the epitaxial wafer and the silicon wafer are temporarily bonded through the high-temperature wax, so that the epitaxial layer can be effectively supported on the silicon wafer (or the epitaxial layer is supported by the silicon wafer), and therefore, the epitaxial layer is transferred to the silicon wafer, so that the epitaxial layer is prevented from cracking, and subsequent processes such as substrate removal and bonding can be conveniently and effectively performed.
In step S03, the substrate in the temporarily bonded epitaxial wafer is removed until the first highly doped layer is exposed.
Since the epitaxial wafer and the silicon wafer are temporarily bonded by the high-temperature wax, the substrate in the epitaxial wafer after the temporary bonding in step S02 can be effectively removed, and the substrate is usually removed by using ammonia water and hydrogen peroxide, wherein as described above, a buffer layer and a stop layer may exist between the substrate and the first high-doping layer, so that the substrate needs to be removed until the first high-doping layer is exposed, that is, the buffer layer and the stop layer need to be removed, so that the first high-doping layer is exposed.
Specifically, the step S03 further includes:
removing the substrate in the epitaxial wafer after temporary bonding;
and polishing the first high-doping layer exposed in the epitaxial wafer after the substrate is removed until the thickness of the first high-doping layer is greater than or equal to 50A and less than or equal to 100A.
That is, after the substrate of the epitaxial wafer after temporary bonding is removed to expose the first high-doping layer, the exposed first high-doping layer is polished until the remaining thickness of the first high-doping layer is greater than or equal to 50A and less than or equal to 100A, so that the purity and the flatness of the first high-doping layer are maintained, and a proper thickness dimension can be provided for the subsequent bonding process.
And step S04, performing plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer, relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the other epitaxial wafer, and placing the epitaxial wafer and the second high-doping layer in the other epitaxial wafer into a bonding machine for bonding.
Wherein, bonding refers to a technique of bonding two homogeneous or heterogeneous semiconductor materials with clean surfaces and flat atomic levels into a whole through van der waals force, molecular force and even atomic force after surface cleaning and activating treatment and direct bonding under certain conditions.
In an embodiment of the present invention, the plasma bombardment activating the epitaxial wafer with one of the removed substrates and the other epitaxial wafer specifically includes: and (3) carrying out plasma bombardment activation on the epitaxial wafer with the substrate removed and another epitaxial wafer by using a plasma cleaning machine, wherein bombardment ions are Ar ions, and the bombardment time is 5-20 min.
And bonding the first high-doping layer in the epitaxial wafer after the substrate is removed and the second high-doping layer in the other epitaxial wafer at the bonding pressure of 12000kgf for 60-120 min, wherein the bonding temperature is determined according to the temperature at which the used wax cannot be melted and flow.
Specifically, the plasma cleaning machine is used for carrying out plasma bombardment activation on the epitaxial wafer obtained in the step S03 after the substrate is removed and the epitaxial wafer obtained in the step S01 after the second high-doping layer is polished, and Ar ions bombard the two epitaxial wafers for 5-20 min, so that activation treatment is realized. And then, relatively attaching the first high-doping layer in the epitaxial wafer obtained in the step S03 after the substrate is removed and the second high-doping layer in the epitaxial wafer polished in the step S01 together, and placing the epitaxial wafer and the second high-doping layer in a bonding machine for bonding, wherein the bonding temperature needs to be controlled within a temperature range at which the high-temperature wax cannot melt and flow and debond the bonding, for example, the temperature of the flowing point of the high-temperature wax is 270 ℃, the bonding temperature can be set to be 200 ℃, the pressure is 12000kgf, and the time is 60-120 min, so that the high-temperature wax is always in a solid state and maintains temporary bonding with the silicon wafer, and the problem that the epitaxial wafer and the debonding wafer are bonded due to melting of the high-temperature wax caused by overhigh bonding temperature is solved.
At this time, in the embodiment of the present invention, after the epitaxial wafer after the substrate is removed is bonded to another epitaxial wafer, the bonding thereof forms a structure similar to a PN junction, where a specific first high-doped layer (e.g., a GaAs layer in the example) belongs to an N-layer structure of the epitaxial wafer after the substrate is removed, a second high-doped layer (e.g., a GaP layer in the example) belongs to a P-layer structure of the other epitaxial wafer, and the GaAs layer in the N-layer and the GaP layer in the P-layer are connected to each other, and then the original N-layer structure and P-layer structure are added to form a new PN junction. Therefore, an interband tunneling junction can be formed between the first high-doping layer in the epitaxial wafer and the second high-doping layer in the other epitaxial wafer after the substrate is removed, wherein interband tunneling refers to that electrons reach a conduction band of the n-type semiconductor layer from a valence band and a forbidden band of the p-type semiconductor layer, and at the moment, current carriers can longitudinally migrate through a tunneling effect.
In step S05, the bonded epitaxial wafer is temporarily released from bonding.
After the bonding of the epitaxial wafer in step S04 is completed, the temperature may be raised accordingly, so that the temperature reaches the flow point of the high-temperature wax, and the high-temperature wax changes from the solid state during temporary bonding to the liquid state, so that the temporary bonding between the silicon wafer and the epitaxial wafer is released or broken, and the epitaxial wafer and the silicon wafer are separated, thereby completing the vertical tandem process between the two epitaxial wafers.
And step S06, carrying out a chip manufacturing process on the epitaxial wafer after the temporary bonding is removed until the manufacturing is finished to obtain a high-voltage chip.
In the embodiment of the invention, the serial process of the epitaxial wafer with the vertical serial structure is completed, and the normal chip manufacturing process can be continued until the chip end is manufactured to obtain the high-voltage chip. At the moment, the epitaxial wafer is used for manufacturing an N electrode, a P electrode and the like through the processes of substrate removal, photoetching, etching, film coating, evaporation, thinning and the like. It should be noted that, a main protection point of the embodiment of the present invention is to obtain an "epitaxial wafer" with a vertical series structure through a process of a chip end, and a subsequent process step of fabricating an electrode and the like is not different from a common chip process, and therefore, a detailed description is not given, and reference may be made to any existing process step that can be implemented specifically, which is not specifically limited herein.
Therefore, the overall process flow in the embodiment of the present invention is substantially as follows:
and a step a of growing an epitaxial wafer, wherein high doping is required to be carried out on the PN region until the doping concentration of the first high-doping layer and the doping concentration of the second high-doping layer both reach at least 1e19, and the thickness of the epitaxial wafer both reaches about 5000A.
And step b, carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and then polishing the second high-doping layer of the epitaxial wafer, wherein the residual thickness of the polished second high-doping layer is not more than 100A and not less than 50A.
And c, temporarily bonding the second high-doping layer of the polished epitaxial wafer with the silicon wafer by using liquid high-temperature wax.
And d, removing the substrate of the temporarily bonded epitaxial wafer until the first high-doping layer is exposed, polishing the exposed first high-doping layer, wherein the residual thickness of the polished first high-doping layer is less than or equal to 100A and more than or equal to 50A.
And e, performing plasma bombardment activation on the epitaxial wafer with the substrate removed in the step d and the epitaxial wafer polished in the step b, and then relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the polished epitaxial wafer together and putting the epitaxial wafer and the polished epitaxial wafer into a bonding machine for bonding.
Step f, removing the temporary bonding of the high-temperature wax from the bonded epitaxial wafer to separate the epitaxial wafer from the silicon wafer;
and g, carrying out the conventional chip manufacturing process on the epitaxial wafer after the temporary bonding is removed.
In summary, in the method for manufacturing a high-voltage chip with a vertical series structure in the above embodiment of the invention, the epitaxial layer can be transferred onto the silicon wafer by adopting temporary bonding, so that the epitaxial layer is prevented from being cracked and the next bonding process is facilitated; the multilayer epitaxial wafers can be connected in series in the vertical direction through a vertical bonding mode, so that a high-voltage chip with a vertical structure is formed, the area of the chip is greatly reduced, the problems of difficulty in slotting the chip, growing an insulating layer and manufacturing a connecting electrode in the prior art are solved, and the problem of high process requirement of the prior high-voltage chip is solved. Meanwhile, the PN regions of the epitaxial wafer are highly doped, so that a tunneling junction can be formed after the epitaxial wafer is bonded, carriers can longitudinally migrate through a tunneling effect, the chip compounding efficiency is improved, and the problem that the high-voltage chip compounding efficiency of a transverse series structure is slightly low is solved.
Example two
Referring to fig. 2, a method for manufacturing a high voltage chip with a vertical serial structure in a second embodiment of the invention is shown, and the method specifically includes steps S11 to S18.
Step S11, growing a plurality of epitaxial wafers having highly doped layers in the PN region, wherein the epitaxial wafer is a first highly doped layer near the substrate and a second highly doped layer far from the substrate.
And step S12, temporarily bonding the second high-doping layer in the epitaxial wafer and the silicon wafer.
In step S13, the substrate in the temporarily bonded epitaxial wafer is removed until the first highly doped layer is exposed.
And step S14, performing plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer, relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the other epitaxial wafer, and placing the epitaxial wafer and the second high-doping layer in the other epitaxial wafer into a bonding machine for bonding.
In step S15, the bonded epitaxial wafer is released from temporary bonding.
The specific flow of steps S11-S15 is substantially the same as that of the foregoing embodiment, and the specific flow can be referred to the foregoing embodiment, which is not limited herein.
And step S16, performing ion bombardment activation on the epitaxial wafer with the other substrate removed and the epitaxial wafer with the temporary bonding removed, relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the epitaxial wafer with the temporary bonding removed, and placing the epitaxial wafer into a bonding machine for bonding again.
In step S12, since the epitaxial wafer in step S15 exposes the polished second highly doped layer after the temporary bonding is released, the epitaxial wafers can be temporarily bonded to the corresponding silicon wafers in step S12, and the substrate removal in step S13 can be continued. At this time, the epitaxial wafer in the step S15 and another epitaxial wafer removed from the substrate prepared in the step S13 are subjected to ion bombardment activation, and bonding again by the bonding machine is continued, so that the tandem three-layer epitaxial structure can be bonded.
In step S17, the temporary bonding of the bonded epitaxial wafer is released.
Accordingly, since the epitaxial wafer removed from the substrate obtained in step S13 is taken in step S16, the temporary bonding between the epitaxial wafer and the silicon wafer still exists, and therefore, after the re-bonding in step S16 is completed, the temporary bonding of the re-bonded epitaxial wafer also needs to be released.
It should be noted that, when the steps S16 and S17 are performed at least once, that is, the bonding is performed only once in the steps S16 and S17, a serial three-layer epitaxial structure is obtained. When steps S16 and S17 are repeated twice, a serial four-layer epitaxial structure is obtained. That is, the foregoing embodiments are made to obtain a serial dual-layer high voltage chip, and the present embodiment is made to obtain a high voltage chip with at least three layers and is not limited to three layers. For example, the specific number of the series connections is set according to the required power, if a high-voltage chip of 5W is required, 5 epitaxial structures of 1W can be connected in series, and at this time, five layers need to be connected in series vertically, that is, step S16 and step S17 need to be executed three times. It should be noted that, it is not preferable that the number of vertical series connections is larger, the larger the number of vertical series connections is, the more the problems of low recombination efficiency and the like easily occur, and the design of the epitaxial wafer and the chip needs to be optimized accordingly. Therefore, it sets the number of execution times of step S16 and step S17 according to the number of series connections required for actual use.
And step S18, carrying out a chip manufacturing process on the epitaxial wafer after the temporary bonding is removed until the manufacturing is finished to obtain a high-voltage chip.
The specific flow of step S18 is substantially the same as that of the foregoing embodiment, and it can be specifically referred to the foregoing embodiment, which is not limited herein.
Therefore, the overall process flow in the embodiment of the present invention is substantially as follows:
and a, growing an epitaxial wafer, wherein high doping is carried out in the PN region until the doping concentration of the first high-doping layer and the doping concentration of the second high-doping layer reach at least 1e19, and the thickness of the epitaxial wafer reaches about 5000A.
And b, carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and then polishing the second high-doping layer of the epitaxial wafer, wherein the residual thickness of the polished second high-doping layer is less than or equal to 100A and more than or equal to 50A.
And c, temporarily bonding the second high-doping layer of the polished epitaxial wafer with the silicon wafer by using liquid high-temperature wax.
And d, removing the substrate of the temporarily bonded epitaxial wafer until the first high-doping layer is exposed, polishing the exposed first high-doping layer, wherein the residual thickness of the polished first high-doping layer is less than or equal to 100A and more than or equal to 50A.
And e, performing plasma bombardment activation on the epitaxial wafer with the substrate removed in the step d and the epitaxial wafer polished in the step b, and then relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the polished epitaxial wafer together and putting the epitaxial wafer and the polished epitaxial wafer into a bonding machine for bonding.
Step f, removing the temporary bonding of the high-temperature wax from the bonded epitaxial wafer to separate the epitaxial wafer from the silicon wafer;
step g, performing sub-bombardment activation on the epitaxial wafer with the substrate removed in the other step d and the epitaxial wafer with the temporary bonding removed in the step f, and relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the epitaxial wafer with the temporary bonding removed together and putting the epitaxial wafer and the second high-doping layer in the epitaxial wafer into a bonding machine for bonding again;
step h, removing the temporary bonding of the high-temperature wax from the epitaxial wafer after the secondary bonding, and separating the epitaxial wafer from the silicon wafer;
and step i, carrying out the conventional chip manufacturing process on the epitaxial wafer after the temporary bonding is removed.
EXAMPLE III
Referring to fig. 3, a method for manufacturing a high voltage chip with a vertical serial structure in a third embodiment of the invention is shown, and the method specifically includes steps S21 to S28.
Step S21, growing a plurality of epitaxial wafers having highly doped layers in the PN region, wherein the epitaxial wafer has a first highly doped layer near the substrate and a second highly doped layer far from the substrate.
And step S22, temporarily bonding the second high-doping layer in the epitaxial wafer and the silicon wafer.
In step S23, the substrate in the temporarily bonded epitaxial wafer is removed until the first highly doped layer is exposed.
And step S24, performing plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer, relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the other epitaxial wafer, and placing the epitaxial wafer and the second high-doping layer in the other epitaxial wafer into a bonding machine for bonding.
The specific flow of steps S11-S24 is substantially the same as that of the foregoing embodiment, and the specific flow can be referred to the foregoing embodiment, which is not limited herein.
In step S25, the substrate in the bonded epitaxial wafer is removed until the first highly doped layer is exposed.
In the embodiment of the present invention, since the epitaxial wafer is bonded and temporarily bonded, and has a sufficient thickness to remove the substrate, the substrate in the bonded epitaxial wafer may be removed first to expose the first high-doping layer, and the first high-doping layer is polished until the remaining thickness of the first high-doping layer is greater than or equal to 50A and less than or equal to 100A.
And step S26, performing plasma bombardment activation on the epitaxial wafer and the further epitaxial wafer after bonding and substrate removal, relatively attaching the first high-doping layer in the epitaxial wafer and the second high-doping layer in the further epitaxial wafer after bonding and substrate removal, and placing the epitaxial wafer and the further epitaxial wafer into a bonding machine for bonding.
In the embodiment of the present invention, since the substrate in the epitaxial wafer is removed in step S25 to expose the first high-doped layer, the bonded and substrate-removed epitaxial wafer and the further polished epitaxial wafer with the second high-doped layer may be subjected to plasma bombardment activation and bonding treatment.
It should be noted that, when the steps S25 and S26 are performed at least once, that is, the steps S25 and S26 are performed only once, the bonding results in a serial three-layer epitaxial structure. When steps S25 and S26 are repeated twice, a serial four-layer epitaxial structure is obtained. That is, the foregoing embodiments are made to obtain a serial dual-layer high voltage chip, and the present embodiment is made to obtain a high voltage chip with at least three layers and is not limited to three layers. For example, the specific number of the series connections is set according to the required power, if a high-voltage chip of 5W is required, 5 epitaxial structures of 1W can be connected in series, and at this time, five layers need to be connected in series vertically, that is, step S25 and step S26 need to be executed three times. It should be noted that, it is not preferable that the number of vertical series connections is larger, the larger the number of vertical series connections is, the more the problems of low recombination efficiency and the like easily occur, and the design of the epitaxial wafer and the chip needs to be optimized accordingly. Therefore, the number of execution times of step S25 and step S26 is set according to the number of series connections required for actual use.
In step S27, the bonded epitaxial wafer is temporarily released from bonding.
After the epitaxial wafers with the required number of layers are connected in series, the temperature is controlled to reach the flowing point of the high-temperature wax, so that the high-temperature wax is changed from a solid state during temporary bonding to a liquid state, the temporary bonding between the silicon wafer and the epitaxial wafers is released or disconnected, the temporary bonding between the silicon wafer and the multilayer epitaxial wafers is finally released, the multilayer epitaxial wafers and the silicon wafers are separated, and the vertical series connection process among the multiple epitaxial wafers is completed.
And step S28, carrying out a chip manufacturing process on the epitaxial wafer after the temporary bonding is removed until the manufacturing is finished to obtain a high-voltage chip.
The specific flow of step S28 is substantially the same as that of the foregoing embodiment, and it can be referred to the foregoing embodiment specifically, and is not limited herein.
Therefore, the overall process flow in the embodiment of the present invention is substantially as follows:
and a, growing an epitaxial wafer, wherein high doping is carried out in the PN region until the doping concentration of the first high-doping layer and the doping concentration of the second high-doping layer reach at least 1e19, and the thickness of the epitaxial wafer reaches about 5000A.
And b, carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt, and then polishing the second high-doping layer of the epitaxial wafer, wherein the residual thickness of the polished second high-doping layer is less than or equal to 100A and more than or equal to 50A.
And c, temporarily bonding the second high-doping layer of the polished epitaxial wafer with the silicon wafer by using liquid high-temperature wax.
And d, removing the substrate of the epitaxial wafer subjected to temporary bonding until the first high-doping layer is exposed, polishing the exposed first high-doping layer, wherein the residual thickness of the polished first high-doping layer is less than or equal to 100A and more than or equal to 50A.
And e, performing plasma bombardment activation on the epitaxial wafer with the substrate removed in the step d and the epitaxial wafer polished in the step b, and then relatively attaching the first high-doping layer in the epitaxial wafer with the substrate removed and the second high-doping layer in the polished epitaxial wafer together and putting the epitaxial wafer and the polished epitaxial wafer into a bonding machine for bonding.
And f, removing the substrate in the epitaxial wafer bonded in the step e until the first high-doping layer is exposed, polishing the exposed first high-doping layer, wherein the residual thickness of the polished first high-doping layer is less than or equal to 100A and more than or equal to 50A.
And g, carrying out plasma bombardment activation on the epitaxial wafer bonded and subjected to substrate removal in the step f and the epitaxial wafer polished in the step b, relatively attaching the first high-doping layer in the epitaxial wafer bonded and subjected to substrate removal and the second high-doping layer in the polished epitaxial wafer, and placing the epitaxial wafer into a bonding machine for bonding.
Step h, removing the temporary bonding of the high-temperature wax from the bonded epitaxial wafer in the step g, so that the epitaxial wafer is separated from the silicon wafer;
and step i, carrying out the conventional chip manufacturing process on the epitaxial wafer after the temporary bonding is removed.
Example four
Referring to fig. 4, a high-voltage chip with a vertical serial structure according to a fourth embodiment of the present invention is shown, which is manufactured according to the manufacturing method in the foregoing method embodiment, and includes:
a GaAs substrate 100, a buffer layer 200, a stop layer 300 stacked in this order on the GaAs substrate 100, and an epitaxial structure 400 stacked repeatedly at least twice;
the epitaxial structure 400 includes a highly doped N-type contact layer 401, an N-type transition layer 402, an N-type current spreading layer 403, an N-type confinement layer 404, an N-type barrier layer 405, a multi-quantum well layer 406, a P-type barrier layer 407, a P-type confinement layer 408, a P-type transition layer 409, and a highly doped P-type current spreading layer 410, which are stacked in sequence.
In an embodiment of the present invention, the buffer layer 200 is a GaAs layer, the stop layer 300 is a GaInP layer, the highly doped N-type contact layer 401 is a GaAs layer, the N-type transition layer 402 is a GaInP layer, the N-type current spreading layer 403 is an AlGaInP layer, the N-type confinement layer 404 is an AlInP layer, the N-type barrier layer 405 is an AlGaInP layer, the P-type barrier layer 407 is an AlGaInP layer, the P-type confinement layer 408 is an AlInP layer, the P-type transition layer 409 is an AlGaInP layer, and the highly doped P-type current spreading layer 410 is a GaP layer; the doping concentration of the highly doped N-type contact layer 401 and the highly doped P-type current spreading layer 410 are both greater than 1e19, and the thickness thereof is both greater than or equal to 50A and less than or equal to 100A.
In summary, in the high-voltage chip with the vertical serial structure in the above embodiments of the invention, the multiple layers of epitaxial wafers can be connected in series in the vertical direction by bonding in the vertical direction, so as to form the high-voltage chip with the vertical structure, so that the chip area is greatly reduced, the problems of difficulty in slotting the chip, growing the insulating layer and manufacturing the connecting electrode in the prior art are solved, and the problem of high process requirements of the prior high-voltage chip is solved. Meanwhile, the highly doped N-type contact layer and the highly doped P-type current expansion layer are obtained by highly doping the PN regions of each epitaxial wafer, so that tunneling junctions can be formed after the epitaxial wafers are bonded, carriers can longitudinally migrate through a tunneling effect, the chip compounding efficiency is improved, and the problem that the high-voltage chip compounding efficiency of a transverse series structure is slightly low is solved.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the present invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (10)
1. A method for manufacturing a high-voltage chip with a vertical series structure is characterized by comprising the following steps:
growing a plurality of epitaxial wafers with high-doped layers at the PN regions, wherein the epitaxial wafers are provided with a first high-doped layer close to the substrate and a second high-doped layer far away from the substrate;
temporarily bonding a second high-doping layer in the epitaxial wafer with the silicon wafer;
removing the substrate in the epitaxial wafer after temporary bonding until the first high-doping layer is exposed;
carrying out plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer, relatively attaching a first high-doping layer in the epitaxial wafer with the substrate removed and a second high-doping layer in the other epitaxial wafer, and placing the epitaxial wafer and the other epitaxial wafer into a bonding machine for bonding;
Removing the temporary bonding of the bonded epitaxial wafer;
and carrying out a chip manufacturing process on the epitaxial wafer after the temporary bonding is removed until the manufacturing is finished to obtain the high-voltage chip.
2. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 1, wherein before the step of performing a chip manufacturing process on the epitaxial wafer after the temporary bonding is released, at least one of the following steps is further performed:
performing ion bombardment activation on the epitaxial wafer with the other substrate removed and the epitaxial wafer with the temporary bonding removed, relatively attaching a first high-doping layer in the epitaxial wafer with the substrate removed and a second high-doping layer in the epitaxial wafer with the temporary bonding removed, and placing the epitaxial wafer into a bonding machine for bonding again;
and releasing the temporary bonding of the epitaxial wafer after the secondary bonding.
3. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 1, wherein the step of releasing the temporary bonding of the bonded epitaxial wafer is preceded by at least one of the following steps:
removing the substrate in the bonded epitaxial wafer until the first high-doping layer is exposed;
and carrying out plasma bombardment activation on the epitaxial wafer and the other epitaxial wafer after bonding and substrate removal, relatively attaching the first high-doping layer in the epitaxial wafer and the second high-doping layer in the other epitaxial wafer after bonding and substrate removal, and placing the epitaxial wafer and the other epitaxial wafer into a bonding machine for bonding.
4. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 1, wherein the step of temporarily bonding the second highly doped layer in the epitaxial wafer and the silicon wafer comprises the steps of:
waxing is carried out on the surface of the second high-doping layer in the epitaxial wafer and/or the surface of the silicon wafer;
and aligning the epitaxial wafer and the silicon wafer and putting the epitaxial wafer and the silicon wafer into a temporary bonding machine for pressure bonding, wherein the bonding pressure is 3000 kgf-6000 kgf, and the temporary bonding temperature is determined according to the temperature of the wax hot melting flow point.
5. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 1, wherein the step of performing plasma bombardment activation on the epitaxial wafer with one substrate removed and the other epitaxial wafer comprises the following steps:
carrying out plasma bombardment activation on the epitaxial wafer with the substrate removed and another epitaxial wafer by using a plasma cleaning machine, wherein bombardment ions are Ar ions, and the bombardment time is 5-20 min;
and bonding the first high-doping layer in the epitaxial wafer after the substrate is removed and the second high-doping layer in the other epitaxial wafer at the bonding pressure of 12000kgf for 60-120 min, wherein the bonding temperature is determined according to the temperature at which the used wax cannot be melted and flow.
6. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 1, wherein the doping concentration of the first high-doped layer and the doping concentration of the second high-doped layer in the grown epitaxial wafer are both greater than 1e19, and the thickness of the first high-doped layer and the second high-doped layer reaches 5000A.
7. The method for manufacturing a high voltage chip with a vertical series structure according to claim 6, wherein the step of growing a plurality of epitaxial wafers each having a high doped layer at the PN region further comprises:
carrying out organic cleaning on the epitaxial wafer to remove surface impurities and dirt;
and polishing the second high-doping layer in the epitaxial wafer after the organic cleaning until the thickness is more than or equal to 50A and less than or equal to 100A.
8. The method for manufacturing a high-voltage chip with a vertical series structure according to claim 6, wherein the step of removing the substrate in the epitaxial wafer after temporary bonding until the first high-doping layer is exposed comprises the following steps:
removing the substrate in the epitaxial wafer after temporary bonding;
and polishing the first high-doping layer exposed in the epitaxial wafer after the substrate is removed until the thickness is greater than or equal to 50A and less than or equal to 100A.
9. A vertical series high voltage chip, comprising:
the GaAs substrate, buffer layer, cut-off layer and repeat the epitaxial structure of the lamination at least twice stacked on said GaAs substrate sequentially;
The epitaxial structure comprises a highly-doped N-type contact layer, an N-type transition layer, an N-type current expansion layer, an N-type limiting layer, an N-type blocking layer, a multi-quantum well layer, a P-type blocking layer, a P-type limiting layer, a P-type transition layer and a highly-doped P-type current expansion layer which are sequentially stacked.
10. The chip of claim 9, wherein the buffer layer is a GaAs layer, the stop layer is a GaInP layer, the heavily doped N-type contact layer is a GaAs layer, the N-type transition layer is a GaInP layer, the N-type current spreading layer is an AlGaInP layer, the N-type confinement layer is an AlInP layer, the N-type barrier layer is an AlGaInP layer, the P-type confinement layer is an AlInP layer, the P-type transition layer is an AlGaInP layer, and the heavily doped P-type current spreading layer is a GaP layer;
the doping concentration of the highly doped N-type contact layer and the highly doped P-type current spreading layer is greater than 1e19, and the thickness of the highly doped N-type contact layer and the highly doped P-type current spreading layer is greater than or equal to 50A and less than or equal to 100A.
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| CN117810318B (en) * | 2024-02-29 | 2024-05-07 | 江西兆驰半导体有限公司 | High-voltage Micro-LED chip and preparation method thereof |
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