CN117747669A - Trench gate MOS semiconductor device and manufacturing method thereof - Google Patents
Trench gate MOS semiconductor device and manufacturing method thereof Download PDFInfo
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- 239000004020 conductor Substances 0.000 claims abstract description 93
- 210000000746 body region Anatomy 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
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- 239000003989 dielectric material Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
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- 229920005591 polysilicon Polymers 0.000 description 2
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- 238000000151 deposition Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a trench gate MOS semiconductor device and a manufacturing method thereof, which solve the problem of poor consistency of two sides of the conventional trench gate, wherein the device comprises: a first epitaxial layer doped with a first conductivity type on the substrate; a second conductivity type doped body region on the first epitaxial layer; a heavily doped layer of the first conductivity type on the body region; a gate trench passing through the heavily doped layer of the first conductivity type and the body region, the bottom being located in the first epitaxial layer; a gate dielectric layer; a gate conductive material layer; the dielectric layer is positioned on the top of the gate conductive material layer, the gate dielectric layer, the gate groove and the first conductive type heavily doped layer; a contact hole trench; a second conductive material layer; and a source metal layer. The invention greatly improves the consistency and performance of the product, reduces the transverse size, increases the power density and reduces the parasitic resistance of the base region.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a trench gate MOS semiconductor device and a manufacturing method thereof.
Background
The avalanche failure parasitic triode of the MOSFET is conducted to easily cause the MOSFET to burn out, the influence on the working range of a safe working area of the MOSFET is relatively large, under the condition that a load is an inductive load, the current is increased linearly, the current depends on the change of voltage, and at the moment, the MOSFET is turned off, and the inductive load can keep drain current. Drain current can pass through the MOSFET, and under conditions where such current cannot be turned off in time, the MOSFET enters the UIS state, which can turn on the parasitic transistor and cause the device to permanently fail.
In order to improve the capability of the parasitic triode for opening and conducting failure, the concentration of the base region of the trench gate semiconductor device is improved, the voltage drop of current flowing is reduced, and opening is prevented. The structure of the conventional first trench gate semiconductor device is schematically shown in fig. 1. The parasitic triode consists of a source region N+, a P-type region and an N drift region, wherein the P-type region is a base region of the parasitic triode, the P-type region is formed on an epitaxial layer of the N region, and an N+ doped source region is formed on the surface of the P-type region; the trench gate comprises a gate dielectric oxide layer of a formed gate trench and a gate filled polysilicon gate; filling an oxide layer for isolation on the polysilicon gate; a contact hole area is formed in the source area and the P-type area and is used for connecting with a source electrode at the top; and a conduction channel is arranged between the source region N+ region and the epitaxial N drift region, and the bottom of the conduction channel and the N-region form an N drift region. In the manufacturing process, due to the deviation of the contact hole process, the concentration of the base regions on the left side and the right side is necessarily different, so that the two sides of the MOSFET are under the same current, and the starting failure is always caused by the fact that the parasitic resistance Rb of the base region is larger on one side. That is, it increases the implantation of the P-type region in order to reduce Rb, which reduces the implantation concentration of the base region and thus reduces Rb. In this structure, the p+ doping is performed after the contact hole without affecting the concentration of the channel region, and the alignment of the photolithography greatly affects the uniformity of both sides of the channel.
Disclosure of Invention
The invention provides a trench gate MOS semiconductor device and a manufacturing method thereof, which aim to solve the problem of poor consistency of two sides of a trench gate of the conventional trench gate MOS semiconductor device and the manufacturing method thereof.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a trench gate MOS semiconductor device comprising:
a substrate;
a first epitaxial layer doped with a first conductivity type on the substrate;
a second conductivity type doped body region on the first epitaxial layer;
a heavily doped layer of the first conductivity type on the body region;
a gate trench passing through the heavily doped layer of the first conductivity type and the body region, the bottom being located in the first epitaxial layer;
the grid dielectric layer is positioned on the inner side surface of the grid groove;
a gate conductive material layer located in the gate trench and higher than the top of the gate trench;
the dielectric layer is positioned on the top of the gate conductive material layer, the gate dielectric layer, the gate groove and the first conductive type heavily doped layer;
a second conductive material layer on the body region and connected with the heavily doped layer of the first conductivity type;
the contact hole groove is positioned on the dielectric layer, the first conductive type heavily doped layer and the second conductive material layer;
the source metal layer is arranged on the surface of the dielectric layer, the outer side surface of the first conductive type heavily doped layer and the upper surface of the second conductive material layer.
A preparation method of a trench gate MOS semiconductor device comprises the following steps:
step one, preparing a substrate;
preparing a first epitaxial layer doped with a first conductivity type on a substrate;
forming a second conductive type doped body region in the first epitaxial layer;
step four, preparing a hard mask layer on the body region;
etching the first epitaxial layer by taking the hard mask layer as a mask to form a gate groove, wherein the gate groove penetrates through the body region, the bottom of the gate groove is positioned in the first epitaxial layer, and the top surface of the gate groove is leveled with the top surface of the first epitaxial layer;
step six, forming a gate dielectric layer on the inner side surface of the gate trench;
step seven, filling a gate conductive material layer in the gate trench, wherein the upper surface of the gate conductive material layer is higher than the top surface of the first epitaxial layer;
step eight, preparing a dielectric layer on the top of the gate conductive material layer and the side surface of the gate conductive material layer higher than the body region, wherein the process of preparing the dielectric layer comprises the step of removing the hard mask layer;
step nine, forming a first conductive type heavily doped layer on the side surface of the grid electrode groove, wherein the dielectric layer is positioned on the upper surface of the first conductive type heavily doped layer;
step ten, preparing a contact hole groove;
step eleven, preparing a second conductive material layer;
and step twelve, preparing a source metal layer, and finishing the preparation of the trench gate MOS semiconductor device.
The beneficial effects of the invention are as follows:
1. the invention provides a trench gate MOS semiconductor device and a manufacturing method thereof, wherein the self-aligned structure and the formation structure of a source metal layer are remanufactured by utilizing the difference of oxidation rates of a gate conductive material layer and a first conductive type heavily doped layer by utilizing the fact that the gate conductive material layer in a gate trench is higher than the top surface of the first conductive type heavily doped layer, so that the dispersion generated in the manufacturing process of photoetching and the like is eliminated, and the consistency and the performance of products are greatly improved.
2. The invention adopts the structure of the longitudinal groove, forms the conductive channel in the longitudinal direction and forms the conductive source electrode in the longitudinal direction of the grid electrode, thereby reducing the transverse size, increasing the power density and reducing the parasitic resistance Rb of the base region.
Drawings
Fig. 1 is a schematic structural diagram of a conventional trench gate MOS semiconductor device.
Fig. 2 is a structural diagram of a trench gate MOS semiconductor device of the present invention.
Fig. 3 is a flowchart of a method of manufacturing a trench gate MOS semiconductor device of the present invention.
Fig. 4A is a state diagram of a fourth step of the method for manufacturing a trench gate MOS semiconductor device of the present invention.
Fig. 4B is a state diagram of a step seven of a method for manufacturing a trench gate MOS semiconductor device of the present invention.
Fig. 4C is a state diagram of step 8.1 of a method for manufacturing a trench gate MOS semiconductor device of the present invention.
Fig. 4D is a state diagram of step 8.3 of a method for fabricating a trench gate MOS semiconductor device of the present invention.
In the figure: 201. a first epitaxial layer; 202. a body region; 203. a second conductive material layer; 205. a first conductivity type heavily doped layer; 207. a gate dielectric layer; 208. a gate conductive material layer; 209. a gate trench; 210. a dielectric layer; 211. a contact hole trench; 212. a source metal layer; 213. a substrate; 214. and a hard mask layer.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
A trench gate MOS semiconductor device, as in fig. 2, comprising: the first epitaxial layer 201, the body region 202, the second conductive material layer 203, the first conductivity type heavily doped layer 205, the gate dielectric layer 207, the gate conductive material layer 208, the gate trench 209, the dielectric layer 210, the contact hole trench 211, the source metal layer 212 and the substrate 213.
A first epitaxial layer 201 doped with a first conductivity type is located on the substrate 213. A body region 202 doped with a second conductivity type is located on the first epitaxial layer 201. A heavily doped layer 205 of the first conductivity type is located on the body region 202. A gate trench 209, passing through the heavily doped layer 205 of the first conductivity type and the body region 202, is located at the bottom in the first epitaxial layer 201. A gate dielectric layer 207 is located on the inside surface of the gate trench 209. A layer of gate conductive material 208 is located in the gate trench 209 and above the top of the gate trench 209. Dielectric layer 210 is located on top of the gate conductive material layer 208, gate dielectric layer 207, gate trench 209 and first conductivity type heavily doped layer 205. A second layer of conductive material 203 is located on the body region 202, the second layer of conductive material 203 being connected to the heavily doped layer 205 of the first conductivity type. Contact hole trenches 211 are located on dielectric layer 210, first conductivity-type heavily doped layer 205, and second conductive material layer 203. The source metal layer 212 is disposed on the surface of the dielectric layer 210, the outer side surface of the first conductive type heavily doped layer 205, and the upper surface of the second conductive material layer 203.
Specific: the second conductive material layer 203 includes a second horizontal conductive material layer and a second vertical conductive material layer, the second vertical conductive material layer is located at the lower side of the first conductive type heavily doped layer 205, the top of the second vertical conductive material layer is connected to the lower surface of the first conductive type heavily doped layer 205, the lower part is connected to the second horizontal conductive material layer, and the second horizontal conductive material layer is located on the body region 202 and located at the outer side of the first conductive type heavily doped layer 205. The contact hole trench 211 includes a longitudinal trench on the outer sidewall of the dielectric layer 210, the outer sidewall of the first conductive type heavily doped layer 205, and the outer sidewall of the second vertical conductive material layer, and a lateral trench communicating with the longitudinal trench, the longitudinal trench being disposed along the outer sidewall of the dielectric layer 210, the outer sidewall of the first conductive type heavily doped layer 205, and the outer sidewall of the second vertical conductive material layer from top to bottom, the lateral trench being on the upper surface of the second horizontal conductive material layer. The source metal layer 212 is located above the dielectric layer 210 and the lateral trench, and covers the contact hole trench 211, and is located on the upper side of the second horizontal conductive material layer, on the upper side of the dielectric layer 210, on the outer side of the heavily doped layer 205 of the first conductivity type, and on the outer side of the second vertical conductive material layer. The first epitaxial layer 201, the body region 202, the second conductive material layer 203, the heavily doped layer 205 of the first conductivity type, the gate dielectric layer 207, the gate conductive material layer 208, the gate trench 209, the dielectric layer 210 and the contact hole trench 211 form a substrate assembly, and a source metal layer 212 is disposed on the upper surface of the substrate assembly.
The surface of the portion of the gate conductive material layer 208 above the heavily doped layer 205 of the first conductivity type is coated with a dielectric layer 210.
The first epitaxial layer 201 doped with the first conductivity type is located on the substrate 213, and the body region 202 doped with the second conductivity type is formed in the first epitaxial layer 201.
The trench gate includes a gate trench 209, a gate dielectric layer 207, and a gate conductive material layer 208. The gate dielectric layer 207 is not limited to an oxide layer in the present invention.
The gate trench 209 is located in the body region 202 and the first epitaxial layer 201, i.e. the gate trench 209 passes through the body region 202, the bottom of the gate trench 209 is located in the first epitaxial layer 201, and the top surface of the gate trench 209 is level with the top surface of the first conductivity type heavily doped layer 205. A gate dielectric layer 207 is located on the inner side surface of the gate trench 209, and the top surface of the gate dielectric layer 207 is level with the surface of the first conductivity type heavily doped layer 205. The top of the gate conductive material layer 208 is higher than the top of the first conductivity type heavily doped layer 205, i.e. higher than the top of the first epitaxial layer 201, and the lower portion of the gate conductive material 208 is completely filled to the bottom of the gate trench 209. The outer surface of the gate conductive material layer 208 contacts the inner surface of the dielectric material 207 and part of the sides of the gate conductive material layer 208 are covered by the dielectric material 207, the trench gate forming a conductive channel with the body 202 on its own side.
A first conductivity type heavily doped layer 205 is formed on the upper surface of the body region 202. The body region 202 and the heavily doped layer 205 of the first conductivity type are formed with the gate conductive material layer 208 in the gate trench 209 being self-aligned.
The oxidation rate of the gate conductive material layer 208 is faster than that of the first epitaxial layer 201, i.e., faster than that of the body region 202 and faster than that of the first conductivity type heavily doped layer 205, and both the body region 202 and the first conductivity type heavily doped layer 205 are prepared based on the first epitaxial layer 201. The gate conductive material layer 208 utilizes the advantage of the material having a faster oxidation rate than the first epitaxial layer 201 to form a dielectric layer 210 on top of and on both sides of the gate conductive material layer 208. Dielectric layer 210 forms a self-aligned structure on both sides of the trench conductive material and forms an isolation of source metal layer from gate conductive material layer 208 from the top of gate conductive material layer 208.
The contact hole trench 211, i.e., a trench type contact hole, serves as a source trench. The contact hole trench 211 forms a source contact with the body region 202 at the side of the first conductivity type heavily doped layer 205, and a source metal layer 212 is drawn out in this contact hole trench 211.
The bottom of the contact hole trench 211 and under the heavily doped layer 205 of the first conductivity type are implanted to form a heavily doped second conductive material layer 203, and the distance between the left side of the gate dielectric layer 207 and the second conductive material layer 203 located on the left side thereof is equal to the distance between the right side of the gate dielectric layer 207 and the second conductive material layer 203 located on the right side thereof, so that the Rb is the same, and the conductivity of both sides is consistent.
The inner side surface and the lower side surface of the contact hole trench 211 form a second conductive material layer 203 of a second conductive type.
A method of fabricating a trench gate MOS semiconductor device, as shown in fig. 3, comprising the steps of:
step one, a substrate 213 is prepared.
Step two, a first epitaxial layer 201 is prepared on the substrate 213.
Step three, forming a body region 202 in the first epitaxial layer 201, i.e. forming a body region 202 doped with the second conductivity type by extending downwards on the top surface of the first epitaxial layer 201 doped with the first conductivity type.
Step four, a hard mask layer 214 is prepared on the body region 202, and selective etching is performed on the hard mask layer 214 to open the formation region of the gate trench 209, as shown in fig. 4A.
And fifthly, etching the body region 202 and the first epitaxial layer 201 by taking the hard mask layer 214 as a mask to form a gate trench 209, wherein the gate trench 209 penetrates through the body region 202, the bottom is positioned in the first epitaxial layer 201, and the top surface of the gate trench 209 is leveled with the top surface of the body region 202.
Step six, a gate dielectric layer 207 is formed on the inner surface of the gate trench 209.
Step seven, filling the gate trench 209 with a gate conductive material layer 208, wherein the upper surface of the gate conductive material layer 208 is higher than the top surface of the body region 202, i.e. higher than the top surface of the body region 202, typically not higher than the top surface of the hard mask layer 214, as shown in fig. 4B.
Step eight, preparing the dielectric layer 210 on top of and on the sides of the gate conductive material layer 208, which includes removing the hard mask layer 214.
Dielectric layer 210 is formed by high temperature oxidation using a gate conductive material layer 208 that oxidizes faster than body region 202.
Step 8.1, oxidizing (high temperature oxidizing) the gate conductive material on the top surface of the gate conductive material layer 208 to obtain an oxidized layer, such as a portion of the dielectric layer 210 shown in fig. 4C, which is referred to herein as a first dielectric layer, where the top surface of the gate conductive material layer 208 is still higher than the top surface of the body 202, and the first dielectric layer is higher than the hard mask layer 214; step 8.2, removing the hard mask layer 214; in step 8.3, a spacer process is used to prepare a second dielectric layer on the side of the first dielectric layer and the side of the portion of the gate conductive material layer 208 above the body region 202, to obtain a dielectric layer 210, as shown in fig. 4D. The dielectric layer 210 is manufactured in two parts, one part is a first dielectric layer, the other part is a second dielectric layer, the first dielectric layer and the second dielectric layer form an integrated structure, and the second dielectric layer can be manufactured by adopting a deposition method. Dielectric layer 210 is also known as a space structural layer.
Step nine, a first conductivity type heavily doped layer 205 is formed under the dielectric layer 210 and on the side surface of the gate trench 209, and the dielectric layer 210 is located on the upper surface of the first conductivity type heavily doped layer 205. Specifically, the first conductivity type heavily doped angled ion implant pre-forms a region of the first conductivity type heavily doped layer 205 in the body region 202.
Step ten, the contact hole trench 211 is prepared.
Contact hole trenches 211 are prepared on the outer sidewalls of the dielectric layer 210, on the outer sidewalls of the first conductivity-type heavily doped layer 205, and on the body region 202.
In step eleven, a second conductive material layer 203 of a second conductivity type is formed by ion implantation on the body region 202 inside the longitudinal trenches and on the lower side of the lateral trenches of the contact hole trenches 211. A second layer of conductive material 203 is located within the body region 202. Regions of the second conductivity type that are heavily doped in the formation of the regions of the preformed second conductive material layer 203 are formed by implantation.
Step twelve, source metal layer 212 is prepared.
In the embodiment of the invention, the first and second differentiated conduction types are adopted, the trench gate MOS semiconductor device is an N-type device, the first conduction type is N-type, and the second conduction type is P-type; the trench gate MOS semiconductor device may also be a P-type device, wherein the first conductivity type is P-type and the second conductivity type is N-type.
In the invention, the structure and the manufacture of the trench gate MOS semiconductor device are specially designed, the self-aligned structure and the formation structure of the source metal layer 212 are remanufactured by utilizing the difference of the material oxidation rate when the gate conductive material layer 208 in the gate trench 209 is higher than the top surface of the first epitaxial layer 201, namely, the top surface of the first conductive type heavily doped layer 205, so that the dispersion generated in the manufacturing process such as photoetching is eliminated, and the consistency and the performance of products are greatly improved.
In order to better increase the power density and reduce the on-resistance, the trench gate MOS semiconductor device adopts a structure of a longitudinal trench, a conductive channel is formed in the longitudinal direction, and a conductive source electrode is formed in the longitudinal direction of a grid electrode, so that the transverse dimension is reduced to achieve the structural design of increasing the density and reducing the resistance.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (9)
1. A trench-gate MOS semiconductor device, comprising:
a substrate (213);
-a first epitaxial layer (201) doped with a first conductivity type, located on said substrate (213);
-a body region (202) doped with a second conductivity type, located on said first epitaxial layer (201);
a heavily doped layer (205) of the first conductivity type located on the body region (202);
a gate trench (209) passing through the heavily doped layer (205) of the first conductivity type and the body region (202), the bottom being located in the first epitaxial layer (201);
a gate dielectric layer (207) on an inside surface of the gate trench (209);
-a layer of gate conductive material (208) located in the gate trench (209) and above the top of the gate trench (209);
a dielectric layer (210) on top of the gate conductive material layer (208), the gate dielectric layer (207), the gate trench (209) and the first conductivity type heavily doped layer (205);
the contact hole groove (211) is positioned in the body region (202), the contact hole groove (211) comprises a vertical groove and a horizontal groove, the top of the vertical groove is connected with the lower surface of the first conductive type heavily doped layer (205), and the bottom of the vertical groove is communicated with the horizontal groove;
a second layer of conductive material (203) located on the body region (202) connecting the heavily doped layer of the first conductivity type (205);
a contact hole trench (211) located on the dielectric layer (210), the first conductivity type heavily doped layer (205) and the second conductive material layer (203);
the source metal layer (212) is arranged on the surface of the dielectric layer (210), the outer side surface of the first conductive type heavily doped layer (205) and the upper surface of the second conductive material layer (203).
2. A trench-gate MOS semiconductor device as claimed in claim 1, characterized in that the distance of the left side of the gate dielectric layer (207) from the second conductive material layer (203) situated on its left side is equal to the distance of the right side of the gate dielectric layer (207) from the second conductive material layer (203) situated on its right side.
3. The trench-gate MOS semiconductor device of claim 1 wherein a dielectric layer (210) is coated on a surface of the portion of the gate conductive material layer (208) that is higher than the heavily doped layer (205) of the first conductivity type.
4. The trench-gate MOS semiconductor device of claim 1 wherein the second conductive material layer (203) comprises a second horizontal conductive material layer and a second vertical conductive material layer, the top of the second vertical conductive material layer being connected to the lower surface of the first conductivity-type heavily doped layer (205), the lower portion being connected to the second horizontal conductive material layer, the second horizontal conductive material layer being located on the body region (202) and outside the first conductivity-type heavily doped layer (205).
5. The trench-gate MOS semiconductor device of claim 4 wherein the contact trench (211) comprises a longitudinal trench and a lateral trench communicating the longitudinal trench, the longitudinal trench being located on an outer sidewall of the dielectric layer (210), an outer sidewall of the first conductivity-type heavily doped layer (205), and an outer sidewall of the second vertical conductive material layer, the lateral trench being located on an upper surface of the second horizontal conductive material layer.
6. The method for manufacturing a trench-gate MOS semiconductor device according to any one of claims 1 to 5, characterized by comprising the steps of:
step one: preparing a substrate (213);
step two: preparing a first epitaxial layer (201) doped with a first conductivity type on a substrate (213);
step three: forming a second conductivity type doped body region (202) in the first epitaxial layer (201);
step four: preparing a hard mask layer (214) on the body region (202);
step five: etching the first epitaxial layer (201) by taking the hard mask layer (214) as a mask to form a gate groove (209), wherein the gate groove (209) penetrates through the body region (202), the bottom is positioned in the first epitaxial layer (201), and the top surface of the gate groove (209) is leveled with the top surface of the first epitaxial layer (201);
step six: forming a gate dielectric layer (207) on the inner side surface of the gate trench (209);
step seven: filling a gate trench (209) with a layer of gate conductive material (208), an upper surface of the layer of gate conductive material (208) being higher than a top surface of the first epitaxial layer (201);
step eight: preparing a dielectric layer (210) on top of the gate conductive material layer (208) and on the side of the portion of the gate conductive material layer (208) above the body region (202), the process of preparing the dielectric layer (210) comprising the step of removing the hard mask layer (214);
step nine: forming a first conductive type heavily doped layer (205) on the side surface of the gate trench (209), wherein the dielectric layer (210) is positioned on the upper surface of the first conductive type heavily doped layer (205);
step ten: preparing a contact hole trench (211);
step eleven: preparing a second layer of conductive material (203);
step twelve: and preparing a source metal layer (212), and completing the preparation of the trench gate MOS semiconductor device.
7. The method for manufacturing a trench-gate MOS semiconductor device of claim 6, wherein the step eight specifically comprises: the dielectric layer (210) is prepared by using a high temperature oxidation method, wherein the oxidation speed of the grid electrode conductive material layer (208) is faster than that of the body region (202).
8. The method for manufacturing a trench-gate MOS semiconductor device of claim 6, wherein the step eight specifically comprises: oxidizing the top surface of the grid conductive material layer (208) to obtain a first dielectric layer; and then removing the hard mask layer (214), and preparing a second dielectric layer on the side surface of the first dielectric layer and the side surface of the grid electrode conductive material layer (208) by adopting a spacer process, wherein the dielectric layer consists of the first dielectric layer and the second dielectric layer.
9. The method of manufacturing a trench-gate MOS semiconductor device of claim 6 wherein the top surface of the gate conductive material layer (208) obtained in step seven is higher than the top surface of the body region (202) and not higher than the top surface of the hard mask layer (214).
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