CN104600119A - Power MOSFET (metal-oxide-semiconductor field effect transistor) device capable of achieving bidirectional current flowing and manufacturing method thereof - Google Patents
Power MOSFET (metal-oxide-semiconductor field effect transistor) device capable of achieving bidirectional current flowing and manufacturing method thereof Download PDFInfo
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- CN104600119A CN104600119A CN201510012655.5A CN201510012655A CN104600119A CN 104600119 A CN104600119 A CN 104600119A CN 201510012655 A CN201510012655 A CN 201510012655A CN 104600119 A CN104600119 A CN 104600119A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000002457 bidirectional effect Effects 0.000 title abstract 5
- 230000005669 field effect Effects 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 216
- 239000002184 metal Substances 0.000 claims abstract description 216
- 239000000758 substrate Substances 0.000 claims description 85
- 230000001413 cellular effect Effects 0.000 claims description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 50
- 238000009413 insulation Methods 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000002347 injection Methods 0.000 description 36
- 239000007924 injection Substances 0.000 description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010923 batch production Methods 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- Power Engineering (AREA)
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a power MOSFET device capable of achieving bidirectional current flowing and a manufacturing method thereof. The element area of the power MOSFET device capable of achieving bidirectional current flowing is composed of a grid electrode metal area, a source electrode metal area and a body electrode metal area; the inside of the source electrode metal area is composed of source electrode metal and an element cell, wherein the element cell is composed of a second conducting type first well region at the internal above of a first conducting type drift region, a first conducting type filling region at the internal above of the second conducting type first well region, and an MOS (metal oxide semiconductor) gate structure; the source electrode metal is electrically connected with the first conducting type filling region, and the first conducting type filling region isolates the source electrode metal and the second conducting type first well region; the body electrode metal area comprises a second conducting type second well region and body electrode metal, the second conducting type second well region and the second conducting type first well region are equipotential, and the second conducting type second well region is electrically connected with the body metal. The power MOSFET device capable of achieving bidirectional current flowing can achieve bidirectional flowing of current between a source electrode and a drain electrode and is simple in manufacturing process, low in cost and applicable to volume production.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, especially a kind ofly can realize power MOSFET device that electric current two-way circulates and manufacture method thereof, belong to the technical field of power semiconductor.
Background technology
Vertical DMOS (VDMOS) is a kind of known semiconductor power MOSFET element, and the advantages such as Yin Qiyi driving, low-loss are widely used in the middle of various electronic circuit.VDMOS is the three terminal device of a voltage driven type, comprise grid, source electrode and drain electrode, during break-over of device work, grid applies a driving voltage, between the source and drain of device, form raceway groove, the applying one that simultaneously drains makes charge carrier form electric current direct flowing of source electrode and drain electrode relative to the voltage Vds of source electrode; During device withstand voltage work, the driving voltage on grid is removed, and the raceway groove between source and drain disappears, and the voltage Vds between drain-source is born by the PN junction between drain-source.
The source electrode of VDMOS device is connected to source area, drain electrode is connected to drift region, wherein source area and drift region have identical dopant type, then had between source area and drift region the well region of opposite impurity type (Body) separate, the junction depth of well region will be deeper than the junction depth of source area, and they at gate surface place junction depth difference formed channel region, the structure of source area-well region-drift region also can form a parasitic bipolar transistor, source area corresponds to emitter, well region corresponds to base stage, drift region corresponds to collector electrode, in order to avoid this parasitic triode is misleaded when VDMOS works, all well region and source area can be shorted together in existing VDMOS device structure, the emitter junction that this assures parasitic triode can not forward bias, avoid the conducting of triode.Widely used is arrange source contact openings at device surface by the method that source area and well region are shorted together, the source metal of filling in source contact openings simultaneously with source area and well region in electrical contact, them are kept to have equal potentials, the groove-shaped VDMOS(Trench VDMOS as in Figure 43) device and Figure 44 plane VDMOS(Planar VDMOS) the cellular generalized section of device.
In Figure 43, groove-shaped VDMOS comprises MOS groove 103, and described MOS groove 103 is positioned at groove P trap 104 and extends vertically downward at described groove P trap 104, and the bottom land of MOS groove 103 is positioned at the N-type drift region 11 below groove P trap 104.In MOS groove 103, comprise trench gate oxide layer 106 and groove conductive polycrystalline silicon body 105, trench gate oxide layer 106 grows the inwall at MOS groove 103, and groove conductive polycrystalline body body 105 is filled in growth to be had in the MOS groove 103 of trench gate oxide layer 106; At the notch of MOS groove 103, channel insulation dielectric 106 is set, trench N-type injection region 107 is equipped with above the side of MOS groove 103 outer wall, groove source metal 109 covers on channel insulation dielectric 106, and respectively with trench N-type injection region 107, groove P trap 104 ohmic contact, thus obtaining gate terminal 100, source terminal 101 and drain electrode end 102, drain electrode end 102 is electrically connected with drain metal 9.
As in Figure 44, plane VDMOS comprises the plane P trap 110 be positioned at above N-type drift region 11, planar N-type injection region 111 is provided with above in plane P trap 110, described planar N-type injection region 111 is overlapping with the grid structure division of top, grid structure comprises planar gate oxide layer 115 and covers the multiplanar conductive polysilicon body 114 in described planar gate oxide layer 115, and described multiplanar conductive polysilicon body 114 and planar gate oxide layer 115 are all covered by planar insulative dielectric 112 bag tails.Planar insulative dielectric 112 is provided with plane source metal 113, described plane source metal 113 and planar N-type injection region 111 and plane P trap 110 ohmic contact.Multiplanar conductive polysilicon body 114 is also overlapped mutually with plane P trap 110 and N-type drift region 11 by planar gate oxide layer 115.
Traditional VDMOS device is when ON operation, the movement of charge carrier is all unidirectional, namely be all mobile to drain electrode by the source electrode of device, therefore, for the VDMOS device of given type, current flowing during ON operation is also unidirectional, but in some particular electrical circuit, circuit designers wishes that MOSFET element can realize two-way current flowing, and electric current is all flow through raceway groove, and so existing VDMOS device just cannot realize.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, there is provided a kind of and can realize power MOSFET device that electric current two-way circulates and manufacture method thereof, it can realize electric current two-way circulating between the source and drain, circulation path is all pass through raceway groove, and its manufacturing process is simple, with low cost, be suitable for batch production.
According to technical scheme provided by the invention, the described power MOSFET device that can realize electric current and two-way circulate, in the top plan view of described MOSFET element, comprise and be positioned at element region on semiconductor substrate and terminal protection district, described terminal protection district is positioned at the outer ring of element region, and terminal protection district is around embracing element district; In the cross section of described MOSFET element, described semiconductor substrate comprises superposed first conduction type drift region and is positioned at the first conductivity type substrate layer of bottom, and described first conductivity type substrate layer adjoins the first conduction type drift region; The upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate layer forms the second interarea of semiconductor substrate; Its innovation is:
In the top plan view of described MOSFET element, element region comprises gate metal district, source metal district and the metal area, body pole of mutually insulated isolation, comprises the source metal for the formation of source electrode and multiple cellulars in parallel distribution of being positioned at below described source metal in described source metal district;
On the cross section of described MOSFET element, cellular comprises the second conduction type first well region being positioned at the first top, conduction type drift region, the first conductivity type implanted region being positioned at described second conduction type first well region top and mos gate structure; Source metal is electrically connected with the first conductivity type implanted region, and source metal and the second conduction type first well region are isolated by the first conductivity type implanted region;
On the cross section of described MOSFET element, metal area, body pole comprises the second conduction type second well region being positioned at the first top, conduction type drift region and the body pole metal be positioned at above described second conduction type second well region, second conduction type second well region and the second conduction type first well region equipotential, and the second conduction type second well region is connected with body pole metal electric.
Drain metal is set at the second interarea of described semiconductor substrate, described drain metal and the first conductivity type substrate layer ohmic contact.
Cellular in source metal district is bar shaped, and described mos gate structure is groove-shaped grid structure or plane grid structure.
When described mos gate structure is groove-shaped grid structure, described mos gate structure comprises cellular groove, and described cellular groove is extended vertically downward by the first interarea, and the bottom land of cellular groove is positioned at the below of the second conduction type first well region; Channel insulation gate oxide is coated with at the inwall of cellular groove, and groove conductive polycrystalline silicon is filled with in the cellular groove being coated with channel insulation gate oxide, be coated with channel insulation dielectric layer at the notch of described cellular groove, insulated gate oxide layer and conductive polycrystalline silicon to be insulated mutually with source metal by channel insulation dielectric layer and isolate.
When described mos gate structure is plane grid structure, described mos gate structure comprises the planar insulative gate oxide be positioned on the first interarea, described planar insulative gate oxide is coated with multiplanar conductive polysilicon, described planar insulative gate oxide and multiplanar conductive polysilicon are all coated in planar insulative dielectric layer, and planar insulative dielectric layer is supported on the first interarea; Planar insulative gate oxide and the first conductivity type implanted region, the first conduction type drift region and the second conduction type first well region overlap mutually.
Described second conduction type first well region and the second conduction type second well region belong to same fabrication layer, and source metal and body pole intermetallic phase are not in contact with each other.
Can realize a manufacture method for the power MOSFET device that electric current two-way circulates, the manufacture method of described power MOSFET device comprises the steps:
A, provide the semiconductor substrate with two opposing main faces, two opposing main faces comprise the first interarea and the second interarea, the first conductivity type substrate layer and adjacent the first conduction type drift region being positioned at described first conductivity type substrate layer is comprised between the first interarea and the second interarea, the upper surface of the first conduction type drift region forms the first interarea, and the lower surface of the first conductivity type substrate layer forms the second interarea;
B, the first interarea of above-mentioned semiconductor substrate makes form the mos gate structure of MOSFET element;
C, on the first interarea of above-mentioned semiconductor substrate, the second conductive type impurity ion is injected in autoregistration, and form the second conduction type well region by high temperature knot, described second conduction type well region comprises the second conduction type first well region being positioned at formation source metal district and the second conduction type second well region being positioned at metal area, body pole, equipotential link between described second conduction type first well region and the second conduction type second well region;
D, on the first interarea of above-mentioned semiconductor substrate, carry out source region photoetching, and inject the first conductive type impurity ion, to be distributed in the first conductivity type implanted region of the second conduction type first well region internal upper part by high temperature knot;
E, on the first interarea of above-mentioned semiconductor substrate, deposit insulating medium layer;
F, contact hole photoetching and etching are carried out to above-mentioned insulating medium layer, to form required source contact openings and body pole contact hole;
G, above the first interarea of above-mentioned semiconductor substrate depositing metal, carry out metal lithographic and etching, the metal level needed for formation, described metal level comprises source metal and body pole metal, described source metal is filled in source contact openings, and is electrically connected with the first conductivity type implanted region; Body is extremely metal filled in the contact hole of body pole, and body pole metal is electrically connected with the second conduction type second well region of below, and body pole metal and source metal mutually insulated are isolated;
H, on the second interarea of above-mentioned semiconductor substrate deposit drain metal.
In described step b, when the mos gate structure of the MOSFET element of making is groove-shaped grid structure, comprise the steps:
B-1, on the first interarea of semiconductor substrate deposit hard mask layer;
B-2, optionally shelter and etch above-mentioned hard mask layer, to form the hard mask window of required through hard mask layer;
B-3, utilize above-mentioned hard mask window, the first interarea carries out anisotropic dry etch, and to form required cellular groove in semiconductor substrate, the degree of depth of described cellular groove in semiconductor substrate is less than the thickness of the first conduction type drift region;
B-4, the hard mask layer removed on above-mentioned first interarea, to grow channel insulation gate oxide in first interarea and cellular groove of above-mentioned semiconductor substrate;
B-5, have a channel insulation gate oxide in above-mentioned growth the first interarea on deposit groove conductive polycrystalline silicon, described conductive polycrystalline silicon covers on the channel insulation gate oxide on the first interarea, and be filled in inwall growth have in the cellular groove of channel insulation gate oxide;
B-6, etching remove groove conductive polycrystalline silicon above above-mentioned first interarea and channel insulation gate oxide, to obtain channel insulation gate oxide in cellular groove and groove conductive polycrystalline silicon.
In described step b, when the mos gate structure of the MOSFET element of making is plane grid structure, comprise the steps:
B-1 ', on the first interarea of semiconductor substrate growth plane insulated gate oxide layer;
B-2 ', have a planar insulative gate oxide in above-mentioned growth the first interarea on deposit multiplanar conductive polysilicon;
B-3 ', optionally etch above-mentioned multiplanar conductive polysilicon and planar insulative gate oxide, obtain required mos gate structure.
The material of described semiconductor substrate comprises silicon, and mos gate structure is bar shaped.
In both described " the first conduction type " and " the second conduction type ", for N-type MOSFET element, the first conduction type refers to N-type, and the second conduction type is P type; For P type MOSFET element, the first conduction type is just in time contrary with N type semiconductor device with the type of the second conduction type indication.
Advantage of the present invention:
Contrast traditional MOSFET element with three extraction electrodes (gate electrode, source electrode, drain electrode), MOSFET element of the present invention adds an extraction electrode: body electrode.The present invention passes through by the second conduction type first well region in source metal district by causing metal area, body pole after the second conduction type second well region equipotential link, and is drawn by body pole metal; Tagma metal, source metal, drain metal are not connected between two mutually, thus guarantee that body pole metal, source metal, drain metal can have independently current potential separately.
For N-type MOSFET element and P type MOSFET element, grid and the second conduction type well region can keep a potential difference when ON operation, this potential difference can guarantee the raceway groove conducting being positioned at the second conduction type well region, thus ensure no matter be that source electrode is to drain electrode high potential, or drain electrode can control conducting and the shutoff of raceway groove to grid in source electrode high potential two kinds of situations, so just can by arranging different source electrodes, drain electrode current potential realizes two-way circulating of electric current.And in available circuit design, two-way circulating of electric current is realized to hope, usual needs provide at least two independently MOSFET element, or by two MOSFET chip packages in the middle of a packaging body, use MOSFET element of the present invention, a MOSFET element just can realize two-way circulating of electric current, reduce the manufacturing cost of circuit, and the encapsulation of a MOSFET chip, they can be more to the leeway of the process choice such as encapsulation base island area, encapsulation bonding wire, and packaging cost also can reduce.
MOSFET element of the present invention; the second conduction type well region in element region is drawn separately as an independently electrode by the structure cell that changes in element region; and the variation on said structure does not relate to the terminal protection district of device; therefore; the element region of MOSFET element of the present invention can combine with the multiple terminal protection zone of existing MOSFET element and not need additionally to increase photolithography plate, thus reduces design difficulty and the manufacturing cost of device.
MOSFET element of the present invention, it just realizes above-mentioned functions by changing layout design, can combine with the manufacturing process of existing MOSFET element well, do not increase extra processing step, therefore, manufacture difficulty and cost do not increase, and are suitable for batch production.
Accompanying drawing explanation
Fig. 1 is the vertical view of the embodiment of the present invention 1.
Fig. 2 is the A-A cutaway view in Fig. 1.
Fig. 3 is the B-B cutaway view in Fig. 1.
Fig. 4 is the C-C cutaway view in Fig. 1.
Fig. 5 ~ Figure 22 is the concrete manufacturing technology steps cutaway view of the embodiment of the present invention 1, wherein
Fig. 5 is the structure cutaway view of semiconductor substrate of the present invention.
Fig. 6 is the cutaway view after the present invention obtains hard mask window.
Fig. 7 is the cutaway view after the present invention obtains cellular groove.
Fig. 8 is the cutaway view after deposit conductive polycrystalline silicon of the present invention.
Fig. 9 is the cutaway view after the present invention obtains groove conductive polycrystalline silicon.
Figure 10 ~ Figure 12 is the cutaway view after obtaining P type trap zone, wherein,
Figure 10 is the cutaway view after obtaining trench P-type first well region in A-A cutaway view.
Figure 11 is the cutaway view after obtaining trench P-type second well region in B-B cutaway view.
Figure 12 is the cutaway view after obtaining trench P-type second well region in C-C cutaway view.
Figure 13 ~ Figure 16 is the cutaway view obtaining groove N+ injection region, wherein,
Figure 13 is the cutaway view obtaining N+ injection region in A-A cutaway view.
Figure 14 is the cutaway view in B-B cutaway view.
Figure 15 is the cutaway view in C-C cutaway view.
Figure 16 ~ Figure 18 is the cutaway view after obtaining contact hole, wherein,
Figure 16 is the cutaway view after obtaining source contact openings in A-A cutaway view.
Figure 17 is the cutaway view after obtaining body pole contact hole in B-B cutaway view.
Figure 18 is the cutaway view after simultaneously obtaining source contact openings and body pole contact hole in C-C cutaway view.
Figure 19 ~ Figure 21 is the cutaway view after obtaining metal area, wherein,
Figure 19 is the cutaway view after obtaining groove source metal in A-A cutaway view.
Figure 20 is the cutaway view after obtaining groove body pole metal in B-B cutaway view.
Figure 21 is the cutaway view after simultaneously obtaining groove source metal and groove body pole metal in C-C cutaway view.
Figure 22 is the cutaway view after the second interarea obtains drain metal.
Figure 23 is the vertical view of the embodiment of the present invention 2.
Figure 24 is the cutaway view of D-D in Figure 23.
Figure 25 is the cutaway view of E-E in Figure 23.
Figure 26 is the cutaway view of F-F in Figure 23.
Figure 27 ~ Figure 42 is the concrete manufacturing technology steps cutaway view of the embodiment of the present invention 2, wherein
Figure 27 is the cutaway view of semiconductor substrate of the present invention.
Figure 28 is the cutaway view after the present invention obtains multiplanar conductive polysilicon layer.
Figure 29 is the cutaway view that the present invention obtains plane mos gate structure.
Figure 30 ~ Figure 32 is the cutaway view after obtaining P type trap zone, wherein,
Figure 30 is the cutaway view after obtaining planar P-type first well region in D-D cutaway view.
Figure 31 is the cutaway view after obtaining planar P-type second well region in E-E cutaway view.
Figure 32 is the cutaway view after obtaining planar P-type second well region in F-F cutaway view.
Figure 33 ~ Figure 35 is the cutaway view after obtaining plane N+injection region, wherein
Figure 33 is the cutaway view after obtaining plane N+injection region in D-D cutaway view.
Figure 34 is the cutaway view after obtaining plane N+injection region in E-E cutaway view.
Figure 35 is the cutaway view after obtaining plane N+injection region in F-F cutaway view.
Figure 36 ~ Figure 38 is the cutaway view after obtaining planar insulative dielectric layer, wherein
Figure 36 is the cutaway view after obtaining planar insulative dielectric layer in D-D cutaway view.
Figure 37 is the cutaway view after obtaining planar insulative dielectric layer in E-E cutaway view.
Figure 38 is the cutaway view after obtaining planar insulative dielectric layer in F-F cutaway view.
Figure 39 is the cutaway view after obtaining plane source metal in D-D cutaway view.
Figure 40 is the cutaway view after obtaining plane body pole metal in D-D cutaway view.
Figure 41 is the cutaway view after obtaining plane source metal and plane body pole metal in F-F cutaway view.
Figure 42 is the cutaway view of the present invention after the second interarea of semiconductor substrate obtains drain metal.
Figure 43 is the cutaway view of existing trench MOSFET device.
Figure 44 is the cutaway view of existing planar MOSFET device.
Description of reference numerals: 1-element region, 2-terminal protection district, 3-source metal district, 4-gate metal district, metal area, 5-body pole, 6-cellular, 7-source contact openings, 8-body pole contact hole, 9-drain metal, 10-N type substrate, 11-N type drift region, 12-trench P-type first well region, 13-cellular groove, 14-channel insulation gate oxide, 15-groove conductive polycrystalline silicon, 16-groove N+ injection region, 17-channel insulation dielectric layer, 18-groove source metal, 19-trench P-type second well region, 20-first interarea, 21-multiplanar conductive polysilicon body, 22-groove body pole metal, 23-second interarea, 24-hard mask layer, the hard mask window of 25-, 26-insulated trench gate oxysome, 27-groove conductive polycrystalline silicon body, 28-plane source metal, 29-planar P-type first well region, 30-plane N+injection region, 31-planar insulative dielectric layer, 32-multiplanar conductive polysilicon, 33-planar insulative gate oxide, 34-planar P-type second well region, 35-plane body pole metal, 36-planar insulated gate oxysome, 100-gate terminal, 101-source terminal, 102-drain electrode end, 103-MOS groove, 104-groove P trap, 105-trench gate oxide layer, 106-groove conductive polycrystalline silicon body, 107-trench N-type injection region, 108-channel insulation dielectric, 109-groove source metal, 110-plane P trap, 111-planar N-type injection region, 112-planar insulative dielectric, 113-plane source metal, 114-multiplanar conductive polysilicon body and 115-planar gate oxide layer.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
Power MOSFET device can adopt slot type structure or planarized structure, for N-type power MOSFET device, adopts two embodiments that are groove-shaped and plane to be described respectively to power MOSFET device.
Embodiment one
As shown in Figure 1, for vertical view during power MOSFET device employing slot type structure, in the top plan view of described MOSFET element, comprise the element region 1 on semiconductor substrate and terminal protection district 2, described terminal protection district 2 is around embracing element district 1, described element region 1 comprises gate metal district 4, source metal district 3 and metal area, body pole 5, wherein, gate metal district 4, mutually insulated isolation between source metal district 3 and metal area, body pole 5, gate metal is comprised in gate metal district 4, gate electrode can be formed by gate metal, groove source metal 18 is comprised in source metal district 3, source electrode can be formed by groove source metal 18, groove body pole metal 22 is comprised in metal area, body pole 5, the body electrode needed for one can be formed by groove body pole metal 22.In the embodiment of the present invention, groove source metal 18 in source metal district 3, groove body pole metal 22 in metal area, body pole 5 and the gate metal in gate metal district 4 all do not contact, gate metal district 4, metal area, body pole 5 lays respectively at the both sides in source metal district 3, in the specific implementation, gate metal district 4, source metal district 3, mutual alignment relation between metal area, body pole 5 is not limited to the position in figure, can arrange as required, as long as ensure source metal district 3, gate metal district 4 and the mutually insulated isolation of 5, metal area, body pole, namely corresponding Metal Phase is not in contact with each other.
In source metal district 3, arrange multiple cellular 6 in parallel distribution, described cellular 6, in bar shaped, has source contact openings 7 between adjacent cellular 6, and described source contact openings 7 also in bar shaped, is provided with tagma contact hole 8 in metal area, body pole 5.
As shown in Figure 2, on the cross section along A-A direction in accompanying drawing 1, described semiconductor substrate comprises the N-type substrate layer 10 being positioned at upper N type drift region 11 and being positioned at bottom, described N-type drift region 11 is adjacent with N-type substrate layer 10, the upper surface of described N-type drift region 11 forms the first interarea 20 of semiconductor substrate, and the lower surface of described N-type substrate layer 10 forms the second interarea 23 of semiconductor substrate.
Trench P-type first well region 12 of multiple regular array is provided with above in described N-type drift region 10, groove N+ injection region 16 is provided with above described trench P-type first well region 12, trench gate structure is separated with between adjacent two trench P-type first well regions 12, described trench gate structure comprises by the cellular groove 13 of the first interarea 20 to downward-extension, described cellular groove 13 degree of depth stretches in the N-type drift region 11 below trench P-type first well region 12, and the bottom land of cellular groove 13 is positioned at N-type drift region 11.Cellular groove 13 inwall is coated with channel insulation gate oxide 14, is filled with groove conductive polycrystalline silicon 15 in cellular groove 13, and described first interarea 20 is coated with channel insulation dielectric layer 17, and described channel insulation dielectric layer 17 wraps up the notch covering cellular groove 13.
Described channel insulation dielectric layer 17 is provided with source contact openings 7, described source contact openings 7 is between adjacent two trench gate, described channel insulation dielectric layer 17 is coated with groove source metal 18 above, described groove source metal 18 is filled source contact openings 7 and is electrical connected with groove N+ injection region 16, and described trench P-type first well region is not connected with groove source metal 18.Between two adjacent cellular grooves 13, groove N+ injection region 16 connects corresponding channel insulation gate oxide 14 respectively, groove source metal 18 covers on channel insulation dielectric layer 17, be electrically connected with groove N+ injection region 16 after being filled in groove source contact openings 7, because groove N+ injection region 16 is between groove source metal 18 and trench P-type first well region 12, groove N+ injection region 16 is by isolated between groove source metal 18 and trench P-type first well region 12.
As shown in Figure 3, on the cross section along B-B direction in accompanying drawing 1, the i.e. cutaway view of metal area, body pole 5, wherein, trench P-type second well region 19 is provided with above described N-type drift region 11, described first interarea 20 is coated with channel insulation dielectric layer 17, described channel insulation dielectric layer 17 is provided with tagma contact hole 8, described channel insulation dielectric layer 17 is coated with groove body pole metal 22 above, and described groove body pole metal 22 is filled tagma contact hole 8 and is electrical connected with trench P-type second well region 19 of below.In the embodiment of the present invention, being positioned at trench P-type second well region 19 of metal area, body pole 5 with trench P-type first well region 12 in source metal district 3 is same fabrication layer, and trench P-type second well region 19 and trench P-type first well region 12 link into an integrated entity, to make having equipotential between trench P-type second well region 19 and trench P-type first well region 12, thus trench P-type first well region 12 is electrically connected with the groove body pole metal 22 in metal area, body pole 5 by trench P-type second well region 19.
As shown in Figure 4, on the cross section along C-C direction in accompanying drawing 1, P type trap zone is provided with above described N-type drift region 11, described P type trap zone comprises P type first well region 12 being positioned at source metal district 3 and P type second well region 19 being positioned at metal area, body pole 5, is provided with groove N+ injection region 16 above P type first well region 12.Described first interarea 20 is coated with channel insulation dielectric layer 17, described channel insulation dielectric layer 17 is provided with source contact openings 7 and tagma contact hole 8, described channel insulation dielectric layer 17 is coated with groove source metal 18 and groove body pole metal 22 above, described groove source metal 18 to be filled in source contact openings 7 and to be electrical connected with groove N+ injection region 16, described groove body pole metal 22 is filled tagma contact hole 8 and is electrical connected with trench P-type second well region 19, is not connected mutually between described groove source metal 18 and groove body pole metal 22.
In the embodiment of the present invention, the channel insulation dielectric layer 17 in source metal district 3, metal area, body pole 5 is same fabrication layer, and the contact hole being positioned at source metal district 3 forms source contact openings 7, is positioned at the contact hole organizator pole contact hole 8 of metal area, body pole 5.
As shown in Fig. 5 ~ Figure 22, the power MOSFET device of said structure, is realized by following processing step:
A1, provide the semiconductor substrate with two opposing main faces, described semiconductor substrate comprises N-type substrate layer 10 and is positioned at the N-type drift region 11 above described N-type substrate layer 10; Described two opposing main faces comprise the first interarea 20 and the second interarea 23;
As shown in Figure 5, N-type substrate layer 10 adjoins with N-type drift region 11, and the upper surface of N-type drift region 11 forms the first interarea 20, the lower surface of N-type substrate layer 10 forms the second interarea 20, the material of semiconductor substrate comprises silicon, certainly, also can adopt other conventional semi-conducting materials.
B1, on the first interarea 20 of described semiconductor substrate deposit hard mask layer 24; The material of described hard mask layer 24 is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
C1, optionally shelter and etch hard mask layer 24, form the hard mask window 25 of etching groove;
As shown in Figure 6, the through hard mask layer 24 of hard mask window 25, obtaining hard mask window 25 for technical process is the technique of the art routine, repeats no more herein.
D1, utilize above-mentioned hard mask window 25, anisotropic dry etch semiconductor substrate on the first interarea 20, form cellular groove 13, described cellular groove 13 degree of depth is less than N-type drift region 11 thickness;
As shown in Figure 7, due to the first interarea 20 being coated with hard mask layer 24, under the effect of blocking of hard mask layer 24, etched by the semiconductor substrate below hard mask window 25, obtain cellular groove 13, detailed process is known by the art personnel.
E1, the hard mask layer 24 removed on the first interarea, on the first interarea 20 and cellular groove 13 inwall growth insulated trench gate oxysome 26;
Described insulated trench gate oxysome 26 can be silicon dioxide, insulated trench gate oxysome 26 is made to grow inwall at the first interarea 20 and cellular groove 13, by insulated trench gate oxysome 26 for the formation of channel insulation gate oxide 14 by techniques such as thermal oxidations.
F1, on described first interarea 20 deposit conductive polycrystalline silicon, described conductive polycrystalline silicon fills inwall growth simultaneously the cellular groove 13 of insulated trench gate oxysome 26;
Obtain groove conductive polycrystalline silicon body 27 after deposit conductive polycrystalline silicon, described groove conductive polycrystalline silicon body 27 covers on insulated trench gate oxysome 26.
Conductive polycrystalline silicon above g1, etching removal first interarea 20, obtains the conductive polycrystalline silicon in cellular groove 13;
As shown in Figure 9, after removing groove conductive polycrystalline body 27 on the first interarea 20 and channel insulation oxysome 26, obtain the channel insulation gate oxide 14 and the groove conductive polycrystalline silicon 15 that are positioned at cellular groove 13, namely form trench gate structure.
H1, on described first interarea 20, autoregistration implanting p-type foreign ion, and by high temperature knot formed P type trap zone;
As shown in Figure 10, Figure 11 and Figure 12, autoregistration p type impurity ion, and form the process of P type trap zone known by the art personnel by high temperature knot, concrete technology condition and process repeat no more.After formation P type trap zone, in source metal district 3, form trench P-type first well region 12, in metal area, body pole 5, form trench P-type second well region 19, trench P-type first well region 12 and trench P-type second well region 19 are interconnected integral.In the embodiment of the present invention, cellular 6, in bar shaped, mainly makes to be interconnected between trench P-type first well region 12 and trench P-type second well region 19 integral; Certainly, cellular 6 also can adopt other shape, as long as can ensure to be interconnected between trench P-type first well region 12 and trench P-type second well region 19 integral, ensures the equipotential state between trench P-type first well region 12 and trench P-type second well region 19.
I1, on described first interarea 20, carry out source region photoetching, and inject the N-type impurity ion of high concentration, and form N+ injection region by high temperature knot;
As shown in Figure 13, Figure 14 and Figure 15, carry out source region photoetching, inject the N-type impurity ion of high concentration, then form the process of N+ injection region known by the art personnel by high temperature knot, repeat no more herein.Described N+ injection region comprises groove N+ injection region 16, and described groove N+ injection region 16 is positioned at source metal district 3.
J1, on above-mentioned first interarea 20, deposit obtains channel insulation dielectric layer 17, and described channel insulation dielectric layer 17 is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
K1, on described channel insulation dielectric layer 17, carry out contact hole photoetching and etching, form source contact openings 7 and body pole contact hole 8, described source contact 7 hole between adjacent two groove conductive polycrystalline silicons 15,
As shown in Figure 16, Figure 17 and Figure 18, to the preparation technology that channel insulation dielectric layer 17 carries out contact hole photoetching and etches as the art routine, repeat no more herein.Source contact openings 7 and body pole contact hole 8 are all by channel insulation dielectric layer 17.
L1, on above-mentioned the first interarea being coated with channel insulation dielectric layer 17 20 depositing metals, carry out metal lithographic and etching, form groove source metal 18 and groove body pole metal 22, described groove source metal 18 is filled source contact openings 7 simultaneously and is electrically connected with groove N+ injection region 16, obturator pole contact hole 8 while of the metal 22 of described groove body pole is also electrically connected with trench P-type second well region 19, described groove source metal 18 is not connected, as shown in accompanying drawing 19, Figure 20 and Figure 21 mutually with groove body pole metal 22; Described groove source metal 18 and groove body pole metal 22 comprises aluminium or aluminium adds tungsten.
M1, on the second interarea 23 of described semiconductor substrate deposit drain metal 9, as shown in Figure 22, drain metal 9 comprises the golden or golden alloy of titanium, nickel, silver.
Embodiment two:
As shown in figure 23; for power MOSFET device adopts the vertical view of planarized structure; in the top plan view of described MOSFET element; comprise the element region 1 on semiconductor substrate and terminal protection district 2; described terminal protection district 2 is around embracing element district 1; described element region 1 comprises gate metal district 4, source metal district 3 and metal area, body pole 5; multiple bar shaped cellular 6 be parallel to each other is provided with in described source metal district 3; be provided with bar shaped source contact openings 7 between adjacent cellular 6, in metal area, described body pole 5, be provided with body pole contact hole 8.
As shown in figure 24, on the cross section along D-D direction in accompanying drawing 23, described semiconductor substrate comprises N-type drift region 11 and N-type substrate layer 10, described N-type drift region 11 is connected with N-type substrate layer 10, the upper surface of described N-type drift region 11 is the first interarea 20 of semiconductor substrate, and the lower surface of described N-type substrate layer 10 is the second interarea 23 of semiconductor substrate.The P type trap zone of multiple regular array is provided with above described N-type drift region 11, described P type trap zone comprises planar P-type first well region 29 and planar P-type second well region 34, plane N+injection region 30 is provided with above described planar P-type first well region 29, planar gate structure is separated with between adjacent two planar P-type first well regions 29, described planar gate structure comprises the multiplanar conductive polysilicon 32 above the first interarea 20, planar insulative gate oxide 33 is provided with between described multiplanar conductive polysilicon 32 and the first interarea 20, described first interarea 20 is provided with planar insulative dielectric layer 31, described planar insulative dielectric layer 31 wraps up overlay planes conductive polycrystalline silicon 32, described planar insulative dielectric layer 31 is provided with source contact openings 7, described planar insulative dielectric layer 31 is coated with plane source metal 28 above, described plane source metal 28 is filled source contact openings 7 and is electrically connected with plane N+injection region 30, described planar P-type first well region 29 is not connected with plane source metal 28,
As shown in Figure 25, on the cross section along E-E direction in accompanying drawing 23, planar P-type second well region 34 is provided with above described N-type drift region 11, described first interarea 20 is coated with planar insulative dielectric layer 31, described planar insulative dielectric layer 31 is provided with body pole contact hole 8, described planar insulative dielectric layer 31 is above coated with plane body pole metal 35, metal 35 obturator pole, described plane body pole contact hole 8 and being electrical connected with planar P-type second well region 34;
As shown in figure 26, on the cross section along F-F direction in accompanying drawing 23, P type trap zone is provided with above described N-type drift region 11, described P type trap zone comprises planar P-type first well region 29 and planar P-type second well region 34, plane N+injection region 30 is provided with above described planar P-type first well region 29, described first interarea 20 is coated with planar insulative dielectric layer 31, described planar insulative dielectric layer 31 is provided with source contact openings 7 and body pole contact hole 8, described planar insulative dielectric layer 31 is coated with plane source metal 28 and plane body pole metal 35 above, described plane source metal 28 is filled source contact openings 7 and is electrical connected with plane N+injection region 30, metal 28 obturator pole, described plane body pole contact hole 8 and being electrical connected with planar P-type second well region 34, be not connected mutually between described plane source metal 28 and plane body pole metal 35.
As shown in Figure 27 ~ Figure 42, the power MOSFET device of said structure, is realized by following processing step:
A2, provide the semiconductor substrate with two opposing main faces, described semiconductor substrate comprises N-type substrate layer 10 and is positioned at the N-type drift region 11 above described N-type substrate layer 10; Described two opposing main faces comprise the first interarea 20 and the second interarea 23, as shown in figure 27;
B2, on the first interarea 20 of described semiconductor substrate, grow insulated gate oxide layer, i.e. growth plane insulated gate oxysome 36 on the first interarea 20.
C2, have a planar insulated gate oxysome 36 in above-mentioned growth the first interarea 20 on deposit conductive polycrystalline silicon, as shown in figure 28, after deposit conductive polycrystalline silicon, obtain multiplanar conductive polysilicon body 21.
D2, optionally etch above-mentioned conductive polycrystalline silicon, obtain planar insulative gate oxide 33 and multiplanar conductive polysilicon 32, as shown in figure 29;
E2, on described first interarea 20, autoregistration implanting p-type foreign ion, and form P type trap zone by high temperature knot, as shown in Figure 30, Figure 31 and Figure 32, the P type trap zone obtained comprises planar P-type first well region 29 being positioned at source metal district 3 and planar P-type second well region 34 being positioned at metal area, body pole 5;
F2, on described first interarea 20, carry out source region photoetching, and inject the N-type impurity ion of high concentration, and form N-type injection region, as Figure 33, Figure 34 and Figure 35 by high temperature knot; Described plane N+injection region 30 is positioned at source metal district 3.
G2, on above-mentioned first interarea 20, deposit planar insulative dielectric layer 31;
H2, on described planar insulative dielectric layer 31, carry out contact hole photoetching and etching, form source contact openings 7 and body pole contact hole 8, described source contact openings 7 between adjacent two multiplanar conductive polysilicons 32, as shown in Figure 36, Figure 37 and Figure 38;
I2, on above-mentioned the first interarea 20 being coated with planar insulative dielectric layer 31 depositing metal, carry out metal lithographic and etching, form plane source metal 28 and plane body pole metal 35, described plane source metal 28 is filled source contact openings 7 simultaneously and is electrically connected with plane N+injection region 30, obturator pole contact hole 8 while of the metal 35 of described plane body pole is also electrically connected with planar P-type second well region 34, described plane source metal 28 is not connected, as shown in Figure 39, Figure 40 and Figure 41 mutually with plane body pole metal 35;
J2, on the second interarea 20 of described semiconductor substrate deposit drain metal 9, as shown in figure 42, the drain electrode end of power MOSFET device can be formed by drain metal 9.
The working mechanism of MOSFET element of the present invention is: by body pole metal energy organizator electrode, can form source electrode, can form drain electrode by drain metal 9 by source metal.Owing to not being connected mutually between two between the source metal in the body pole metal of metal area, body pole 5, source metal district 3, drain metal 9, therefore, the body electrode of MOSFET element, source electrode and drain electrode can apply separately independently current potential.
For N-type MOSFET element, device is when ON operation, current potential on body electrode and source electrode, the current potential in both drain electrodes with an electrode of more electronegative potential is equal, gate electrode applies a positive voltage, gate electrode is made to have a high potential to body electrode, and described high potential can guarantee the complete conducting of raceway groove being positioned at body electrode, now, one end that electrons has electronegative potential by raceway groove from source electrode and drain electrode flows to the other end, specifically, when body electrode and source electrode have electronegative potential, when drain electrode has high potential, electronics flows to drain electrode by source electrode by raceway groove, when body electrode and drain electrode have electronegative potential, when source electrode has high potential, electronics flows to source electrode by drain electrode by raceway groove.
Device is when ending withstand voltage work, specifically, when body electrode and source electrode have electronegative potential, when drain electrode has high potential, the PN junction reverse bias that drain electrode and body pole are formed, thus producing depletion layer, to carry out supports withstand voltage, when body electrode and drain electrode have electronegative potential, when source electrode has high potential, the PN junction reverse bias that source electrode and body electrode are formed, thus producing depletion layer, to carry out supports withstand voltage.
For P type MOSFET element, device is when ON operation, current potential on body electrode and source electrode, the current potential in both drain electrodes with an electrode of more high potential is equal, gate electrode applies a negative voltage, gate electrode is made to have an electronegative potential to body, and described electronegative potential can guarantee the complete conducting of raceway groove being positioned at metal area, body pole 5, now, one end that hole can have a high potential by raceway groove from source electrode and drain electrode flows to the other end, specifically, when body electrode and source electrode have high potential, when drain electrode has electronegative potential, hole flows to drain electrode by source electrode by raceway groove, when body electrode and drain electrode have high potential, when source electrode has electronegative potential, hole flows to source electrode by drain electrode by raceway groove.
Device is when ending withstand voltage work, specifically, when body electrode and source electrode have high potential, when drain electrode has electronegative potential, the PN junction reverse bias that drain electrode and body electrode are formed, thus producing depletion layer, to carry out supports withstand voltage, when body electrode and drain electrode have high potential, when source electrode has electronegative potential, the PN junction reverse bias that source electrode and body electrode are formed, thus producing depletion layer, to carry out supports withstand voltage.
Claims (10)
1. the power MOSFET device that can realize electric current and two-way circulate, in the top plan view of described MOSFET element, comprise and be positioned at element region on semiconductor substrate and terminal protection district, described terminal protection district is positioned at the outer ring of element region, and terminal protection district is around embracing element district; In the cross section of described MOSFET element, described semiconductor substrate comprises superposed first conduction type drift region and is positioned at the first conductivity type substrate layer of bottom, and described first conductivity type substrate layer adjoins the first conduction type drift region; The upper surface of the first conduction type drift region forms the first interarea of semiconductor substrate, and the lower surface of the first conductivity type substrate layer forms the second interarea of semiconductor substrate; It is characterized in that:
In the top plan view of described MOSFET element, element region comprises gate metal district, source metal district and the metal area, body pole of mutually insulated isolation, comprises the source metal for the formation of source electrode and multiple cellulars in parallel distribution of being positioned at below described source metal in described source metal district;
On the cross section of described MOSFET element, cellular comprises the second conduction type first well region being positioned at the first top, conduction type drift region, the first conductivity type implanted region being positioned at described second conduction type first well region top and mos gate structure; Source metal is electrically connected with the first conductivity type implanted region, and source metal and the second conduction type first well region are isolated by the first conductivity type implanted region;
On the cross section of described MOSFET element, metal area, body pole comprises the second conduction type second well region being positioned at the first top, conduction type drift region and the body pole metal be positioned at above described second conduction type second well region, second conduction type second well region and the second conduction type first well region equipotential, and the second conduction type second well region is connected with body pole metal electric.
2. the power MOSFET device that can realize electric current and two-way circulate according to claim 1, is characterized in that: arrange drain metal at the second interarea of described semiconductor substrate, described drain metal and the first conductivity type substrate layer ohmic contact.
3. the power MOSFET device that can realize electric current and two-way circulate according to claim 1, is characterized in that: the cellular in source metal district is bar shaped, and described mos gate structure is groove-shaped grid structure or plane grid structure.
4. the power MOSFET device that can realize electric current and two-way circulate according to claim 3, it is characterized in that: when described mos gate structure is groove-shaped grid structure, described mos gate structure comprises cellular groove, described cellular groove is extended vertically downward by the first interarea, and the bottom land of cellular groove is positioned at the below of the second conduction type first well region; Channel insulation gate oxide is coated with at the inwall of cellular groove, and groove conductive polycrystalline silicon is filled with in the cellular groove being coated with channel insulation gate oxide, be coated with channel insulation dielectric layer at the notch of described cellular groove, insulated gate oxide layer and conductive polycrystalline silicon to be insulated mutually with source metal by channel insulation dielectric layer and isolate.
5. the power MOSFET device that can realize electric current and two-way circulate according to claim 3, it is characterized in that: when described mos gate structure is plane grid structure, described mos gate structure comprises the planar insulative gate oxide be positioned on the first interarea, described planar insulative gate oxide is coated with multiplanar conductive polysilicon, described planar insulative gate oxide and multiplanar conductive polysilicon are all coated in planar insulative dielectric layer, and planar insulative dielectric layer is supported on the first interarea; Planar insulative gate oxide and the first conductivity type implanted region, the first conduction type drift region and the second conduction type first well region overlap mutually.
6. the power MOSFET device that can realize electric current and two-way circulate according to claim 1, is characterized in that: described second conduction type first well region and the second conduction type second well region belong to same fabrication layer, and source metal and body pole intermetallic phase are not in contact with each other.
7. can realize a manufacture method for the power MOSFET device that electric current two-way circulates, it is characterized in that, the manufacture method of described power MOSFET device comprises the steps:
(a), the semiconductor substrate with two opposing main faces is provided, two opposing main faces comprise the first interarea and the second interarea, the first conductivity type substrate layer and adjacent the first conduction type drift region being positioned at described first conductivity type substrate layer is comprised between the first interarea and the second interarea, the upper surface of the first conduction type drift region forms the first interarea, and the lower surface of the first conductivity type substrate layer forms the second interarea;
(b), make on the first interarea of above-mentioned semiconductor substrate and form the mos gate structure of MOSFET element;
(c), on the first interarea of above-mentioned semiconductor substrate, the second conductive type impurity ion is injected in autoregistration, and form the second conduction type well region by high temperature knot, described second conduction type well region comprises the second conduction type first well region being positioned at formation source metal district and the second conduction type second well region being positioned at metal area, body pole, equipotential link between described second conduction type first well region and the second conduction type second well region;
(d), on the first interarea of above-mentioned semiconductor substrate, carry out source region photoetching, and inject the first conductive type impurity ion, to be distributed in the first conductivity type implanted region of the second conduction type first well region internal upper part by high temperature knot;
(e), on the first interarea of above-mentioned semiconductor substrate, deposit insulating medium layer;
(f), contact hole photoetching and etching are carried out to above-mentioned insulating medium layer, to form required source contact openings and body pole contact hole;
(g), above the first interarea of above-mentioned semiconductor substrate depositing metal, carry out metal lithographic and etching, the metal level needed for formation, described metal level comprises source metal and body pole metal, described source metal is filled in source contact openings, and is electrically connected with the first conductivity type implanted region; Body is extremely metal filled in the contact hole of body pole, and body pole metal is electrically connected with the second conduction type second well region of below, and body pole metal and source metal mutually insulated are isolated;
(h), on the second interarea of above-mentioned semiconductor substrate deposit drain metal.
8. can realize the manufacture method of the power MOSFET device that electric current two-way circulates according to claim 7, it is characterized in that, in described step (b), when the mos gate structure of the MOSFET element of making is groove-shaped grid structure, comprise the steps:
(b-1), deposit hard mask layer on the first interarea of semiconductor substrate;
(b-2), optionally shelter and etch above-mentioned hard mask layer, to form the hard mask window of required through hard mask layer;
(b-3), utilize above-mentioned hard mask window, the first interarea carries out anisotropic dry etch, to form required cellular groove in semiconductor substrate, the degree of depth of described cellular groove in semiconductor substrate is less than the thickness of the first conduction type drift region;
(b-4), the hard mask layer removed on above-mentioned first interarea, to grow channel insulation gate oxide in first interarea and cellular groove of above-mentioned semiconductor substrate;
(b-5) deposit groove conductive polycrystalline silicon on the first interarea, having channel insulation gate oxide in above-mentioned growth, described conductive polycrystalline silicon covers on the channel insulation gate oxide on the first interarea, and be filled in inwall growth have in the cellular groove of channel insulation gate oxide;
(b-6), etching removes groove conductive polycrystalline silicon above above-mentioned first interarea and channel insulation gate oxide, to obtain channel insulation gate oxide in cellular groove and groove conductive polycrystalline silicon.
9. can realize the manufacture method of the power MOSFET device that electric current two-way circulates according to claim 7, it is characterized in that, in described step (b), when the mos gate structure of the MOSFET element of making is plane grid structure, comprise the steps:
(b-1 '), on the first interarea of semiconductor substrate growth plane insulated gate oxide layer;
(b-2 '), have a planar insulative gate oxide in above-mentioned growth the first interarea on deposit multiplanar conductive polysilicon;
(b-3 '), optionally etch above-mentioned multiplanar conductive polysilicon and planar insulative gate oxide, obtain required mos gate structure.
10. can realize the manufacture method of the power MOSFET device that electric current two-way circulates according to claim 7, it is characterized in that, the material of described semiconductor substrate comprises silicon, and mos gate structure is bar shaped.
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| CN113130660A (en) * | 2021-03-26 | 2021-07-16 | 先之科半导体科技(东莞)有限公司 | Vertically arranged MOSFET (Metal-oxide-semiconductor field Effect transistor) |
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