CN110047930A - VDMOS device - Google Patents
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- CN110047930A CN110047930A CN201910261385.XA CN201910261385A CN110047930A CN 110047930 A CN110047930 A CN 110047930A CN 201910261385 A CN201910261385 A CN 201910261385A CN 110047930 A CN110047930 A CN 110047930A
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- 239000007924 injection Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000002513 implantation Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 108091006146 Channels Proteins 0.000 description 38
- 230000015556 catabolic process Effects 0.000 description 22
- 238000000034 method Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 230000001413 cellular effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001727 in vivo Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- -1 right For VDMOS Proteins 0.000 description 2
- 238000010792 warming Methods 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
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- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses a kind of VDMOS devices, have the epitaxial layer of the first conduction type, the channel region with the second conduction type and the source region in channel region in epitaxial layer in the semiconductor substrate of the first conduction type；Between the channel region, also with the injection region of the first conduction type；In the epitaxial surface of first conduction type, also there is the grid of gate oxide and the VDMOS device；Also there is oxide layer, the oxide layer is integrally covered on semiconductor substrate surface, grid is wrapped up above the grid；Contact hole passes through the source region of oxide layer and lower section, and bottom is located in channel region, source region is drawn；In the channel region, also with the injection region of the second conduction type, the injection region of second conduction type is downward from area surface, and bottom is more than that channel region is located in epitaxial layer；The injection region of second conduction type is no more than source region in transverse direction.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of VDMOS device.
Background technique
The device of VDMOS (vertical double-diffused MOS) is a kind of power device, and polysilicon gate is buried in source metal
Below, source current passes through horizontal channel, and pass through the vertical drift region N- again by grid build up beneath layer and is left to drain electrode, this
The power MOS of kind of structure, with the super large-scale integration process compatible of present high development, therefore develops very in technique
Fastly.
The structure of VDMOS is as shown in Figure 1, here by taking NMOS as an example, wherein 1 is the substrate of heavy doping, the resistivity of substrate
Usually between 1~2m Ω cm.The thickness of substrate usually between 250~300 μm, carrys out 8 cun of pieces for 6 cun of pieces
It says usually near 200 μm.In order to reduce the resistance of substrate, it is often desirable that the thickness of substrate can get over Bao Yuehao.Substrate be with
What the drain electrode of device was connected.2 be the epitaxial layer above heavy doping substrate, the breakdown voltage that the resistivity of epitaxial layer is realized with needs
Related, breakdown voltage is higher, and the resistivity of epitaxial layer is lower.Breakdown voltage is higher, and the thickness of epitaxial layer is thicker.3 be channel, right
For VDMOS, channel is usually that self aligned p-type injection promotes to be formed plus high temperature, can save a Zhang Guang in this way
It cuts blocks for printing.Simultaneously as what autoregistration was formed, the uniformity of threshold voltage also can be more preferable.6 grids being made of polysilicon, it is right
For NMOS, polysilicon is N-type heavy doping；For PMOS, polysilicon is p-type heavy doping.5 be gate oxidation
Layer, usually silica.Its thickness is usually between 500 to 1500 angstroms.4 be N-type injection, its effect is to reduce device
JFET effect reduces the conducting resistance of device.N-type injection, dosage is usually 1E12~3E12cm-2Between, the energy of injection is logical
Often between 60keV to 200keV.7 be the source region of heavy doping, and usually arsenic injects.8 be metal throuth hole, heavily doped for connecting 7
Miscellaneous source region and 3 channels.9 be source metal, and usually AlCu, thickness is usually at 3 μm or more.
When Fig. 2 is that a typical 650V VDMOS closes on breakdown, the distribution map of intracorporal electric field strength.It can be seen that
The distribution of electric field strength in vivo is similar to a triangle, is inclined.By surface to being gradually reduced in vivo.Drift region
Doping concentration it is higher, the slope of decline is bigger, and the breakdown voltage of device is also lower.For this purpose, in order to improve the breakdown of VDMOS
Voltage, it usually needs the thickness of drift region is increased, doping concentration reduces.Therefore the ratio conducting resistance of device can be with requiring
Breakdown voltage is improved and is sharply increased.
For this purpose, super junction MOSFET is suggested, super junction MOSFET is not both with the maximum of VDMOS, square under the channel
Drift region in insert lateral P column 10, as shown in Figure 3.There are two types of implementation methods at present for the formation of P column, and one is multiple
It is epitaxially formed.In this implementation, P column is then to add the thermal process of high temperature by multiple ion implanting, allows every section of P
Column is connected to form a whole.In this implementation, each processing step is fairly simple, but processing step is more, and
The alignment of every layer of P column is difficult point.Another is the fill process based on deep etching and P-type silicon.This implementation, has
Processing step is few.But the depth-to-width ratio height of its deep etching is a big difficulty, while how to guarantee that the fill process of P-type silicon does not have
Defect is also a big difficulty.
When Fig. 4 is that a typical 650V super junction MOSFET closes on breakdown, the distribution map of intracorporal electric field strength.Figure
Middle this emulated super junction, the formation of P column are by being repeatedly epitaxially formed.
The structure using super junction MOSFET can be seen, the distribution of electric field strength in vivo is substantially flat.This
Be because P column carried out under very low voltage with N-type drift region it is completely depleted, be equivalent to drift region equivalent doping concentration become
It is 0, close to intrinsic.
For theoretically, regardless of how high the doping concentration of N-type drift region is, as long as P column is completely depleted with N-type drift region, electricity
The distribution of field intensity in vivo be all it is flat, close to ideal.Therefore super junction MOSFET structure is used, with traditional VDMOS
It compares, the breakdown voltage of device can be greatly improved in the case where not reducing drift doping concentration；Or it is hit not reducing
In the case where wearing voltage, the conducting resistance of drift region is greatly reduced.With great advantage.
Accordingly, it is desirable to be able to realize the structure for being similar to super junction, the breakdown potential of Lai Tigao device on the basis of VDMOS
Pressure, or in the case where guaranteeing that breakdown voltage is constant, conducting resistance is compared in reduction.
For VDMOS device, terminal structure, usually by JTE (knot terminal extension)+field plate either Floating
Ring (floating field ring)+field plate is realized.
It is the terminal structure of JTE+ field plate shown in Fig. 5.11 be JTE in figure, and the lateral length of JTE is usually determined by breakdown voltage
It is fixed.The breakdown voltage of device is higher, and the length of JTE is longer.In order to reduce the curvature effect of device, the junction depth of usual JTE is remote
Far it is deeper than the junction depth in the area Body 3.In actual process, junction depth may be that 2 times of body area 3 are even more.In actual process,
The injection of JTE is just made in the first step of device, is that it is non-then to carry out a step using the p-type injection with reticle
The high Warming processes of Chang Shen, make the junction depth of JTE deep as far as possible, to reduce the curvature effect of device.Allow the breakdown voltage of terminal
It is higher.The Implantation Energy of JTE is usually between 80~300keV, and the dosage of injection is usually in 1E13~3E13cm-2Between.High temperature
The temperature of thermal process is usually at 1150 DEG C or more, and the time was at 300 minutes or more.
Either using the terminal structure of Floating Ring+ field plate as shown in FIG. 6, wherein 12 be Floating
Ring.Wherein first Floating Ring 12a is connected with channel region 3.12b and 12c is floating.The breakdown potential of device
Press BV higher, the number of Floating Ring is more.The distance between Floating Ring is gradually increased.In order to reduce
The deeper curvature effect, the junction depth that we are intended to Floating Ring the better.Floating Ring is the same as JTE type in practice
Terminal is the same, is realized in the first step, then there is the very high thermal process of a step, makes its junction depth deeper to reduce curvature effect
It answers.There can be the field plate of floating above Floating Ring, effect can be enhanced in the field plate for increasing floating.Floating Ring
Implantation Energy usually between 60~300keV, the dosage of injection is usually in 1E13~5E15cm-2Between.High Warming processes
Temperature is usually at 1150 DEG C or more, and the time was at 300 minutes or more.
In above-mentioned traditional device architecture, the structure of these high junction depths such as JTE either Floating Ring is
Used in the terminal of device, it is not introduced into the cellular region of device.
Summary of the invention
Technical problem to be solved by the present invention lies in a kind of VDMOS device is provided, JTE or floating field ring are introduced into
The cellular region of device forms the super-junction structure for being similar to P column.
With the epitaxial layer of the first conduction type in the semiconductor substrate of the first conduction type, in the epitaxial layer
In, include the channel region with the second conduction type of the VDMOS device, includes VDMOS device in the channel region
The source region with the first conduction type of part；
Between the channel region, also with the injection region of the first conduction type, the injection region laterally connects with channel region
It connects；
In the epi-layer surface of first conduction type, also there is the grid of gate oxide and the VDMOS device；Institute
Also there is oxide layer, the oxide layer is integrally covered on semiconductor substrate surface, grid is wrapped up above the grid stated；
Contact hole passes through the source region of oxide layer and lower section, and bottom is located in channel region, source region is drawn；
In the channel region, also with the injection region of the second conduction type, the injection region of second conduction type from
Area surface is downward, and bottom is more than that channel region is located in epitaxial layer；
The injection region of second conduction type is no more than source region in transverse direction.
Further, the injection region of second conduction type, injection junction depth are not less than 2 times of channel region.
Further, the oxidation layer surface also has source metal, the source metal and contact holes contact, is formed
The source electrode of VDMOS device.
Further, the grid is the polysilicon gate of heavy doping, the type one of doping type and VDMOS device
It causes, i.e. its polysilicon gate of N-type VDMOS extremely N-type heavy doping, the extremely p-type heavy doping of its polysilicon gate of p-type VDMOS.
To solve the above problems, the present invention also provides a kind of VDMOS device, in the semiconductor substrate of the first conduction type
Epitaxial layer with the first conduction type includes the VDMOS device with the second conductive-type in the epitaxial layer
The channel region of type includes the source region with the first conduction type of VDMOS device in the channel region；
Between the channel region, also with the injection region of the first conduction type, the injection region laterally connects with channel region
It connects；
In the epi-layer surface of first conduction type, also there is the grid of gate oxide and the VDMOS device；Institute
Also there is oxide layer, the oxide layer is integrally covered on semiconductor substrate surface, grid is wrapped up above the grid stated；
Contact hole passes through the source region of oxide layer and lower section, and bottom is located in channel region, source region is drawn；
In the channel region, also with the injection region of the second conduction type, the injection region of second conduction type from
Area surface is downward, and bottom is more than that channel region is located in epitaxial layer；
The injection region of second conduction type is no more than source region in transverse direction；
The epitaxial layer of first conduction type is divided into the different bilevel epitaxial layer of doping concentration, wherein
The doping concentration of upper layer epitaxial layer is greater than the epitaxial layer of lower layer；And the injection region depth of second conduction type is more than upper layer
Epitaxial layer, bottom is located in lower layer's epitaxial layer.
Further, the injection region of second conduction type, injection junction depth are not less than 2 times of channel region.
Further, the oxidation layer surface also has source metal, the source metal and contact holes contact, is formed
The source electrode of VDMOS device.
To solve the above problems, the present invention also provides a kind of VDMOS device, in the semiconductor substrate of the first conduction type
Epitaxial layer with the first conduction type includes the VDMOS device with the second conductive-type in the epitaxial layer
The channel region of type includes the source region with the first conduction type of VDMOS device in the channel region；
In the epi-layer surface of first conduction type, also there is the grid of gate oxide and the VDMOS device；Institute
Also there is oxide layer, the oxide layer is integrally covered on semiconductor substrate surface, grid is wrapped up above the grid stated；
Contact hole passes through the source region of oxide layer and lower section, and bottom is located in channel region, source region is drawn；
In the channel region, also with the injection region of the second conduction type, the injection region of second conduction type from
Area surface is downward, and bottom is more than that channel region is located in epitaxial layer；
The injection region of second conduction type is no more than source region in transverse direction；
Between the channel region, also with the injection region of the first conduction type, the injection region laterally connects with channel region
It connects；The injection region of first conduction type, is divided into upper layer and lower layer, is formed by different Implantation Energies.
Further, the injection region of first conduction type, at the middle and upper levels the Implantation Energy of injection region be 60~
200keV, implantation dosage are 1E12~3E12cm-2, upper layer injection region can be by its JFET effect；Lower layer injection region
Implantation Energy is 600~2000keV, and implantation dosage is 1E12~3E12cm-2, improve the doping concentration of surface drift region.
Further, the injection region of second conduction type, injection junction depth are not less than 2 times of channel region.
JTE or floating field ring are introduced into cellular region, are formed and be similar to super junction by VDMOS device of the present invention
Effect so that electric-field intensity distribution is similar to perfect condition with drift region assisted depletion, to improve breakdown voltage, or
It is to reduce in the case where breakdown voltage is constant and compare conducting resistance.
Detailed description of the invention
Fig. 1 is the sectional structure chart of common VDMOS device.
It is horizontal in the internal field distribution schematic diagram for closing on breakdown voltage and being, figure that Fig. 2 is typical 650V VDMOS device
Coordinate is the depth from device surface inwards, and ordinate is electric field strength.
Fig. 3 is the schematic diagram of the section structure with the MOSFET of super junction.
Fig. 4 is typical 650V super junction MOSFET element in the internal field distribution schematic diagram for closing on breakdown voltage and being,
Abscissa is the depth from device surface inwards in figure, and ordinate is electric field strength.
Fig. 5 is schematic diagram of the VDMOS device using JTE and the terminal structure of field plate.
Fig. 6 is schematic diagram of the VDMOS device using the terminal structure of floating field ring.
Fig. 7 is schematic diagram of the present invention in VDMOS device cellular region introducing super-junction structure.
Fig. 8 is that the present invention introduces super-junction structure in VDMOS device cellular region and uses the schematic diagram of two-layer epitaxial layer.
Fig. 9 be the present invention VDMOS device cellular region introduce super-junction structure and injected using different-energy twice to be formed it is double
The schematic diagram of layer injection region.
Description of symbols
1 is substrate, and 2 (2a, 2b) are extensions, and 3 be channel region, and 4 be injection region, and 5 be gate oxide, and 6 be grid, and 7 be source
Area, 8 be contact hole, and 9 be source metal, and 10 be P column, and 11 be JTE, and 12 be floating field ring.
Specific embodiment
JTE or floating field ring are introduced into the cellular region of device by a kind of VDMOS device of the present invention, form class
It is similar to the super-junction structure of P column.
In the embodiment of the present invention by taking N-type VDMOS as an example for illustrate, for p-type VDMOS, the present invention is equally applicable.
As shown in fig. 7, the epitaxial layer 2 in the semiconductor substrate 1 of N+ with N- includes in the epitaxial layer
The P-type channel area 3 of the VDMOS device includes the N+ source region 7 of VDMOS device in the channel region 3.
Between the channel region 3, also with the injection region 4 of N-type, the injection region 4 and 3 lateral connection of channel region.
On 2 surface of epitaxial layer of the N-, also there is the grid 6 of gate oxide 5 and the VDMOS device；The grid
The polysilicon gate extremely adulterated, for N-type VDMOS, polysilicon gate extremely N-type heavy doping carrys out p-type VDMOS device
It says, polysilicon gate extremely p-type heavy doping.Also there is oxide layer, the oxide layer is integrally covered on half above the grid
Conductor substrate surface, grid is wrapped up.
Contact hole 8 passes through the source region 7 of oxide layer and lower section, and bottom is located in channel region, source region is drawn.
In the channel region, also with the injection region 11 (12) of p-type, which is that the p-type of termination environment is injected shape
Introduce cellular region at JTE or floating field ring, improve the junction depth of p-type injection, the junction depth for injecting p-type double with
On, p-type junction depth increases, and is equivalent to one section of P column, can be exhausted with N-type drift region, so the electric field of this section can allow
Strength distribution curve keeps horizontal perfect condition as far as possible, to improve its breakdown voltage, or constant in breakdown voltage
In the case of, it reduces it and compares conducting resistance.The p-type injection region 11 (12) is downward from area surface, and bottom is more than channel position
In epitaxial layer.
The injection region 11 (12) of the p-type, source region is no more than in transverse direction, and injection junction depth is not less than 2 times of channel region.
The oxidation layer surface also has source metal, the source metal and contact holes contact, forms VDMOS device
Source electrode.
Because increasing p-type injection region 11 (12) in the cellular region of device, they have higher junction depth, so that device table
Face forms one kind and is similar to super-junction structure, and the doping concentration of silicon face can be improved, for this purpose, can mixing 2 surface of epitaxial layer
Miscellaneous concentration improves.
As shown in figure 8, This structure increases double-deck epitaxial layer 2a and 2b, the doping of 2b compared with structure shown in Fig. 7
Concentration is greater than the doping concentration of 2a.It is a kind of can with scheme be that, for 650V device, the resistivity that epitaxial layer generallys use is 17
Ω·cm.Therefore it can be the doping concentration of traditional VDMOS in non-super knot point, doping concentration, be 17 Ω cm.And
One section of top, because using the structure similar to super junction, the doping concentration on surface can be greatly improved.It therefore, can be with
Using 2 Ω cm, the even epitaxial layer of 1 Ω cm resistivity.As long as the P column selection of 11 (12) is suitable, can be complete by 2a
It exhausts, the breakdown voltage of device will not reduce.
In addition, the raising of epi-layer surface doping concentration can also increase injection region other than using two layers of epitaxial layer
4 Implantation Energy.As shown in figure 9, using the double-deck injection of different Implantation Energies to form N-type compared with the structure described in Fig. 7
Injection region 4a and 4b.One is the typical conditions for reducing JFET effect, as the dosage of 60~200keV of Implantation Energy, injection are
The 4a on upper layer is formed between 1E12~3E12cm-2, another is to form 4b using higher Implantation Energy.Such as injection
Energy be 600~2000keV, the dosage of injection forms 4b between 1E12~3E12cm-2.Its purpose is silicon wafer table
Face forms one section of super junction because using 11 (12), and is that the doping concentration of drift region can be improved the characteristics of super junction.
Therefore it is injected using high-energy to improve the doping concentration of surface drift region, the performance of Lai Tigao device.
The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of VDMOS device, with the epitaxial layer of the first conduction type in the semiconductor substrate of the first conduction type, in institute
In the epitaxial layer stated, includes the channel region with the second conduction type of the VDMOS device, include in the channel region
There is the source region with the first conduction type of VDMOS device；
Between the channel region, also with the injection region of the first conduction type, the injection region and channel region lateral connection；
In the epi-layer surface of first conduction type, also there is the grid of gate oxide and the VDMOS device；Described
Also there is oxide layer, the oxide layer is integrally covered on semiconductor substrate surface, grid is wrapped up above grid；
Contact hole passes through the source region of oxide layer and lower section, and bottom is located in channel region, source region is drawn；
It is characterized by: in the channel region, also with the injection region of the second conduction type, the note of second conduction type
It is downward from area surface to enter area, bottom is more than that channel region is located in epitaxial layer；
The injection region of second conduction type is no more than source region in transverse direction.
2. VDMOS device as described in claim 1, it is characterised in that: the injection region of second conduction type, injection
Junction depth is not less than 2 times of channel region.
3. VDMOS device as described in claim 1, it is characterised in that: the oxidation layer surface also has source metal, institute
Source metal and contact holes contact are stated, the source electrode of VDMOS device is formed.
4. VDMOS device as described in claim 1, it is characterised in that: the grid is the polysilicon gate of heavy doping,
Doping type is consistent with the type of VDMOS device, i.e. the extremely N-type heavy doping of its polysilicon gate of N-type VDMOS, it is more by p-type VDMOS
Polysilicon gate is p-type heavy doping.
5. a kind of VDMOS device, with the epitaxial layer of the first conduction type in the semiconductor substrate of the first conduction type, in institute
In the epitaxial layer stated, includes the channel region with the second conduction type of the VDMOS device, include in the channel region
There is the source region with the first conduction type of VDMOS device；
Between the channel region, also with the injection region of the first conduction type, the injection region and channel region lateral connection；
In the epi-layer surface of first conduction type, also there is the grid of gate oxide and the VDMOS device；Described
Also there is oxide layer, the oxide layer is integrally covered on semiconductor substrate surface, grid is wrapped up above grid；
Contact hole passes through the source region of oxide layer and lower section, and bottom is located in channel region, source region is drawn；
It is characterized by: in the channel region, also with the injection region of the second conduction type, the note of second conduction type
It is downward from area surface to enter area, bottom is more than that channel region is located in epitaxial layer；
The injection region of second conduction type is no more than source region in transverse direction；
The epitaxial layer of first conduction type is divided into the different bilevel epitaxial layer of doping concentration, at the middle and upper levels
The doping concentration of epitaxial layer is greater than the epitaxial layer of lower layer；And the injection region depth of second conduction type is more than the outer of upper layer
Prolong layer, bottom is located in lower layer's epitaxial layer.
6. VDMOS device as claimed in claim 5, it is characterised in that: the injection region of second conduction type, injection
Junction depth is not less than 2 times of channel region.
7. VDMOS device as claimed in claim 5, it is characterised in that: the oxidation layer surface also has source metal, institute
Source metal and contact holes contact are stated, the source electrode of VDMOS device is formed.
8. a kind of VDMOS device, with the epitaxial layer of the first conduction type in the semiconductor substrate of the first conduction type, in institute
In the epitaxial layer stated, includes the channel region with the second conduction type of the VDMOS device, include in the channel region
There is the source region with the first conduction type of VDMOS device；
In the epi-layer surface of first conduction type, also there is the grid of gate oxide and the VDMOS device；Described
Also there is oxide layer, the oxide layer is integrally covered on semiconductor substrate surface, grid is wrapped up above grid；
Contact hole passes through the source region of oxide layer and lower section, and bottom is located in channel region, source region is drawn；
It is characterized by: in the channel region, also with the injection region of the second conduction type, the note of second conduction type
It is downward from area surface to enter area, bottom is more than that channel region is located in epitaxial layer；
The injection region of second conduction type is no more than source region in transverse direction；
Between the channel region, also with the injection region of the first conduction type, the injection region and channel region lateral connection；Institute
The injection region for the first conduction type stated, is divided into upper layer and lower layer, is formed by different Implantation Energies.
9. VDMOS device as claimed in claim 8, it is characterised in that: the injection region of first conduction type, wherein on
The Implantation Energy of layer injection region is 60~200keV, and implantation dosage is 1E12~3E12cm-2, upper layer injection region can imitate its JFET
It answers；The Implantation Energy of lower layer injection region is 600~2000keV, and implantation dosage is 1E12~3E12cm-2, improve surface drift region
Doping concentration.
10. VDMOS device as claimed in claim 8, it is characterised in that: the injection region of second conduction type, note
Enter 2 times that junction depth is not less than channel region.
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| CN201910261385.XA CN110047930A (en) | 2019-04-02 | 2019-04-02 | VDMOS device |
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| CN201910261385.XA CN110047930A (en) | 2019-04-02 | 2019-04-02 | VDMOS device |
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| CN111969049A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | SOI transverse insulated gate bipolar transistor |
| WO2021169381A1 (en) * | 2020-02-25 | 2021-09-02 | 南京华瑞微集成电路有限公司 | Dmos having optimized electric characteristics |
| CN117059673A (en) * | 2023-10-11 | 2023-11-14 | 珠海格力电子元器件有限公司 | Semiconductor structure, manufacturing method of semiconductor structure and semiconductor device |
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| US20160104792A1 (en) * | 2013-09-20 | 2016-04-14 | Monolith Semiconductor Inc. | High voltage mosfet devices and methods of making the devices |
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| WO2021169381A1 (en) * | 2020-02-25 | 2021-09-02 | 南京华瑞微集成电路有限公司 | Dmos having optimized electric characteristics |
| CN111969049A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | SOI transverse insulated gate bipolar transistor |
| CN117059673A (en) * | 2023-10-11 | 2023-11-14 | 珠海格力电子元器件有限公司 | Semiconductor structure, manufacturing method of semiconductor structure and semiconductor device |
| CN117059673B (en) * | 2023-10-11 | 2024-02-27 | 珠海格力电子元器件有限公司 | Semiconductor structure, manufacturing method of semiconductor structure and semiconductor device |
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