CN117276306A - 薄膜晶体管及其制备方法、存储器和显示器 - Google Patents

薄膜晶体管及其制备方法、存储器和显示器 Download PDF

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CN117276306A
CN117276306A CN202210656607.XA CN202210656607A CN117276306A CN 117276306 A CN117276306 A CN 117276306A CN 202210656607 A CN202210656607 A CN 202210656607A CN 117276306 A CN117276306 A CN 117276306A
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layer
metal layer
metal
source
thin film
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刘明
李泠
耿玓
段新绿
陆丛研
卢年端
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Institute of Microelectronics of CAS
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Priority to PCT/CN2022/116072 priority patent/WO2023236375A1/zh
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Abstract

本发明公开了一种薄膜晶体管及其制备方法、存储器和显示器，其中的薄膜晶体管包括依次层叠设置的第二源漏层、绝缘层和第一源漏层；栅极和环绕所述栅极的沟道层，位于所述第一源漏层和所述绝缘层内；所述沟道层与所述第一源漏层和所述第二源漏层接触；所述第一源漏层包括第一金属层和第二金属层，所述第一金属层靠近所述绝缘层，所述第二金属层远离所述绝缘层；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×106S/m，且抗氧化性能不低于钼的金属。所述CAA架构的薄膜晶体管能够缩小晶体管尺寸、降低晶体管的功耗并提高晶体管的接触性能和导电性能。

Description

薄膜晶体管及其制备方法、存储器和显示器
技术领域
本申请涉及半导体技术领域，尤其涉及一种薄膜晶体管及其制备方法、存储器和显示器。
背景技术
根据摩尔定律，集成电路不断向更细微尺寸发展，而先进制程则是集成电路制造中最为顶尖的节点之一。目前，先进制程已发展至5/7nm节点，这对晶体管的进一步微型化提出了极高的要求。
目前晶体管的一个关键架构：鳍式场效应晶体管(Fin Field EffectTransistor，简称FinFET)的设计可以大幅改善电路控制并减少漏电流(leakage)，同时大幅缩短晶体管的栅长。但是FinFET架构主要适用于10～22nm的制程，对于10nm以下，如7nm，5nm，3nm的制程，则会受到FinFET宽度缩放的限制，无法在继续缩小尺寸的同时保证高性能和低功耗。另一方面，目前FinFET的源漏极还存在接触性能较差，导电性能较差的问题。
因此，如何进一步缩小晶体管尺寸、降低晶体管的功耗、提高晶体管的接触性能和导电性能，满足先进制程：高性能、低功耗的要求，成为目前亟需解决的问题。
发明内容
本发明提供了一种薄膜晶体管及其制备方法、存储器和显示器，以解决或者部分解决如何进一步缩小晶体管尺寸、降低晶体管的功耗、提高晶体管的接触性能和导电性能的技术问题。
为解决上述技术问题，根据本发明实施例提供了一种薄膜晶体管，包括：
依次层叠设置的第二源漏层、绝缘层和第一源漏层；
栅极和环绕所述栅极的沟道层，位于所述第一源漏层和所述绝缘层内；所述沟道层与所述第一源漏层和所述第二源漏层接触；
其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层靠近所述绝缘层，所述第二金属层远离所述绝缘层；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×106S/m，且抗氧化性能不低于钼的金属。
可选的，所述第一金属层与所述第二金属层的厚度之比不低于10，所述第一金属层和所述第二金属层的总厚度不低于50nm。
进一步的，所述第一金属层的材质为钛或钨，所述第二金属层的材质为银或金。
可选的，所述第一金属层与所述第二金属层的厚度之比为0.9～1.1，所述第一金属层和所述第二金属层的总厚度不低于50nm。
进一步的，所述第一金属层的材质为钛或钨，所述第二金属层的材质为钼或氮化钛。
可选的，所述第一源漏层还包括第三金属层，所述第三金属层位于所述第一金属层和所述绝缘层之间；所述第三金属层的材质为抗氧化性能不低于钼的金属。
可选的，所述第二源漏层包括第四金属层、第五金属层和第六金属层；所述第四金属层靠近所述绝缘层，所述第五金属层远离所述绝缘层；所述第六金属层位于所述第四金属层和所述绝缘层之间。
进一步的，所述栅极的底部位于所述第四金属层内，所述第四金属层的材质为功函数低于钼的金属。
基于相同的发明构思，根据本发明实施例提供了一种薄膜晶体管的制备方法，包括：
提供衬底；
在所述衬底上依次形成第二源漏层、绝缘层和第一源漏层；其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层形成在所述绝缘层上，所述第二金属层形成在所述第一金属层上；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×106S/m，且抗氧化性能不低于钼的金属；
在所述第一源漏层和所述绝缘层内形成延伸至所述第二源漏层的孔；
在所述孔的内壁和所述第一源漏层的表面沉积沟道材料，形成沟道层；
在所述沟道层上沉积栅极材料，形成栅极。
基于相同的发明构思，根据本发明实施例提供了一种存储器，所述存储器包括多个存储阵列，所述存储阵列包括前述技术方案中的任一项薄膜晶体管。
基于相同的发明构思，根据本发明实施例提供了一种显示器，所述显示器包括像素电路，所述像素电路包括前述技术方案中的任一项薄膜晶体管。
通过本发明的一个或者多个技术方案，本发明具有以下有益效果或者优点：
本发明提供了一种薄膜晶体管，其栅极下穿第一源漏层和绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极设置的Channel All Around，简称CAA架构的晶体管。本发明的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能力，提高了电流传导效率；且相对于GAA(GateAll Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，对薄膜晶体管的第一源漏层采用分层结构，其中靠近绝缘层的第一金属层采用功函数较低的金属，以提高接触性能；由于功函数较低的金属通常抗氧化能力较弱，因此远离绝缘层的第二金属层采用导电能力更佳，抗氧化性能更好的金属，在保护第一金属层不被氧化，不降低接触性能的同时，减小源漏极金属引线的电阻，从而提高晶体管的导电性能。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。
在附图中：
图1示出了根据本发明一个实施例的薄膜晶体管的结构示意图；
图2示出了根据本发明一个实施例的包括第三金属层的薄膜晶体管的结构示意图；
图3示出了根据本发明一个实施例的薄膜晶体管的制备方法流程示意图；
图4示出了根据本发明一个实施例的存储阵列示意图；
附图标记说明：
1、第一源漏层；11、第一金属层；12、第二金属层；13、第三金属层；2、第二源漏层；21、第四金属层；22、第五金属层；23、第六金属层；3、绝缘层；4、沟道层；5、栅极；6、栅介质层；71、第一薄膜晶体管；72、第二薄膜晶体管。
具体实施方式
为了使本申请所属技术领域中的技术人员更清楚地理解本申请，下面结合附图，通过具体实施例对本申请技术方案作详细描述。在整个说明书中，除非另有特别说明，本文使用的术语应理解为如本领域中通常所使用的含义。因此，除非另有定义，本文使用的所有技术和科学术语具有与本发明所属领域技术人员的一般理解相同的含义。若存在矛盾，本说明书优先。除非另有特别说明，本发明中用到的各种设备等，均可通过市场购买得到或者可通过现有方法制备得到。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
此外，术语“水平”、“竖直”、“悬垂”等术语并不表示要求部件绝对水平或悬垂，而是可以稍微倾斜。如“水平”仅仅是指其方向相对“竖直”而言更加水平，并不是表示该结构一定要完全水平，而是可以稍微倾斜。
研究表明，晶体管的源漏极存在接触性能较差，导电性能较差的原因为：源漏极金属为了保证耐用性，采用的抗氧化性能较好，但功函数较高的金属，如钼(Mo)和氮化钛(TiN)，但功函数高则存在接触性能和导电性能变差的问题。而功函数较低的金属，如钛(Ti)，钨(W)能够提高接触性能和导电性能，但又容易被氧化，氧化之后接触性能仍然会变差，同时金属电阻增大。
为了解决上述问题，在一个可选的实施例中，提出了一种薄膜晶体管TFT(ThinFilm Transistor)，其结构参阅图1，包括：
依次层叠设置的第二源漏层2、绝缘层3和第一源漏层1；
栅极5和环绕栅极5的沟道层4，位于第一源漏层1和绝缘层3内；沟道层4与第一源漏层1和第二源漏层2接触。
具体的，本实施例提供的TFT晶体管为垂直沟道结构，为了方便理解，可以将第一源漏层1视为TFT的上层源漏极，将第二源漏层2视为TFT的下层源漏极。在实际使用时，第一源漏层1可以制备成源极，第二源漏层2可以制备为漏极，也可以将第一源漏层1制备成漏极，第二源漏层2制备为源极，对此不进行具体限定。
栅极5为垂直结构，栅极5的底部至少穿透第一源漏层1并进入绝缘层3。栅极5的底部还可以穿透绝缘层3进入第二源漏层2。栅极5的形状可以是柱形的，其横截面形状可以是圆形，椭圆形或多边形；栅极5的形状还可以是环形的，其横截面形状可以是圆环，椭圆环或多边形环，可根据实际需求确定。栅极5的可选材质有：氧化铟锡(ITO，Indium Tin Oxide)，氧化铟锌I(ZO，Indium Zinc Oxide)或氮化钛(TiN)。
沟道层4为垂直沟道结构，环绕第一源漏层1和绝缘层3内的栅极5部分形成。因此，本实施例的TFT晶体管属于垂直沟道全环绕栅极的CAA(Channel All Around)架构。沟道层4的横截面形状可以是圆形，椭圆形或多边形的，沟道层4的横截面形状可以与栅极5的横截面形状相同或不同。
一个较佳的沟道层形状是在沟道层4的横截面面积不变的前提下，选择横截面周长最大的形状，如此能够提高沟道层4的沟道宽度，从而进一步提高沟道宽长比，有利于提高薄膜晶体管的饱和电流。
沟道层4的材质可以是氧化铟镓锌IGZO(Indium Gallium Zinc Oxide)。
可选的，薄膜晶体管还包括栅介质层6，栅介质层6位于栅极5层和沟道层4之间。栅介质层6的可选材质包括：氧化铪、铪铝氧化物和三氧化二铝中的至少一种。
本实施例的CAA架构的晶体管相比于FinFET架构的晶体管，具有如下的特点：
1)垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层3的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；
2)通过环形沟道环绕栅极5的CAA架构，能够极大的增加栅极5和沟道层4之间的接触面积，从而显著增强栅极5对沟道层4的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极5全向场效应晶体管)架构，CAA架构也具有更大的栅极5与沟道层4之间的接触面积。
同时，为了解决目前晶体管的源漏极存在接触性能较差，导电性能较差的问题，本实施例提供的TFT晶体管，其对第一源漏层1采用了分层结构，具体如下：
第一源漏层1包括第一金属层11和第二金属层12，第一金属层11靠近绝缘层3，第二金属层12远离绝缘层3；第一金属层11的材质为功函数低于钼的金属；第二金属层12的材质为导电率高于3×106S/m(西门子/米)，且抗氧化性能不低于钼的金属。
相比于FinFET架构的晶体管，本实施例的CAA晶体管，通过采用不同的金属，分层形成源漏极后，还具有如下的特点：
3)靠近绝缘层3的第一金属层11采用功函数较低的金属，能够获得更好的接触性能；由于功函数较低的金属通常抗氧化能力较弱，因此远离绝缘层3、靠近顶部沟道区的第二金属层12采用导电能力更佳，抗氧化性能更好的金属，在保护第一金属层11不被氧化，不降低接触性能的同时，减小源漏极金属引线的电阻，提高晶体管的导电性能。
在分层形成第一源漏层1时，第一金属层11和第二金属层12的可选材质和厚度配比可采用如下两种方案：
方案一、第一金属层11与第二金属层12的厚度之比不低于10，第一金属层11和第二金属层12的总厚度不低于50nm。
与方案一对应的，第一金属层11的可选材质为钛(Ti)或钨(W)，第二金属层12的可选材质为银(Ag)或金(Au)。
具体的，靠近绝缘层3的第一金属层11选择功函数较低、导电率较高的金属，如Ti和W，从而获得良好的接触性能和高电导能力，为了保证接触性能和导电性能，第一金属层11越厚越好。
第二金属层12形成在第一金属层11的上表面，选择抗氧化性较强的金属，如Ag和Au，以防止抗氧化能力弱的第一金属层11被氧化。由于只起到防氧化的作用，因此第二金属层12较薄。
通过方案一中的第一金属层11和第二金属层12之间的材质和厚度配置，能够使晶体管同时具备更佳的接触性能、导电性能和抗氧化性能。
方案二、第一金属层11与第二金属层12的厚度之比为0.9～1.1，第一金属层11和第二金属层12的总厚度不低于50nm。
与之对应的，第一金属层11的材质为钛(Ti)或钨(W)，第二金属层12的材质为钼(Mo)或氮化钛(TiN)。
具体的，第一金属层11选择功函数低于Mo的金属，如Ti、W等金属，从而保证第一源漏层1与半导体，即沟道层4之间具有更佳的接触性能，可采用较厚的厚度；而第二金属层12需要同时具备较低的功函数、较高的电导和较好的抗氧化性的特点，如采用TiN、Mo等，越厚越好。因此在方案二中第一金属层11和第二金属层12两者的厚度相当，如此可以同时获得高电导率和低接触电阻的特性。
在一些可选的实施例中，如图2所示，第一源漏层1还包括第三金属层13，第三金属层13位于第一金属层11和绝缘层3之间；第三金属层13的材质为抗氧化性能不低于钼的金属。
至此，第一金属层11、第二金属层12和第三金属层13形成了一种三层夹心结构的第一源漏层1。其中，第二金属层12为顶层，可选择Mo、TiN、Au、Ag等金属，避免第一源漏层1的顶部被氧化所导致的接触性能变差和金属走线电阻升高；第一金属层11作为中间层或夹心层，可选择功函数较低的金属，如Ti或W，从而进一步提高沟道层4与第一源漏层1之间的接触性能；第三金属层13靠近绝缘层3为底层，可选择Mo、TiN、Au、Ag等金属，是为了保护第一源漏层1的底部不被氧化，避免接触性能变差和金属走线电阻升高。
与第一源漏层1的分层形成同理，第二源漏层2也可以采用相同的分层配置。在一些可选的实施例中，如图2所示，第二源漏层2包括第四金属层21、第五金属层22和第六金属层23；第四金属层21靠近绝缘层3，第五金属层22远离绝缘层3；第六金属层23位于第四金属层21和绝缘层3之间。
具体的，第五金属层22为第二源漏层2的底层，可选择Mo、TiN、Au、Ag等金属，避免第二源漏层2的底部被氧化所导致的接触性能变差和金属走线电阻升高；第四金属层21为第二源漏层2的中间层或夹心层，可选择功函数较低的金属，如Ti或W，从而进一步提高沟道层4与第二源漏层2之间的接触性能；第六金属层23靠近绝缘层3为第二源漏层2的顶层，可选择Mo、TiN、Au、Ag等金属，是为了保护第二源漏层2的顶部不被氧化，避免接触性能变差和金属走线电阻升高。
进一步的，如图2所示，栅极5的底部位于第四金属层21内，第四金属层21的材质为功函数低于钼的金属。通过使用功函数低的第四金属层21包裹栅极5和沟道层4的底部，能够进一步提高接触性能。
基于前述实施例相同的发明构思，在又一个可选的实施例中，如图3所示，提供了一种薄膜晶体管的制备方法，包括：
S301：提供衬底；可使用硅衬底；
S302：在衬底上依次形成第二源漏层2、绝缘层3和第一源漏层1；其中，第一源漏层1包括第一金属层11和第二金属层12，第一金属层11形成在绝缘层3上，第二金属层12形成在第一金属层11上；第一金属层11的材质为功函数低于钼的金属；第二金属层12的材质为导电率高于3×106S/m，且抗氧化性能不低于钼的金属；
具体的，可先在衬底上沉积预氧化层，厚度为300～400nm，沉积完成后进行预清洗，然后在预氧化层上沉积形成第二源漏层2的金属材料层，具体如下：
对预氧化层进行预清洗；在预清洗后的预氧化层上沉积源漏金属材料；采用分层沉积的方式：第一层先沉积第五金属层22的材料，如Mo、TiN、Au、Ag等金属；第二层再沉积第四金属层21的材料，如Ti或W；第三层再沉积第六金属层23的材料，如Mo、TiN、Au、Ag等金属。
接着在源漏金属材料层上进行双保护层沉积，可以是SiN和SiO形成的双层保护层，双层保护层的厚度约为200nm；接下来再进行源漏金属材料层的光刻，具体是在双层保护层上覆盖光刻胶后依次进行曝光、显影、刻蚀形成第二源漏层2；
接着，在第二源漏层2上进行填平氧化层沉积，然后再进行化学机械抛光、清洗，完成后沉积绝缘层材料形成绝缘层3；
接着，在绝缘层3上沉积第一源漏层金属，同样采用分层沉积的方式：第一层先沉积第三金属层13的材料，如Mo、TiN、Au、Ag等金属；第二层再沉积第一金属层11的材料，如Ti或W；第三层再沉积第二金属层12的材料，如Mo、TiN、Au、Ag等金属；然后依次进行双保护层沉积、覆盖光刻胶、曝光、显影、刻蚀、清洗形成第一源漏层1。
S303：在第一源漏层1和绝缘层3内形成延伸至第二源漏层2的孔；可采用深刻刻蚀方法形成所需的孔，具体如下：
在第一源漏层1上再次进行填平氧化物沉积，然后进行化学机械抛光、清洗，抛光位置停留在填平氧化层上；
形成通孔：在要形成通孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，并进行曝光、显影、刻蚀、清洗和化学机械抛光，分别形成底部到达第一源漏层1、底部到达第二源漏层2的通孔；
形成沟道孔：在要形成沟道孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，对准第一源漏层1后进行曝光、显影、刻蚀并清洗，形成穿透第一源漏层1和绝缘层3，且底部到达第二源漏层2的沟道孔。
S304：在孔的内壁和第一源漏层1的表面沉积沟道材料，形成沟道层4；
S305：在沟道层4上沉积栅极材料，形成栅极5。
可选的，在沉积沟道材料后，先沉积栅介质材料以形成栅介质层6，然后在栅介质层7的表面沉积栅极材料。
在沟道孔内沉积沟道材料、栅极材料和栅介质材料的方法均可以是原子层沉积。
基于前述实施例相同的发明构思，在又一个可选的实施例中，提供了一种存储器，存储器包括多个存储阵列，存储阵列包括前述实施例中的任一项的薄膜晶体管。
图4示出了一种可选的2T0C的存储阵列结构，一个存储阵列中包括两个本发明实施例提供的：第一薄膜晶体管71和第二薄膜晶体管72，其中，第一薄膜晶体管71的栅极电连接写字线WWL，源极电连接写位线WBL，漏极电连接第二薄膜晶体管72的栅极，第二薄膜晶体管72的源极电连接读字线RWL，漏极电连接读位线RBL。
将本发明实施例提供的薄膜晶体管应用于2T0C的存储电路，可以将一个TFT晶体管的栅极与另一个TFT晶体管的源漏极直接连接，无需要外接引线，因此可以极大的缩小整个存储器的体积，有利于进一步实现存储器的小型化。
另外，本发明实施例提供的薄膜晶体管还可以应用到1T0C，1T1C，2T1C的存储阵列，在此不进行具体限定。
基于前述实施例相同的发明构思，在又一个可选的实施例中，提供了一种显示器，显示器包括像素电路，像素电路包括前述实施例中任一项的薄膜晶体管。
通过本发明的一个或者多个实施例，本发明具有以下有益效果或者优点：
本发明提供了一种薄膜晶体管、存储器及显示器；其中薄膜晶体管的栅极下穿第一源漏层和绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极设置的Channel AllAround，简称CAA架构的晶体管。本发明的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，对薄膜晶体管的第一源漏层采用分层结构，其中靠近绝缘层的第一金属层采用功函数较低的金属，以提高接触性能；由于功函数较低的金属通常抗氧化能力较弱，因此远离绝缘层的第二金属层采用导电能力更佳，抗氧化性能更好的金属，在保护第一金属层不被氧化，不降低接触性能的同时，减小源漏极金属引线的电阻，从而提高晶体管的导电性能。
尽管已描述了本申请的优选实施例，但本领域内的普通技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

1.一种薄膜晶体管，其特征在于，所述薄膜晶体管包括：
依次层叠设置的第二源漏层、绝缘层和第一源漏层；
栅极和环绕所述栅极的沟道层，位于所述第一源漏层和所述绝缘层内；所述沟道层与所述第一源漏层和所述第二源漏层接触；
其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层靠近所述绝缘层，所述第二金属层远离所述绝缘层；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×106S/m，且抗氧化性能不低于钼的金属。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述第一金属层与所述第二金属层的厚度之比不低于10，所述第一金属层和所述第二金属层的总厚度不低于50nm。
3.如权利要求2所述的薄膜晶体管，其特征在于，所述第一金属层的材质为钛或钨，所述第二金属层的材质为银或金。
4.如权利要求1所述的薄膜晶体管，其特征在于，所述第一金属层与所述第二金属层的厚度之比为0.9～1.1，所述第一金属层和所述第二金属层的总厚度不低于50nm。
5.如权利要求4所述的薄膜晶体管，其特征在于，所述第一金属层的材质为钛或钨，所述第二金属层的材质为钼或氮化钛。
6.如权利要求1所述的薄膜晶体管，其特征在于，所述第一源漏层还包括第三金属层，所述第三金属层位于所述第一金属层和所述绝缘层之间；所述第三金属层的材质为抗氧化性能不低于钼的金属。
7.如权利要求1所述的薄膜晶体管，其特征在于，所述第二源漏层包括第四金属层、第五金属层和第六金属层；所述第四金属层靠近所述绝缘层，所述第五金属层远离所述绝缘层；所述第六金属层位于所述第四金属层和所述绝缘层之间。
8.一种薄膜晶体管的制备方法，其特征在于，包括：
提供衬底；
在所述衬底上依次形成第二源漏层、绝缘层和第一源漏层；其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层形成在所述绝缘层上，所述第二金属层形成在所述第一金属层上；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×106S/m，且抗氧化性能不低于钼的金属；
在所述第一源漏层和所述绝缘层内形成延伸至所述第二源漏层的孔；
在所述孔的内壁和所述第一源漏层的表面沉积沟道材料，形成沟道层；
在所述沟道层上沉积栅极材料，形成栅极。
9.一种存储器，其特征在于，所述存储器包括多个存储阵列，所述存储阵列包括如权利要求1～7中任一项所述的薄膜晶体管。
10.一种显示器，其特征在于，所述显示器包括像素电路，所述像素电路包括如权利要求1～7中任一项所述的薄膜晶体管。
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