CN117276308A - 薄膜晶体管及其制备方法、存储器和显示器 - Google Patents

薄膜晶体管及其制备方法、存储器和显示器 Download PDF

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CN117276308A
CN117276308A CN202210657516.8A CN202210657516A CN117276308A CN 117276308 A CN117276308 A CN 117276308A CN 202210657516 A CN202210657516 A CN 202210657516A CN 117276308 A CN117276308 A CN 117276308A
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layer
insulating layer
channel
source
gate
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耿玓
李泠
刘明
段新绿
陆丛研
卢年端
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种薄膜晶体管及其制备方法、存储器和显示器；其中的薄膜晶体管包括：依次层叠设置的第一源漏层，第一绝缘层，第二源漏层和第二绝缘层；栅极和环绕所述栅极的沟道层，位于所述第二绝缘层、所述第二源漏层和所述第一绝缘层内；所述沟道层与所述第一源漏层、所述第一绝缘层、所述第二源漏层和所述第二绝缘层接触。本发明提供的薄膜晶体管为环形沟道环绕栅极的CAA架构，并通过在第二源漏层的上方增加第二绝缘层，能够减小栅极泄露电流和薄膜晶体管的寄生电容。

Description

薄膜晶体管及其制备方法、存储器和显示器
技术领域
本申请涉及半导体技术领域，尤其涉及一种薄膜晶体管及其制备方法、存储器和显示器。
背景技术
根据摩尔定律，集成电路不断向更细微尺寸发展，而先进制程则是集成电路制造中最为顶尖的节点之一。目前，先进制程已发展至5/7nm节点，这对晶体管的进一步微型化提出了极高的要求。
目前晶体管的一个关键架构：鳍式场效应晶体管(Fin Field EffectTransistor，简称FinFET)的设计可以大幅改善电路控制并减少漏电流(leakage)，同时大幅缩短晶体管的栅长。然而，FinFET架构适用于10～22nm的制程，对于10nm以下，如7nm，5nm，3nm的制程，则会受到FinFET宽度缩放的限制，无法在继续缩小尺寸的同时保证高性能和低功耗。另一方面，制程的进一步提高使FinFET的栅极出现较大的泄露电流，导致性能降低的同时产生了更多的功耗。
因此，如何进一步缩小晶体管的尺寸、提高晶体管的性能、降低功耗并减少栅极的泄露电流，成为目前亟需解决的问题。
发明内容
本发明提供了一种薄膜晶体管及其制备方法、存储器和显示器，以解决或者部分解决如何进一步缩小晶体管的尺寸、提高晶体管的性能、降低功耗并减少栅极的泄露电流的技术问题。
为解决上述技术问题，根据本发明实施例提供了一种薄膜晶体管，包括：
依次层叠设置的第一源漏层，第一绝缘层，第二源漏层和第二绝缘层；
栅极和环绕所述栅极的沟道层，位于所述第二绝缘层、所述第二源漏层和所述第一绝缘层内；所述沟道层与所述第一源漏层、所述第一绝缘层、所述第二源漏层和所述第二绝缘层接触。
可选的，所述栅极包括栅极竖直部和栅极水平部，所述沟道层包括沟道竖直部和沟道水平部；
所述沟道竖直部环绕所述栅极竖直部；所述沟道竖直部与所述第一源漏层，所述第一绝缘层，所述第二源漏层和所述第二绝缘层接触；
所述沟道水平部位于所述栅极水平部与所述第二绝缘层的上表面之间。
可选的，所述栅极和所述沟道层的顶部与所述第二绝缘层齐平。
可选的，所述第二绝缘层的厚度为10～30纳米。
可选的，所述第二绝缘层的材质为二氧化硅。
可选的，所述薄膜晶体管还包括栅介质层，所述栅介质层位于所述栅极和所述沟道层之间。
基于相同的发明构思，根据本发明实施例提供了一种薄膜晶体管的制备方法，包括：
提供衬底；
在所述衬底上依次形成第一源漏层、第一绝缘层，第二源漏层和第二绝缘层；
在所述第二绝缘层、所述第二源漏层、所述第一绝缘层内形成延伸至所述第一源漏层的孔；
在所述孔的内壁和所述第二绝缘层的表面沉积沟道材料，形成沟道层；
在所述沟道层上沉积栅极材料，形成栅极。
可选的，在所述形成栅极之后，所述制备方法还包括：
去除位于第二绝缘层上表面的沟道层和栅极。
基于相同的发明构思，根据本发明实施例提供了一种存储器，所述存储器包括多个存储阵列，所述存储阵列包括前述技术方案中任一项薄膜晶体管。
基于相同的发明构思，根据本发明实施例提供了一种显示器，所述显示器包括像素电路，所述像素电路包括如前述技术方案中的任一项薄膜晶体管。
通过本发明的一个或者多个技术方案，本发明具有以下有益效果或者优点：
本发明提供了一种薄膜晶体管，其栅极下穿第二源漏层和第一绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极的Channel All Around，简称CAA架构的晶体管。本发明的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由第一绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，在上层源漏，即第二源漏层的上方再增加第二绝缘层，一方面能够有效减小因为栅极与第二源漏层在水平方向上的交叠所产生的栅极泄露电流，另一方面第二绝缘层有利于使第二源漏层与后续工艺的金属层隔离，从而减小晶体管的寄生电容。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。
在附图中：
图1示出了根据本发明一个实施例的薄膜晶体管的结构示意图；
图2示出了根据本发明一个实施例的栅极竖直部、栅极水平部、沟道竖直部、沟道水平部的示意图；
图3示出了根据本发明一个实施例的去掉栅极水平部、沟道水平部后的薄膜晶体管的结构示意图；
图4示出了根据本发明一个实施例的薄膜晶体管的制备方法流程示意图；
图5示出了根据本发明一个实施例的存储阵列示意图；
附图标记说明：
1、第一源漏层；2、第一绝缘层；3、第二源漏层；4、第二绝缘层；5、沟道层；51、沟道竖直部；52、沟道水平部；6、栅极；61、栅极竖直部；62、栅极水平部；7、栅介质层；81、第一薄膜晶体管；82、第二薄膜晶体管。
具体实施方式
为了使本申请所属技术领域中的技术人员更清楚地理解本申请，下面结合附图，通过具体实施例对本申请技术方案作详细描述。在整个说明书中，除非另有特别说明，本文使用的术语应理解为如本领域中通常所使用的含义。因此，除非另有定义，本文使用的所有技术和科学术语具有与本发明所属领域技术人员的一般理解相同的含义。若存在矛盾，本说明书优先。除非另有特别说明，本发明中用到的各种设备等，均可通过市场购买得到或者可通过现有方法制备得到。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
此外，术语“水平”、“竖直”、“悬垂”等术语并不表示要求部件绝对水平或悬垂，而是可以稍微倾斜。如“水平”仅仅是指其方向相对“竖直”而言更加水平，并不是表示该结构一定要完全水平，而是可以稍微倾斜。
研究表明，目前晶体管的栅极出现较大的泄露电流的原因为：为了方便布线，垂直结构晶体管的栅极通常在上层源/漏极的上表面进行水平延伸，因此栅电极与上层源/漏电极。在水平方向上存在交叠区域。随着晶体管尺寸的进一步微缩，在该交叠区域将会使栅电极与上层源/漏极之间产生明显泄露电流。
为了解决上述问题，在一个可选的实施例中，提出了一种薄膜晶体管TFT(ThinFilm Transistor)，其结构参阅图1，包括：
依次层叠设置的第一源漏层1，第一绝缘层2，第二源漏层3和第二绝缘层4；
栅极6和环绕栅极6的沟道层5，位于第二绝缘层4、第二源漏层3和第一绝缘层2内；沟道层5与第一源漏层1、第一绝缘层2、第二源漏层3和第二绝缘层4接触。
具体的，本实施例提供的TFT晶体管为垂直沟道结构，为了方便理解，可以将第二源漏层3视为TFT的上层源漏极，将第一源漏层1视为TFT的下层源漏极。在实际使用时，可以将第二源漏层3制备成源极，第一源漏层1制备为漏极，也可以将第二源漏层3制备成漏极，第一源漏层1制备为源极，对此不进行具体限定。
第一绝缘层2位于第二源漏层3和第一源漏层1之间，起到绝缘作用。
栅极6为垂直栅极结构，栅极6的底部至少穿透第二源漏层3并进入第一绝缘层2。栅极6的底部还可以穿透第一绝缘层2进入第一源漏层1。栅极6的形状可以是柱形的，其横截面形状可以是圆形，椭圆形或多边形；栅极6的形状还可以是环形的，其横截面形状可以是圆环，椭圆环或多边形环，可根据实际需求确定。栅极6的可选材质有：氧化铟锡(ITO，Indium Tin Oxide)，氧化铟锌(IZO，Indium Zinc Oxide)或氮化钛(TiN)。
沟道层5为垂直沟道结构，环绕第二源漏层3和第一绝缘层2内的栅极6形成。因此，本实施例的TFT晶体管属于环形沟道全环绕栅极6的CAA(ChannelAll Around)架构。沟道层5的横截面形状可以是圆形，椭圆形或多边形的，沟道层5的横截面形状可以与栅极6的横截面形状相同或不同。
一个较佳的沟道层5形状是在沟道层5的横截面面积不变的前提下，选择横截面周长最大的形状，如此能够提高沟道层5的沟道宽度，从而进一步提高沟道宽长比，有利于提高薄膜晶体管的饱和电流。
沟道层5的材质可以是氧化铟镓锌IGZO(Indium Gallium Zinc Oxide)或其他金属氧化物沟道材料。
可选的，薄膜晶体管还包括栅介质层7，栅介质层7位于栅极6和沟道层5之间。栅介质层7的可选材质包括：氧化铪、铪铝氧化物和三氧化二铝中的至少一种。
为了解决目前晶体管容易在栅极6处产生较大的泄露电流的问题，本实施例在第二源漏层3的上表面形成第二绝缘层4，此处需结合两种不同的处理方式进行说明。
一种包括第二绝缘层4的TFT晶体管的结构如图2所示，栅极6包括栅极水平部62和栅极竖直部61，沟道层5包括沟道竖直部51和沟道水平部52；沟道竖直部51环绕栅极竖直部61；沟道竖直部51与第一源漏层1，第一绝缘层2，第二源漏层3和第二绝缘层4接触；沟道水平部52位于栅极水平部62与第二绝缘层4的上表面之间。
具体的，第二绝缘层4设置在第二源漏层3和栅极6的水平延伸部分之间，用于减小栅极水平部62与第二源漏层3在水平方向上的交叠部分的泄露电流。由于第二绝缘层4的存在还增加了栅极水平部62与第二源漏层3在水平方向形成的交叠区域的垂直距离，因此还可以减小栅极6与第二源漏层3之间的寄生电容。
另一种包括第二绝缘层4的TFT晶体管的结构如图3所示，与图1和图2的区别在于，栅极6和沟道层5的顶部与第二绝缘层4齐平。栅极6和沟道层5的顶部与第二绝缘层4齐平既可以是栅极6和沟道层5的顶部与第二绝缘层4的上表面对齐，也可以是栅极6和沟道层5的顶部与第二绝缘层4的上表面之间的高度差不超过设定值，在此不对其进行具体限定。
图3的TFT晶体管去掉了沟道水平部52和栅极水平部62，使栅极6和沟道层5的顶部与第二绝缘层4齐平，能够在使用该晶体管组成电路时，实现不同晶体管器件之间的栅极6的隔离。同时，去掉沟道水平部52和栅极水平部62也就避免了栅极6与第一源漏层1在水平方向上存在的交叠，故而减小了寄生电容以及栅极6泄露电流。
如图3所示的TFT晶体管可以直接制备获得，也可以先形成图1所示的晶体管，然后通过研磨抛光的方式对沟道水平部52和栅极水平部62进行刻蚀处理。
第二绝缘层4的材质可以选择绝缘性良好的材料，如二氧化硅，能够显著的减小栅极6泄露电流；为了保证绝缘效果，第二绝缘层4的可选厚度为10～30nm。
总的来说，本实施例提供的薄膜晶体管具有如下的特点：
1)垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；
2)通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极6和沟道层5之间的接触面积，从而显著增强栅极6对沟道层5的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极6与沟道层5之间的接触面积。
3)在第二源漏层3的上方增加第二绝缘层4，其一，能够有效减小因为栅极6与第二源漏层3在水平方向上的交叠所产生的栅极6泄露电流；其二，第二绝缘层4增加了栅极6与第二源漏层3在水平方向上的交叠区域的垂直距离，能够减小栅极6与第二源漏层3之间的寄生电容；其三，增加第二绝缘层4还有利于使第二源漏层3与后续工艺的金属层隔离，从而减小薄膜晶体管的寄生电容；
4)另一方面，在去掉第二源漏层3上方所有的栅极6和沟道层5后，也能避免栅极6与第一源漏层1在水平方向上存在的交叠，实现减小了寄生电容以及栅极6泄露电流的目的。
基于前述实施例相同的发明构思，在另一个可选的实施例中，提供了一种薄膜晶体管的制备方法，如图4所示，其步骤包括：
S401：提供衬底；可使用硅衬底；
S402：在衬底上依次形成第一源漏层1、第一绝缘层2，第二源漏层3和第二绝缘层4；
具体的，可先在衬底上沉积预氧化层，厚度为300～400nm，沉积完成后进行预清洗，然后在预氧化层上沉积形成第一源漏层1的金属材料层，具体如下：对预氧化层进行预清洗；在预清洗后的预氧化层上沉积源漏金属材料，然后在源漏金属材料层上进行双保护层沉积，可以是SiN和SiO形成的双层保护层，双层保护层的厚度约为200nm；接下来进行源漏金属材料层的光刻，具体是在双层保护层上覆盖光刻胶后依次进行曝光、显影、刻蚀形成第一源漏层1；
接着，在第一源漏层1上进行填平氧化层沉积，然后再进行化学机械抛光、清洗，完成后沉积绝缘层材料形成第一绝缘层2；
接着，在第一绝缘层2上重复第一源漏层1的步骤沉积第二源漏层金属，然后依次进行双保护层沉积、覆盖光刻胶、曝光、显影、刻蚀、清洗形成第二源漏层3；
接着，在第二源漏层3上进行填平氧化层沉积，然后再进行化学机械抛光、清洗，完成后沉积绝缘层材料形成第二绝缘层4。
S403：在第二绝缘层4、第二源漏层3、第一绝缘层2内形成延伸至第一源漏层1的孔；可采用深刻刻蚀方法形成所需的孔，具体如下：
形成通孔：在要形成通孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，并进行曝光、显影、刻蚀、清洗和化学机械抛光，分别形成底部到达第一源漏层1、底部到达第二源漏层3的通孔；
形成沟道孔：在要形成沟道孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，对准第二源漏层3后进行曝光、显影、刻蚀并清洗，形成穿透第二绝缘层4、第二源漏层3、第一绝缘层2，且底部到达第一源漏层1的沟道孔。
S404：在孔的内壁和第二绝缘层4的表面沉积沟道材料，形成沟道层5；
S405：在沟道层5上沉积栅极材料，形成栅极6。
具体的，成孔方法可以是深孔刻蚀，在沟道孔内沉积沟道材料、栅极材料的方法可以是原子层沉积。
可选的，在沉积沟道材料后，先沉积栅介质材料以形成栅介质层7，然后在栅介质层7的表面沉积栅极材料，沉积栅介质材料的方法可以是原子层沉积。
可选的，在形成栅极6之后，制备方法还包括：
去除位于第二绝缘层4上表面的沟道层5和栅极6。去除方法可以是研磨、抛光和刻蚀。
基于前述实施例相同的发明构思，在又一个可选的实施例中，提供了一种存储器，存储器包括多个存储阵列，存储阵列包括前述实施例中的任一项的薄膜晶体管。
图5示出了一种可选的2T0C的存储阵列结构，一个存储阵列中包括两个本发明实施例提供的：第一薄膜晶体管81和第二薄膜晶体管82，其中，第一薄膜晶体管81的栅极电连接写字线WWL，源极电连接写位线WBL，漏极电连接第二薄膜晶体管82的栅极，第二薄膜晶体管82的源极电连接读字线RWL，漏极电连接读位线RBL。
将本发明实施例提供的薄膜晶体管应用于2T0C的存储电路，可以将一个TFT晶体管的栅极与另一个TFT晶体管的源漏极直接连接，无需要外接引线，因此可以极大的缩小整个存储器的体积，有利于进一步实现存储器的小型化。
另外，本发明实施例提供的薄膜晶体管还可以应用到1T0C，1T1C，2T1C的存储阵列，在此不进行具体限定。
基于前述实施例相同的发明构思，在又一个可选的实施例中，提供了一种显示器，显示器包括像素电路，像素电路包括前述实施例中任一项的薄膜晶体管。
通过本发明的一个或者多个实施例，本发明具有以下有益效果或者优点：
本发明提供了一种薄膜晶体管及其制备方法、存储器和显示器，其中的薄膜晶体管的栅极下穿第二源漏层和第一绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极的Channel All Around，简称CAA架构的晶体管。本发明的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由第一绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，在上层源漏，即第二源漏层的上方再增加第二绝缘层，一方面能够有效减小因为栅极与第二源漏层在水平方向上的交叠所产生的栅极泄露电流，另一方面第二绝缘层有利于使第二源漏层与后续工艺的金属层隔离，从而减小晶体管的寄生电容。
尽管已描述了本申请的优选实施例，但本领域内的普通技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

1.一种薄膜晶体管，其特征在于，所述薄膜晶体管包括：
依次层叠设置的第一源漏层，第一绝缘层，第二源漏层和第二绝缘层；
栅极和环绕所述栅极的沟道层，位于所述第二绝缘层、所述第二源漏层和所述第一绝缘层内；所述沟道层与所述第一源漏层、所述第一绝缘层、所述第二源漏层和所述第二绝缘层接触。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述栅极包括栅极竖直部和栅极水平部，所述沟道层包括沟道竖直部和沟道水平部；
所述沟道竖直部环绕所述栅极竖直部；所述沟道竖直部与所述第一源漏层，所述第一绝缘层，所述第二源漏层和所述第二绝缘层接触；
所述沟道水平部位于所述栅极水平部与所述第二绝缘层的上表面之间。
3.如权利要求1所述的薄膜晶体管，其特征在于，所述栅极和所述沟道层的顶部与所述第二绝缘层齐平。
4.如权利要求1所述的薄膜晶体管，其特征在于，所述第二绝缘层的厚度为10～30纳米。
5.如权利要求1所述的薄膜晶体管，其特征在于，所述第二绝缘层的材质为二氧化硅。
6.如权利要求1所述的薄膜晶体管，其特征在于，还包括栅介质层，所述栅介质层位于所述栅极和所述沟道层之间。
7.一种薄膜晶体管的制备方法，其特征在于，所述制备方法包括：
提供衬底；
在所述衬底上依次形成第一源漏层、第一绝缘层，第二源漏层和第二绝缘层；
在所述第二绝缘层、所述第二源漏层、所述第一绝缘层内形成延伸至所述第一源漏层的孔；
在所述孔的内壁和所述第二绝缘层的表面沉积沟道材料，形成沟道层；
在所述沟道层上沉积栅极材料，形成栅极。
8.如权利要求7所述的制备方法，其特征在于，在所述形成栅极之后，所述制备方法还包括：
去除位于第二绝缘层上表面的沟道层和栅极。
9.一种存储器，其特征在于，所述存储器包括多个存储阵列，所述存储阵列包括如权利要求1～6中任一项所述的薄膜晶体管。
10.一种显示器，其特征在于，所述显示器包括像素电路，所述像素电路包括如权利要求1～6中任一项所述的薄膜晶体管。
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