WO2023236376A1 - 场效应晶体管及其制备方法、存储器、显示器 - Google Patents

场效应晶体管及其制备方法、存储器、显示器 Download PDF

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WO2023236376A1
WO2023236376A1 PCT/CN2022/116073 CN2022116073W WO2023236376A1 WO 2023236376 A1 WO2023236376 A1 WO 2023236376A1 CN 2022116073 W CN2022116073 W CN 2022116073W WO 2023236376 A1 WO2023236376 A1 WO 2023236376A1
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layer
source
drain
channel
effect transistor
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PCT/CN2022/116073
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French (fr)
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刘明
李泠
耿玓
段新绿
陆丛研
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中国科学院微电子研究所
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Definitions

  • the present disclosure relates to a field effect transistor and a preparation method thereof, a memory, and a display.
  • Fin Field Effect Transistor can greatly improve circuit control and reduce leakage, while significantly shortening the gate length of the transistor.
  • FinFET Fin Field Effect Transistor
  • the FinFET architecture is suitable for 10-22nm processes. For processes below 10nm, such as 7nm, 5nm, and 3nm, it will be limited by FinFET width scaling, and it is impossible to continue to reduce the size while ensuring high performance and low power consumption; in addition, On the one hand, FinFET also has the problem of poor contact performance.
  • the present disclosure provides a field effect transistor, a preparation method thereof, a memory, and a display, and solves the current technical problems of how to further reduce the size of the transistor, reduce power consumption, and improve contact performance.
  • a first aspect of the present disclosure provides a field effect transistor, including:
  • a first source-drain layer, an insulating layer and a second source-drain layer are stacked in sequence; a gate electrode and a channel layer surrounding the gate electrode are located in the second source-drain layer and the insulating layer; the trench The channel layer is in contact with the first source and drain layer and the second source and drain layer; wherein, the channel layer includes an outer layer and an inner layer; the inner layer is close to the gate; and the outer layer is in contact with the gate electrode.
  • the insulating layer, the first source and drain layer and the second source and drain layer are in contact; the material of the outer layer and the inner layer is indium oxide.
  • a second aspect of the present disclosure provides a method for manufacturing a field effect transistor, including:
  • a substrate sequentially form a first source-drain layer, an insulating layer and a second source-drain layer on the substrate; form a layer extending to the first source-drain layer in the second source-drain layer and the insulating layer.
  • layer of holes deposit indium oxide on the inner wall of the hole and the surface of the insulating layer to form an outer layer; deposit a channel material on the outer layer to form a channel layer; wherein the channel layer further It includes an inner layer, and the material of the inner layer is indium oxide; a gate material is deposited on the inner layer to form a gate electrode.
  • a third aspect of the present disclosure provides a memory, which includes a plurality of memory arrays, and the memory arrays include the field effect transistors provided in the first aspect.
  • a fourth aspect of the present disclosure provides a display, which includes a pixel circuit including the field effect transistor provided in the first aspect.
  • the present disclosure provides a field effect transistor, the gate of which passes through the first source-drain layer and the insulating layer, and the annular channel is arranged around the gate, forming a Channel All Around with an annular channel arranged around the gate, referred to as a transistor with a CAA architecture. .
  • the CAA architecture transistor of the present disclosure has: first, compared with the planar channel structure, the vertical channel structure reduces the horizontal area occupation of the electrode by stacking the source/drain electrodes, and can Significantly reducing the size of the transistor is conducive to reducing the device unit density; the channel length is determined by the thickness of the insulating layer, and the shrinkage of the channel length is not limited by the photolithography process, which is conducive to achieving a smaller channel length, thereby improving the channel length.
  • the channel width to length ratio achieves greater device current and reduces power consumption; secondly, the CAA architecture with an annular channel surrounding the gate can greatly increase the contact area between the gate and the channel, thus significantly enhancing the gate The gate control capability of the pole to channel improves the current conduction efficiency; and compared with the GAA (Gate All Around, gate omnidirectional field effect transistor) architecture, the CAA architecture also has a larger contact between the gate and the channel area; thirdly, the outer layer in the channel layer that is in contact with the first source and drain layer and the second source and drain layer is indium oxide, which can improve the connection between the channel layer and the first source and drain layer and the second source and drain layer. Contact performance; and the inner layer in the channel layer close to the gate is also indium oxide, which can improve the interface characteristics, thereby improving the sub-threshold characteristics and operating current of the transistor.
  • GAA Gate All Around, gate omnidirectional field effect transistor
  • Figure 1 is a schematic structural diagram of a field effect transistor according to an embodiment of the present disclosure
  • Figure 2 is an exploded schematic diagram of the layered structure of the channel layer according to an embodiment of the present disclosure
  • Figure 3 is a schematic flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present disclosure
  • Figure 4 is a schematic diagram of a storage array according to an embodiment of the present disclosure.
  • First source and drain layer 2. Insulating layer; 3. Second source and drain layer; 4. Channel layer; 41. Deposition sublayer; 411. Indium oxide layer; 412. Gallium oxide layer; 413. Zinc Oxide layer; 42, inner layer; 5, gate electrode; 6, gate dielectric layer; 71, first field effect transistor; 72, second field effect transistor.
  • horizontal does not imply a requirement that the component be absolutely horizontal or overhanging, but may be slightly tilted.
  • “horizontal” only means that its direction is more horizontal than “vertical”. It does not mean that the structure must be completely horizontal, but can be slightly tilted.
  • the present disclosure provides a field effect transistor (Field Effect Transistor, FET for short), whose structure is shown in Figure 1 and includes:
  • the first source and drain layer 1, the insulating layer 2 and the second source and drain layer 3 are stacked in sequence;
  • the gate electrode 5 and the channel layer 4 surrounding the gate electrode 5 are located in the second source and drain layer 3 and the insulating layer 2; the channel layer 4 is in contact with the first source and drain layer 1 and the second source and drain layer 3.
  • the FET transistor provided in this embodiment has a vertical channel structure.
  • the second source-drain layer 3 can be regarded as the upper source-drain electrode of the FET, and the first source-drain layer 1 can be regarded as the lower source-drain electrode of the FET.
  • the second source-drain layer 3 can be prepared as a source electrode, and the first source-drain layer 1 can be prepared as a drain electrode, or the second source-drain layer 3 can be prepared as a drain electrode, and the first source-drain layer 1 can be prepared as a drain electrode.
  • the optional materials of the first source and drain layer 1 and the second source and drain layer 3 are at least one of titanium, titanium nitride, tungsten, molybdenum, gold, and silver.
  • the insulating layer 2 is located between the second source and drain layer 3 and the first source and drain layer 1 and plays an insulating role.
  • the material of the insulating layer 2 may be SiO 2 .
  • the gate 5 has a vertical gate 5 structure, and the bottom of the gate 5 at least penetrates the second source and drain layer 3 and enters the insulating layer 2 .
  • the bottom of the gate electrode 5 can also penetrate the insulating layer 2 and enter the first source and drain layer 1 .
  • the shape of the grid electrode 5 can be cylindrical, and its cross-sectional shape can be circular, elliptical, or polygonal; the shape of the grid electrode 5 can also be annular, and its cross-sectional shape can be a circular ring, an elliptical ring, or a polygonal ring. , can be determined according to actual needs.
  • the optional materials of the gate 5 include: indium tin oxide (ITO, Indium Tin Oxide), indium zinc oxide (IZO, Indium Zinc Oxide) or titanium nitride (TiN).
  • the channel layer 4 is a vertical channel structure and is formed around the second source and drain layer 3 and the gate electrode 5 in the insulating layer 2 . Therefore, the field effect transistor of this embodiment belongs to the CAA (Channel All Around) architecture with a ring channel all around the gate.
  • the cross-sectional shape of the channel layer 4 may be circular, elliptical or polygonal, and the cross-sectional shape of the channel layer 4 may be the same as or different from the cross-sectional shape of the gate electrode 5 .
  • a better shape of the channel layer 4 is to select the shape with the largest cross-sectional circumference under the premise that the cross-sectional area of the channel layer 4 remains unchanged. This can increase the channel width of the channel layer 4, thereby further improving the channel width.
  • the track width to length ratio is beneficial to increasing the saturation current of the field effect transistor.
  • the optional material of the channel layer 4 is Indium Gallium Zinc Oxide (IGZO).
  • the field effect transistor further includes a gate dielectric layer 6 located between the gate electrode 5 and the channel layer 4 .
  • Optional materials for the gate dielectric layer 6 include: at least one of hafnium oxide, hafnium aluminum oxide, and aluminum oxide.
  • the gate electrode 5 penetrates the first source-drain layer 1 and the insulating layer 2, and the annular channel is arranged around the gate electrode 5, forming a channel in which the annular channel layer 4 is arranged around the gate electrode 5.
  • All Around referred to as CAA architecture transistors, has the following characteristics compared to FinFET architecture transistors:
  • the vertical channel structure reduces the horizontal area occupied by the electrodes by stacking the source/drain electrodes, which can significantly reduce the size of the transistor and help reduce the device unit density;
  • the channel length is Determined by the thickness of the insulating layer 2, the shrinkage of the channel length is not limited by the photolithography process, which is conducive to achieving a smaller channel length, thus increasing the channel width-to-length ratio, achieving greater device current and reducing power consumption;
  • the CAA structure with a ring channel surrounding the gate can greatly increase the contact area between the gate 5 and the channel layer 4, thereby significantly enhancing the gate control ability of the gate 5 on the channel layer 4 , improving the current conduction efficiency; and compared to the GAA (Gate All Around, gate omnidirectional field effect transistor) architecture, the CAA architecture also has a larger contact area between the gate 5 and the channel layer 4.
  • GAA Gate All Around, gate omnidirectional field effect transistor
  • the field effect transistor provided in this embodiment also adjusts the channel structure, as follows:
  • the channel layer 4 includes an outer layer and an inner layer; the inner layer is close to the gate 5; the outer layer is in contact with the insulating layer 2, the first source and drain layer 1 and the second source and drain layer 3; the material of the outer layer and the inner layer is indium. Oxide.
  • the channel layer 4 has a layered structure, the inner layer is close to the gate 5, the outer layer is in contact with the insulating layer 2 and the second source and drain layer 3, and the material of the inner layer and the outer layer is indium oxide.
  • the outer layer of the channel layer 4 that is in contact with the first source and drain layer 1 and the second source and drain layer 3 is indium oxide InOx, which can improve the contact between the channel layer 4, especially the IGZO channel layer 4 and the first source and drain layer.
  • the contact performance between layer 1 and the second source and drain layer 3; and the inner layer region closest to the gate 5 in the channel layer 4 is also indium oxide, which can improve the interface characteristics and thereby improve the sub-threshold characteristics and Working current.
  • the process of forming the layered channel can use an atomic layer deposition method.
  • a plasma enhanced atomic layer deposition (PE-ALD) method can be used for deposition.
  • sheet materials are deposited by the PE-ALD method to form an IGZO channel.
  • the channel layer 4 also includes N deposition sub-layers 41, N ⁇ 1 and is an integer; each deposition sub-layer 41 includes Indium oxide layer 411, gallium oxide layer 412 and zinc oxide layer 413; indium oxide layer 411 is close to the insulating layer 2, zinc oxide layer 413 is close to the gate 5, gallium oxide layer 412 is located between the zinc oxide layer 413 and between indium oxide layers 411.
  • the channel layer 4 When preparing the channel layer 4, first form the first source-drain layer 1, the insulating layer 2, and the second source-drain layer 3 on the substrate and etch them into holes, and then deposit the first deposition sub-layer on the inner wall of the holes.
  • the indium oxide layer 411 in 41 is then deposited on the surface of the indium oxide layer 411 in the order of the gallium oxide layer 412 and the zinc oxide layer to obtain the first deposition sub-layer 41; the above deposition process is cycled to deposit A plurality of sub-layers 41 are deposited.
  • each deposition sub-layer 41 includes a three-layer structure from outside to inside, that is, from the insulating layer 2 to the direction of the gate 5: InO x -GaO x -ZnO x .
  • the channel layer The outer layer of 4 is actually the InO 42.
  • InO x and GaO x are adjacent, and there will be no situation where InO x is completely sandwiched by ZnO x such as ZnO x -InO x -ZnO x .
  • ZnO x such as ZnO x -InO x -ZnO x .
  • This is beneficial to inhibiting the formation of oxygen vacancies.
  • Improve device controllability For the CAA-structured FET of this embodiment, since the first source-drain layer 1 and the second source-drain layer 3 are deposited before the IGZO channel layer 4, good electrochemical properties can be obtained between the channel layer 4 and the source/drain electrode. Contact characteristics and better interface characteristics, thereby further improving the sub-threshold characteristics and operating current of the device.
  • the thickness of each deposited oxide layer and the total thickness of the IGZO channel layer 4 are approximately 3 to 5 nm.
  • the deposition thickness of each oxide layer is about several angstroms, and the thickness ratio of each layer is adjustable.
  • the thickness ratio of InOx : GaOx : ZnOx is 3: 1:1 ⁇ 6:1:1.
  • the present disclosure provides a method for manufacturing a field effect transistor, as shown in Figure 3.
  • the steps include S301 to S306, specifically as follows:
  • S301 Provide substrate; silicon substrate can be used;
  • S302 Form the first source-drain layer 1, the insulating layer 2 and the second source-drain layer 3 sequentially on the substrate;
  • a pre-oxidation layer can be deposited on the substrate first, with a thickness of 300 to 400 nm. After the deposition is completed, pre-cleaning is performed, and then a metal material layer forming the first source and drain layer 1 is deposited on the pre-oxidation layer, as follows:
  • the pre-oxidation layer is pre-cleaned, and the source-drain metal material is deposited on the pre-cleaned pre-oxidation layer; then a double protective layer is deposited on the source-drain metal material layer, which can be a double-layer protective layer formed of SiN and SiO.
  • the thickness of the protective layer is about 200nm; next, photolithography of the source and drain metal material layer is performed, specifically covering the double layer protective layer with photoresist and then sequentially exposing, developing, and etching to form the first source and drain layer 1;
  • a filling oxide layer is deposited on the first source and drain layer 1, and then chemical mechanical polishing and cleaning are performed.
  • the insulating layer material is deposited to form the insulating layer 2;
  • S303 Form a hole extending to the first source-drain layer 1 in the second source-drain layer 3 and the insulating layer 2; a deep etching method can be used to form the required hole, specifically as follows:
  • the leveling oxide is deposited again on the second source and drain layer 3, and then chemical mechanical polishing and cleaning are performed, and the polishing position stays on the leveling oxide layer;
  • Form a through hole deposit a double protective layer (SiN+SiO) at the location where the through hole is to be formed, then cover it with photoresist, and perform exposure, development, etching, cleaning and chemical mechanical polishing to form the bottom to the first Source and drain layer 1, the bottom reaches the through hole of the second source and drain layer 3;
  • a double protective layer SiN+SiO
  • Form the channel hole deposit a double protective layer (SiN+SiO) at the location where the channel hole is to be formed, then cover it with photoresist, align the second source and drain layer 3, and then perform exposure, development, etching and cleaning.
  • a channel hole is formed that penetrates the second source and drain layer 3 and the insulating layer 2 and reaches the bottom of the first source and drain layer 1 .
  • S304 Deposit indium oxide on the inner wall of the hole and the surface of the insulating layer 2 to form an outer layer;
  • S305 Deposit the channel material on the outer layer to form the channel layer 4; wherein the channel layer 4 also includes an inner layer 42, and the inner layer 42 is made of indium oxide;
  • the method of depositing the channel material and the gate material in the channel hole may be a plasma enhanced atomic layer deposition (PE-ALD) method.
  • PE-ALD plasma enhanced atomic layer deposition
  • the gate dielectric material is first deposited to form the gate dielectric layer 6, and then the gate material is deposited on the surface of the gate dielectric layer 7.
  • the method of depositing the gate dielectric material may also be atomic layer deposition. .
  • the present disclosure provides a memory.
  • the memory includes a plurality of memory arrays.
  • the memory arrays include the field effect transistors provided in the first aspect.
  • Figure 4 shows an optional 2T0C memory array structure.
  • a memory array includes two provided by embodiments of the present disclosure: a first field effect transistor 71 and a second field effect transistor 72, wherein the first field effect transistor
  • the gate of the transistor 71 is electrically connected to the write word line WWL
  • the source is electrically connected to the write bit line WBL
  • the drain is electrically connected to the gate of the second field effect transistor 72
  • the source of the second field effect transistor 72 is electrically connected to the read word line RWL.
  • the drain is electrically connected to the read bit line RBL.
  • the gate of one TFT transistor can be directly connected to the source and drain of another TFT transistor without the need for external leads, so the entire memory can be greatly reduced.
  • the volume is conducive to further miniaturization of the memory.
  • the field effect transistor provided by the embodiment of the present disclosure can also be applied to 1T0C, 1T1C, and 2T1C memory arrays, which are not specifically limited here.
  • the present disclosure provides a display, the display includes a pixel circuit, and the pixel circuit includes the field effect transistor provided in the first aspect.
  • the present disclosure has the following beneficial effects or advantages:
  • the present disclosure provides a field effect transistor, the gate of which passes through the first source-drain layer and the insulating layer, and the annular channel is arranged around the gate, forming a Channel All Around with an annular channel arranged around the gate, referred to as a transistor with a CAA architecture. .
  • the CAA architecture transistor of the present disclosure has: first, compared with the planar channel structure, the vertical channel structure reduces the horizontal area occupation of the electrode by stacking the source/drain electrodes, and can Significantly reducing the size of the transistor is conducive to reducing the device unit density; the channel length is determined by the thickness of the insulating layer, and the shrinkage of the channel length is not limited by the photolithography process, which is conducive to achieving a smaller channel length, thereby improving the channel length.
  • the channel width to length ratio achieves greater device current and reduces power consumption; secondly, the CAA architecture with an annular channel surrounding the gate can greatly increase the contact area between the gate and the channel, thus significantly enhancing the gate The gate control capability of the pole to channel improves the current conduction efficiency; and compared with the GAA (Gate All Around, gate omnidirectional field effect transistor) architecture, the CAA architecture also has a larger contact between the gate and the channel area; thirdly, the outer layer in the channel layer that is in contact with the first source and drain layer and the second source and drain layer is indium oxide, which can improve the connection between the channel layer and the first source and drain layer and the second source and drain layer. Contact performance; and the inner layer in the channel layer close to the gate is also indium oxide, which can improve the interface characteristics, thereby improving the sub-threshold characteristics and operating current of the transistor.
  • GAA Gate All Around, gate omnidirectional field effect transistor

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Abstract

本文公开了一种场效应晶体管及其制备方法、存储器、显示器，其中的场效应晶体管包括：依次层叠设置的第一源漏层(1)，绝缘层(2)和第二源漏层(3)；栅极(5)和环绕所述栅极(5)的沟道层(4)，位于所述第二源漏层(3)和所述绝缘层(2)内；所述沟道层(4)与所述第一源漏层(1)和所述第二源漏层(3)接触；其中，所述沟道层(4)包括外层和内层(42)；所述内层(42)靠近所述栅极(5)；所述外层与所述绝缘层(2)、所述第一源漏层(1)和所述第二源漏层(3)接触；所述外层和所述内层(42)的材质均为铟氧化物；上述场效应晶体管中的沟道层(4)的外层和内层(42)均为铟氧化物，能够解决进一步缩小晶体管的尺寸、降低功耗并提高接触性能的问题。

Description

场效应晶体管及其制备方法、存储器、显示器
相关申请的交叉引用
本申请要求于2022年6月10日提交、申请号为202210657793.9且名称为“场效应晶体管及其制备方法、存储器、显示器”的中国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开内容涉及一种场效应晶体管及其制备方法、存储器、显示器。
背景技术
根据摩尔定律，集成电路不断向更细微尺寸发展，而先进制程则是集成电路制造中最为顶尖的节点之一。目前，先进制程已发展至5/7nm节点，这对晶体管的进一步微型化提出了极高的要求。
目前晶体管的一个关键架构：鳍式场效应晶体管(Fin Field Effect Transistor，简称FinFET)的设计可以大幅改善电路控制并减少漏电流(leakage)，同时大幅缩短晶体管的栅长。然而，FinFET架构适用于10～22nm的制程，对于10nm以下，如7nm，5nm，3nm的制程，则会受到FinFET宽度缩放的限制，无法在继续缩小尺寸的同时保证高性能和低功耗；另一方面，FinFET还存在接触性能较差的问题。
因此，如何进一步缩小晶体管尺寸、降低晶体管的功耗并提高接触性能，成为目前亟需解决的问题。
发明内容
本公开内容提供了一种场效应晶体管及其制备方法、存储器、显示器，解决了目前如何进一步缩小晶体管的尺寸、降低功耗并提高接触性能的技术问题。
本公开第一方面提供了一种场效应晶体管，包括：
依次层叠设置的第一源漏层，绝缘层和第二源漏层；栅极和环绕所述栅极的沟道层，位于所述第二源漏层和所述绝缘层内；所述沟道层与所述第一 源漏层和所述第二源漏层接触；其中，所述沟道层包括外层和内层；所述内层靠近所述栅极；所述外层与所述绝缘层、所述第一源漏层和所述第二源漏层接触；所述外层和所述内层的材质均为铟氧化物。
本公开第二方面提供了一种场效应晶体管的制备方法，包括：
提供衬底；在所述衬底上依次形成第一源漏层、绝缘层和第二源漏层；在所述第二源漏层、所述绝缘层内形成延伸至所述第一源漏层的孔；在所述孔的内壁和所述绝缘层的表面沉积铟氧化物，形成外层；在所述外层上沉积沟道材料，形成沟道层；其中，所述沟道层还包括内层，所述内层的材质为铟氧化物；在所述内层上沉积栅极材料，形成栅极。
本公开第三方面提供了一种存储器，所述存储器包括多个存储阵列，所述存储阵列包括第一方面提供的场效应晶体管。
本公开第四方面提供了一种显示器，所述显示器包括像素电路，所述像素电路包括第一方面提供的场效应晶体管。
本公开提供了一种场效应晶体管，其栅极下穿第一源漏层和绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极设置的Channel All Around，简称CAA架构的晶体管。本公开的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，沟道层中与第一源漏层和第二源漏层接触的外层为铟氧化物，能够提高沟道层与第一源漏层、第二源漏层之间的接触性能；而沟道层中靠近栅极的内层同样为铟氧化物，能够提高界面特性，从而提高晶体管的亚阈值特性和工作电流。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的 技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
图1为根据本公开实施例的场效应晶体管的结构示意图；
图2为根据本公开实施例的沟道层的分层结构***示意图；
图3为根据本公开实施例的场效应晶体管的制备方法流程示意图；
图4为根据本公开实施例的存储阵列示意图；
附图标记说明：
1、第一源漏层；2、绝缘层；3、第二源漏层；4、沟道层；41、沉积子层；411、铟氧化物层；412、镓氧化物层；413、锌氧化物层；42、内层；5、栅极；6、栅介质层；71、第一场效应晶体管；72、第二场效应晶体管。
具体实施方式
本公开内容为了使本公开所属技术领域中的技术人员更清楚地理解本公开，下面结合附图，通过具体实施例对本公开技术方案作详细描述。在整个说明书中，除非另有特别说明，本文使用的术语应理解为如本领域中通常所使用的含义。因此，除非另有定义，本文使用的所有技术和科学术语具有与本公开所属领域技术人员的一般理解相同的含义。若存在矛盾，本说明书优先。除非另有特别说明，本公开中用到的各种设备等，均可通过市场购买得到或者可通过现有方法制备得到。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
此外，术语“水平”、“竖直”、“悬垂”等术语并不表示要求部件绝对水平 或悬垂，而是可以稍微倾斜。如“水平”仅仅是指其方向相对“竖直”而言更加水平，并不是表示该结构一定要完全水平，而是可以稍微倾斜。
为了进一步缩小晶体管的尺寸、降低功耗，在第一方面，本公开提供了一种场效应晶体管(Field Effect Transistor，简称FET)，其结构参阅图1，包括：
依次层叠设置的第一源漏层1，绝缘层2和第二源漏层3；
栅极5和环绕栅极5的沟道层4，位于第二源漏层3和绝缘层2内；沟道层4与第一源漏层1和第二源漏层3接触。
本实施例提供的FET晶体管为垂直沟道结构，为了方便理解，可以将第二源漏层3视为FET的上层源漏极，将第一源漏层1视为FET的下层源漏极。在实际使用时，可以将第二源漏层3制备成源极，第一源漏层1制备为漏极，也可以将第二源漏层3制备成漏极，第一源漏层1制备为源极，对此不进行具体限定。第一源漏层1和第二源漏层3的可选材质为钛、氮化钛、钨、钼、金、银中的至少一种。
绝缘层2位于第二源漏层3和第一源漏层1之间，起到绝缘作用。绝缘层2的材质可以是SiO 2。
栅极5为垂直栅极5结构，栅极5的底部至少穿透第二源漏层3并进入绝缘层2。栅极5的底部还可以穿透绝缘层2进入第一源漏层1。栅极5的形状可以是柱形的，其横截面形状可以是圆形，椭圆形或多边形；栅极5的形状还可以是环形的，其横截面形状可以是圆环，椭圆环或多边形环，可根据实际需求确定。栅极5的可选材质有：氧化铟锡(ITO，Indium Tin Oxide)，氧化铟锌(IZO，Indium Zinc Oxide)或氮化钛(TiN)。
沟道层4为垂直沟道结构，环绕第二源漏层3和绝缘层2内的栅极5形成。因此，本实施例的场效应晶体管属于环形沟道全环绕栅极的CAA(Channel All Around)架构。沟道层4的横截面形状可以是圆形，椭圆形或多边形的，沟道层4的横截面形状可以与栅极5的横截面形状相同或不同。
一个较佳的沟道层4形状是在沟道层4的横截面面积不变的前提下，选择横截面周长最大的形状，如此能够提高沟道层4的沟道宽度，从而进一步提高沟道宽长比，有利于提高场效应晶体管的饱和电流。
在本实施例中，沟道层4的可选材质为氧化铟镓锌IGZO(Indium Gallium Zinc Oxide)。
在一些实施方式中，如图1所示，场效应晶体管还包括栅介质层6，栅介质层6位于栅极5和沟道层4之间。栅介质层6的可选材质包括：氧化铪、铪铝氧化物和三氧化二铝中的至少一种。
至此，本实施例提供的FET晶体管，其栅极5下穿第一源漏层1和绝缘层2，环形沟道环绕栅极5设置，形成环形的沟道层4环绕栅极5设置的Channel All Around，简称CAA架构的晶体管，其相比于FinFET架构的晶体管，具有如下的特点：
1)垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层2的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；
2)第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极5和沟道层4之间的接触面积，从而显著增强栅极5对沟道层4的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极5与沟道层4之间的接触面积。
而为了进一步提高接触性能，本实施例提供的场效应晶体管还对沟道结构进行了调整，具体如下：
沟道层4包括外层和内层；内层靠近栅极5；外层与绝缘层2、第一源漏层1和第二源漏层3接触；外层和内层的材质均为铟氧化物。
具体的，沟道层4具有分层结构，其内层靠近栅极5，外层与绝缘层2和第二源漏层3接触，并且内层和外层的材质均为铟氧化物，这个结构特点使本实施例提供的FET晶体管还具有如下的优势：
3)沟道层4中与第一源漏层1和第二源漏层3接触的外层为铟氧化物InOx，能够提高沟道层4，尤其是IGZO沟道层4与第一源漏层1、第二源漏层3之间的接触性能；而沟道层4中最接近栅极5的内层区域同样为铟氧化物，如此能够提高界面特性，从而提高晶体管的亚阈值特性和工作电流。
形成分层沟道的工艺可以采用原子层沉积方法，具体的，可采用等离子增强原子层沉积(PE-ALD)方法进行沉积。
本实施例通过PE-ALD方法沉积片层材料形成IGZO沟道，如图2所示，沟道层4还包括N个沉积子层41，N≥1且为整数；每一沉积子层41包括铟氧化物层411、镓氧化物层412和锌氧化物层413；铟氧化物层411靠近绝缘层2，锌氧化物层413靠近栅极5，镓氧化物层412位于锌氧化物层413和铟氧化物层411之间。
在制备沟道层4时，先在衬底上形成第一源漏层1、绝缘层2、第二源漏层3并刻蚀成孔后，在孔的内壁先沉积第一个沉积子层41中的铟氧化物层411，然后在铟氧化物层411的表面按镓氧化物层412、锌氧化物层的顺序进行沉积，得到第一个沉积子层41；循环上述沉积过程，沉积出多个沉积子层41。因此，按照沉积的顺序，每一个沉积子层41由外至内，即从绝缘层2指向栅极5的方向包括三片层结构：InO x-GaO x-ZnO x，此时，沟道层4的外层实际上是第一个沉积形成的沉积子层41中的InO x层，而在最后一个沉积子层41中的ZnO x沉积完成后，再额外沉积一层InO x层作为内层42。
在采用上述沉积顺序进行沉积时，InO x和GaO x相邻，不会出现ZnO x-InO x-ZnO x这种InO x完全被ZnO x包夹的情况，如此有利于抑制氧空位的形成，提高器件的可控性。对于本实施例的CAA架构的FET，由于第一源漏层1和第二源漏层3先于IGZO沟道层4沉积，所以在沟道层4和源/漏极之间能够获得良好的接触特性和更好的界面特性，从而进一步提高器件的亚阈值特性和工作电流。
本实施例中每一层沉积的氧化物的厚度，IGZO沟道层4的总厚度约为3～5nm。而循环的沉积子层41中，每一层氧化物的沉积厚度约为数埃，每一层的厚度比例可调，在一些实施方式中，InO x：GaO x：ZnO x的厚度比为3:1:1～6:1:1。
在第二方面，本公开提供了一种场效应晶体管的制备方法，如图3所示，其步骤包括S301～S306，具体如下：
S301：提供衬底；可使用硅衬底；
S302：在衬底上依次形成第一源漏层1、绝缘层2和第二源漏层3；
具体的，可先在衬底上沉积预氧化层，厚度为300～400nm，沉积完成后进行预清洗，然后在预氧化层上沉积形成第一源漏层1的金属材料层，具体如下：
对预氧化层进行预清洗，在预清洗后的预氧化层上沉积源漏金属材料；然后在源漏金属材料层上进行双保护层沉积，可以是SiN和SiO形成的双层保护层，双层保护层的厚度约为200nm；接下来进行源漏金属材料层的光刻，具体是在双层保护层上覆盖光刻胶后依次进行曝光、显影、刻蚀形成第一源漏层1；
接着，在第一源漏层1上进行填平氧化层沉积，然后再进行化学机械抛光、清洗，完成后沉积绝缘层材料形成绝缘层2；
接着，在绝缘层2上重复第一源漏层1的步骤沉积源漏金属材料，然后依次进行双保护层沉积、覆盖光刻胶、曝光、显影、刻蚀、清洗形成第二源漏层3；
S303：在第二源漏层3、绝缘层2内形成延伸至第一源漏层1的孔；可采用深刻刻蚀方法形成所需的孔，具体如下：
在第二源漏层3上再次进行填平氧化物沉积，然后进行化学机械抛光、清洗，抛光位置停留在填平氧化层上；
形成通孔：在要形成通孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，并进行曝光、显影、刻蚀、清洗和化学机械抛光，分别形成底部到达第一源漏层1、底部到达第二源漏层3的通孔；
形成沟道孔：在要形成沟道孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，对准第二源漏层3后进行曝光、显影、刻蚀并清洗，形成穿透第二源漏层3、绝缘层2，且底部到达第一源漏层1的沟道孔。
S304：在孔的内壁和绝缘层2的表面沉积铟氧化物，形成外层；
S305：在外层上沉积沟道材料，形成沟道层4；其中，沟道层4还包括内层42，内层42的材质为铟氧化物；
S306：在内层42上沉积栅极材料，形成栅极5。
具体的，在沟道孔内沉积沟道材料、栅级材料的方法可以是等离子增强原子层沉积(PE-ALD)方法。
在一些实施方式中，在沉积沟道材料后，先沉积栅介质材料以形成栅介质层6，然后在栅介质层7的表面沉积栅极材料，沉积栅介质材料的方法也可以是原子层沉积。
在第三方面，本公开提供了一种存储器，存储器包括多个存储阵列，存储阵列包括第一方面提供的场效应晶体管。
图4示出了一种可选的2T0C的存储阵列结构，一个存储阵列中包括两个本公开实施例提供的：第一场效应晶体管71和第二场效应晶体管72，其中，第一场效应晶体管71的栅极电连接写字线WWL，源极电连接写位线WBL，漏极电连接第二场效应晶体管72的栅极，第二场效应晶体管72的源极电连接读字线RWL，漏极电连接读位线RBL。
将本公开实施例提供的场效应晶体管应用于2T0C的存储电路，可以将一个TFT晶体管的栅极与另一个TFT晶体管的源漏极直接连接，无需要外接引线，因此可以极大的缩小整个存储器的体积，有利于进一步实现存储器的小型化。
另外，本公开实施例提供的场效应晶体管还可以应用到1T0C，1T1C，2T1C的存储阵列，在此不进行具体限定。
在第四方面，本公开提供了一种显示器，显示器包括像素电路，像素电路包括第一方面提供的场效应晶体管。
通过本公开的一个或者多个实施例，本公开具有以下有益效果或者优点：
本公开提供了一种场效应晶体管，其栅极下穿第一源漏层和绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极设置的Channel All Around，简称CAA架构的晶体管。本公开的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能 力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，沟道层中与第一源漏层和第二源漏层接触的外层为铟氧化物，能够提高沟道层与第一源漏层、第二源漏层之间的接触性能；而沟道层中靠近栅极的内层同样为铟氧化物，能够提高界面特性，从而提高晶体管的亚阈值特性和工作电流。
尽管已描述了本公开的优选实施例，但本领域内的普通技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种场效应晶体管，包括：
    依次层叠设置的第一源漏层，绝缘层和第二源漏层；
    栅极和环绕所述栅极的沟道层，位于所述第二源漏层和所述绝缘层内；所述沟道层与所述第一源漏层和所述第二源漏层接触；
    其中，所述沟道层包括外层和内层；所述内层靠近所述栅极；所述外层与所述绝缘层、所述第一源漏层和所述第二源漏层接触；所述外层和所述内层的材质均为铟氧化物。
  2. 如权利要求1所述的场效应晶体管，其中，所述沟道层还包括N个沉积子层，N≥1且为整数；
    每一所述沉积子层包括铟氧化物层、镓氧化物层和锌氧化物层；所述铟氧化物层靠近所述绝缘层，所述锌氧化物层靠近所述栅极，所述镓氧化物层位于所述锌氧化物层和所述铟氧化物层之间；
    其中，所述外层是与所述栅极接触的铟氧化物层。
  3. 如权利要求1所述的场效应晶体管，其中，所述沟道层的厚度为3纳米至5纳米。
  4. 如权利要求1所述的场效应晶体管，其中，所述沟道层的横截面形状为圆形、椭圆形、多边形中的其中一种。
  5. 如权利要求1所述的场效应晶体管，其中，还包括栅介质层，所述栅介质层位于所述栅极层和所述沟道层之间。
  6. 如权利要求1所述的场效应晶体管，其中，所述栅极的材质为氧化铟锡、氧化铟锌、氮化钛中的其中一种。
  7. 如权利要求1所述的场效应晶体管，其中，所述第一源漏层和所述第二源漏层的材质为钛、氮化钛、钨、钼、金、银中的至少一种。
  8. 一种场效应晶体管的制备方法，包括：
    提供衬底；
    在所述衬底上依次形成第一源漏层、绝缘层和第二源漏层；
    在所述第二源漏层、所述绝缘层内形成延伸至所述第一源漏层的孔；
    在所述孔的内壁和所述绝缘层的表面沉积铟氧化物，形成外层；
    在所述外层上沉积沟道材料，形成沟道层；其中，所述沟道层还包括内层，所述内层的材质为铟氧化物；
    在所述内层上沉积栅极材料，形成栅极。
  9. 一种存储器，包括多个存储阵列，所述存储阵列包括如权利要求1～7中任一项所述的场效应晶体管。
  10. 一种显示器，包括像素电路，所述像素电路包括如权利要求1～7中任一项所述的场效应晶体管。
PCT/CN2022/116073 2022-06-10 2022-08-31 场效应晶体管及其制备方法、存储器、显示器 WO2023236376A1 (zh)

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