WO2023236375A1 - 薄膜晶体管及其制备方法、存储器和显示器 - Google Patents

薄膜晶体管及其制备方法、存储器和显示器 Download PDF

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WO2023236375A1
WO2023236375A1 PCT/CN2022/116072 CN2022116072W WO2023236375A1 WO 2023236375 A1 WO2023236375 A1 WO 2023236375A1 CN 2022116072 W CN2022116072 W CN 2022116072W WO 2023236375 A1 WO2023236375 A1 WO 2023236375A1
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layer
metal layer
source
metal
drain
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PCT/CN2022/116072
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English (en)
French (fr)
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刘明
李泠
耿玓
段新绿
陆丛研
卢年端
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中国科学院微电子研究所
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Definitions

  • the present disclosure relates to a thin film transistor and a preparation method thereof, a memory and a display.
  • Fin Field Effect Transistor can greatly improve circuit control and reduce leakage, while significantly shortening the gate length of the transistor.
  • FinFET Fin Field Effect Transistor
  • the FinFET architecture is mainly suitable for processes between 10 and 22nm.
  • processes below 10nm, such as 7nm, 5nm, and 3nm it will be limited by the scaling of FinFET width and cannot ensure high performance and low power consumption while continuing to shrink the size.
  • the source and drain of FinFET currently have problems with poor contact performance and poor conductivity.
  • the present disclosure provides a thin film transistor and a preparation method thereof, a memory and a display, and solves the technical problems of how to further reduce the size of the transistor, reduce the power consumption of the transistor, and improve the contact performance and conductive performance of the transistor.
  • the present disclosure provides a thin film transistor, including: a second source-drain layer, an insulating layer, and a first source-drain layer that are stacked in sequence; a gate electrode and a channel layer surrounding the gate electrode, located at the within the first source and drain layer and the insulating layer; the channel layer is in contact with the first source and drain layer and the second source and drain layer; wherein the first source and drain layer includes a first metal layer and a second metal layer, the first metal layer is close to the insulating layer, and the second metal layer is away from the insulating layer; the material of the first metal layer is a metal with a work function lower than molybdenum; the third metal layer is close to the insulating layer.
  • the material of the second metal layer is a metal with a conductivity higher than 3 ⁇ 10 6 S/m and an oxidation resistance not lower than that of molybdenum.
  • the present disclosure provides a method for manufacturing a thin film transistor, including: providing a substrate;
  • a second source-drain layer, an insulating layer and a first source-drain layer are sequentially formed on the substrate; wherein the first source-drain layer includes a first metal layer and a second metal layer, and the first metal layer forms On the insulating layer, the second metal layer is formed on the first metal layer; the material of the first metal layer is a metal with a work function lower than molybdenum; the material of the second metal layer is conductive Metals with a rate higher than 3 ⁇ 10 6 S/m and an antioxidant performance not lower than molybdenum;
  • Gate material is deposited on the channel layer to form a gate electrode.
  • the present disclosure provides a memory including a plurality of memory arrays, the memory arrays including the thin film transistors provided in the first aspect.
  • the present disclosure provides a display, which includes a pixel circuit including the thin film transistor provided in the first aspect.
  • the present disclosure provides a thin film transistor, the gate of which passes through the first source-drain layer and the insulating layer, and the annular channel is arranged around the gate, forming a Channel All Around with an annular channel arranged around the gate, which is a transistor with a CAA architecture for short.
  • the CAA architecture transistor of the present disclosure has: first, compared with the planar channel structure, the vertical channel structure reduces the horizontal area occupation of the electrode by stacking the source/drain electrodes, and can Significantly reducing the size of the transistor is conducive to reducing the device unit density; the channel length is determined by the thickness of the insulating layer, and the shrinkage of the channel length is not limited by the photolithography process, which is conducive to achieving a smaller channel length, thereby improving the channel length.
  • the channel width to length ratio achieves greater device current and reduces power consumption;
  • the CAA architecture with an annular channel surrounding the gate can greatly increase the contact area between the gate and the channel, thus significantly enhancing the gate
  • the gate control capability of the pole to channel improves the current conduction efficiency;
  • the CAA architecture also has a larger contact between the gate and the channel area;
  • adopt a layered structure for the first source and drain layer of the thin film transistor in which the first metal layer close to the insulating layer uses a metal with a lower work function to improve the contact performance; because metals with a lower work function usually resist
  • the oxidation ability is weak, so the second metal layer far away from the insulating layer uses a metal with better conductivity and better oxidation resistance. This protects the first metal layer from oxidation and does not reduce the contact performance while reducing the source and drain electrodes.
  • the resistance of the metal leads, thereby improving the conductivity of the transistor.
  • Figure 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a thin film transistor including a third metal layer according to an embodiment of the present disclosure
  • Figure 3 is a schematic flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • Figure 4 is a schematic diagram of a storage array according to an embodiment of the present disclosure.
  • First source and drain layer 11. First metal layer; 12. Second metal layer; 13. Third metal layer; 2. Second source and drain layer; 21. Fourth metal layer; 22. Fifth metal layer ; 23. Sixth metal layer; 3. Insulating layer; 4. Channel layer; 5. Gate electrode; 6. Gate dielectric layer; 71. First thin film transistor; 72. Second thin film transistor.
  • horizontal does not imply a requirement that the component be absolutely horizontal or overhanging, but may be slightly tilted.
  • “horizontal” only means that its direction is more horizontal than “vertical”. It does not mean that the structure must be completely horizontal, but can be slightly tilted.
  • the present disclosure provides a thin film transistor TFT (Thin Film Transistor), whose structure is shown in Figure 1 and includes:
  • the second source and drain layer 2, the insulating layer 3 and the first source and drain layer 1 are stacked in sequence;
  • the gate electrode 5 and the channel layer 4 surrounding the gate electrode 5 are located in the first source-drain layer 1 and the insulating layer 3; the channel layer 4 is in contact with the first source-drain layer 1 and the second source-drain layer 2.
  • the TFT transistor provided in this embodiment has a vertical channel structure.
  • the first source and drain layer 1 can be regarded as the upper source and drain of the TFT, and the second source and drain layer 2 can be regarded as the lower source of the TFT. drain.
  • the first source and drain layer 1 can be prepared as a source electrode, and the second source and drain layer 2 can be prepared as a drain electrode, or the first source and drain layer 1 can be prepared as a drain electrode, and the second source and drain layer 2 can be prepared as a drain electrode.
  • the source there is no specific limitation on this.
  • the gate electrode 5 has a vertical structure, and the bottom of the gate electrode 5 at least penetrates the first source and drain layer 1 and enters the insulating layer 3 .
  • the bottom of the gate electrode 5 can also penetrate the insulating layer 3 and enter the second source and drain layer 2 .
  • the shape of the grid electrode 5 can be cylindrical, and its cross-sectional shape can be circular, elliptical, or polygonal; the shape of the grid electrode 5 can also be annular, and its cross-sectional shape can be a circular ring, an elliptical ring, or a polygonal ring. , can be determined according to actual needs.
  • the optional materials of the gate 5 include: indium tin oxide (ITO, Indium Tin Oxide), indium zinc oxide (IZO, Indium Zinc Oxide) or titanium nitride (TiN).
  • a better shape of the channel layer is to select the shape with the largest cross-sectional circumference under the premise that the cross-sectional area of the channel layer 4 remains unchanged. This can increase the channel width of the channel layer 4, thereby further improving the channel width.
  • the width-to-length ratio is beneficial to increasing the saturation current of thin film transistors.
  • the material of the channel layer 4 may be indium gallium zinc oxide IGZO (Indium Gallium Zinc Oxide).
  • the vertical channel structure reduces the horizontal area occupied by the electrodes by stacking the source/drain electrodes, which can significantly reduce the size of the transistor and help reduce the device unit density;
  • the channel length is Determined by the thickness of the insulating layer 3, the shrinkage of the channel length is not limited by the photolithography process, which is conducive to achieving a smaller channel length, thus increasing the channel width-to-length ratio, achieving greater device current and reducing power consumption;
  • the first source and drain layer 1 includes a first metal layer 11 and a second metal layer 12.
  • the first metal layer 11 is close to the insulating layer 3, and the second metal layer 12 is far away from the insulating layer 3.
  • the material of the first metal layer 11 has a low work function.
  • a metal based on molybdenum; the second metal layer 12 is made of a metal with a conductivity higher than 3 ⁇ 10 6 S/m (Siemens/meter) and an oxidation resistance not lower than that of molybdenum.
  • the CAA transistor in this embodiment uses different metals to form source and drain electrodes in layers, and has the following characteristics:
  • the first metal layer 11 close to the insulating layer 3 uses a metal with a lower work function to obtain better contact performance; since metal with a lower work function usually has weak oxidation resistance, it is far away from the insulating layer 3 and close to the top
  • the second metal layer 12 in the channel area is made of metal with better conductivity and better oxidation resistance, which protects the first metal layer 11 from being oxidized and does not reduce the contact performance, while reducing the resistance of the source and drain metal leads. , improve the conductive performance of the transistor.
  • first source and drain layer 1 When forming the first source and drain layer 1 in layers, the following two options can be adopted for the optional materials and thickness ratios of the first metal layer 11 and the second metal layer 12:
  • Option 1 The ratio of the thickness of the first metal layer 11 to the second metal layer 12 is not less than 10, and the total thickness of the first metal layer 11 and the second metal layer 12 is not less than 50 nm.
  • the first metal layer 11 close to the insulating layer 3 selects metals with lower work function and higher conductivity, such as Ti and W, so as to obtain good contact performance and high conductivity.
  • the second metal layer 12 is formed on the upper surface of the first metal layer 11 , and a metal with strong oxidation resistance, such as Ag and Au, is selected to prevent the first metal layer 11 with weak oxidation resistance from being oxidized. Since it only serves to prevent oxidation, the second metal layer 12 is thin.
  • a metal with strong oxidation resistance such as Ag and Au
  • the transistor can have better contact performance, conductive performance and oxidation resistance at the same time.
  • Option 2 The ratio of the thickness of the first metal layer 11 to the second metal layer 12 is 0.9-1.1, and the total thickness of the first metal layer 11 and the second metal layer 12 is not less than 50 nm.
  • the material of the first metal layer 11 is titanium (Ti) or tungsten (W), and the material of the second metal layer 12 is molybdenum (Mo) or titanium nitride (TiN).
  • the first source and drain layer 1 also includes a third metal layer 13 , and the third metal layer 13 is located between the first metal layer 11 and the insulating layer 3 ;
  • the material is a metal with an oxidation resistance no less than molybdenum.
  • the first metal layer 11, the second metal layer 12 and the third metal layer 13 form the first source and drain layer 1 of a three-layer sandwich structure.
  • the second metal layer 12 is the top layer, and metals such as Mo, TiN, Au, and Ag can be selected to avoid the deterioration of contact performance and increase in metal wiring resistance caused by oxidation of the top of the first source and drain layer 1;
  • first The metal layer 11 serves as an intermediate layer or a sandwich layer, and a metal with a lower work function, such as Ti or W, can be selected to further improve the contact performance between the channel layer 4 and the first source and drain layer 1;
  • the third metal layer 13 is close to
  • the insulating layer 3 is the bottom layer, and metals such as Mo, TiN, Au, and Ag can be selected to protect the bottom of the first source and drain layer 1 from being oxidized and to avoid deterioration of contact performance and increase in metal wiring resistance.
  • the second source and drain layer 2 can also adopt the same layered configuration.
  • the second source and drain layer 2 includes a fourth metal layer 21 , a fifth metal layer 22 and a sixth metal layer 23 ; the fourth metal layer 21 is close to the insulating layer 3 , and the fifth metal layer 21 is close to the insulating layer 3 .
  • Layer 22 is away from the insulating layer 3; the sixth metal layer 23 is located between the fourth metal layer 21 and the insulating layer 3.
  • the fifth metal layer 22 is the bottom layer of the second source and drain layer 2, and metals such as Mo, TiN, Au, and Ag can be selected to avoid the deterioration of contact performance and metal damage caused by oxidation of the bottom of the second source and drain layer 2.
  • the wiring resistance increases; the fourth metal layer 21 is the middle layer or sandwich layer of the second source and drain layer 2.
  • a metal with a lower work function can be selected, such as Ti or W, thereby further improving the connection between the channel layer 4 and the second source layer 2.
  • Contact performance between drain layers 2; the sixth metal layer 23 is close to the insulating layer 3 and is the top layer of the second source and drain layer 2.
  • Metals such as Mo, TiN, Au, and Ag can be selected to protect the second source and drain layer 2. The top is not oxidized to avoid poor contact performance and increased metal trace resistance.
  • the bottom of the gate 5 is located in the fourth metal layer 21, and the material of the fourth metal layer 21 is a metal with a lower work function than molybdenum.
  • the present disclosure provides a method for preparing a thin film transistor, including steps S301 to S305, specifically as follows:
  • S301 Provide substrate; silicon substrate can be used;
  • S302 Form the second source and drain layer 2, the insulating layer 3 and the first source and drain layer 1 in sequence on the substrate; wherein the first source and drain layer 1 includes the first metal layer 11 and the second metal layer 12, and the first metal layer 1 Layer 11 is formed on the insulating layer 3, and the second metal layer 12 is formed on the first metal layer 11; the material of the first metal layer 11 is a metal with a lower work function than molybdenum; the material of the second metal layer 12 is high conductivity. Metals with an antioxidant capacity of no less than 3 ⁇ 10 6 S/m and no less than molybdenum;
  • the fifth metal layer 22 such as Mo, TiN, Au, Metals such as Ag are deposited on the second layer
  • the material of the fourth metal layer 21 is deposited, such as Ti or W
  • the material of the sixth metal layer 23 is deposited on the third layer, such as Mo, TiN, Au, Ag and other metals.
  • a double protective layer is deposited on the source and drain metal material layer, which can be a double protective layer formed of SiN and SiO.
  • the thickness of the double layer protective layer is about 200nm.
  • photolithography of the source and drain metal material layer is performed. Specifically, The second source and drain layer 2 is formed by covering the double-layer protective layer with photoresist and then sequentially exposing, developing, and etching;
  • a filling oxide layer is deposited on the second source and drain layer 2, and then chemical mechanical polishing and cleaning are performed.
  • the insulating layer material is deposited to form the insulating layer 3;
  • the first source and drain layer metal is deposited on the insulating layer 3, using the same layered deposition method: the material of the third metal layer 13 is first deposited on the first layer, such as Mo, TiN, Au, Ag and other metals; The material of the first metal layer 11 is then deposited, such as Ti or W; the third layer is then deposited with the material of the second metal layer 12, such as Mo, TiN, Au, Ag and other metals; then double protective layer deposition and coverage photolithography are performed in sequence. glue, exposure, development, etching, and cleaning to form the first source and drain layer 1.
  • the material of the third metal layer 13 is first deposited on the first layer, such as Mo, TiN, Au, Ag and other metals
  • the material of the first metal layer 11 is then deposited, such as Ti or W
  • the third layer is then deposited with the material of the second metal layer 12, such as Mo, TiN, Au, Ag and other metals
  • double protective layer deposition and coverage photolithography are performed in sequence. glue, exposure, development,
  • S303 Form a hole extending to the second source-drain layer 2 in the first source-drain layer 1 and the insulating layer 3; a deep etching method can be used to form the required hole, specifically as follows:
  • a leveling oxide is deposited on the first source and drain layer 1 again, and then chemical mechanical polishing and cleaning are performed, and the polishing position stays on the leveling oxide layer;
  • Form a through hole deposit a double protective layer (SiN+SiO) at the location where the through hole is to be formed, then cover it with photoresist, and perform exposure, development, etching, cleaning and chemical mechanical polishing to form the bottom to the first Source and drain layer 1, the bottom reaches the through hole of the second source and drain layer 2;
  • a double protective layer SiN+SiO
  • Form the channel hole deposit a double protective layer (SiN+SiO) at the location where the channel hole is to be formed, then cover it with photoresist, align it with the first source and drain layer 1, and then perform exposure, development, etching and cleaning.
  • a channel hole is formed that penetrates the first source and drain layer 1 and the insulating layer 3 and has a bottom that reaches the second source and drain layer 2 .
  • S304 Deposit channel material on the inner wall of the hole and the surface of the first source and drain layer 1 to form the channel layer 4;
  • S305 Deposit the gate material on the channel layer 4 to form the gate 5.
  • the gate dielectric material is first deposited to form the gate dielectric layer 6 , and then the gate material is deposited on the surface of the gate dielectric layer 7 .
  • the method of depositing the channel material, the gate material and the gate dielectric material in the channel hole may be atomic layer deposition.
  • the present disclosure provides a memory.
  • the memory includes a plurality of memory arrays, and the memory arrays include the thin film transistors provided in the first aspect.
  • FIG. 4 shows an optional 2T0C memory array structure.
  • a memory array includes two provided by embodiments of the present disclosure: a first thin film transistor 71 and a second thin film transistor 72, wherein the first thin film transistor 71 The gate is electrically connected to the write word line WWL, the source is electrically connected to the write bit line WBL, the drain is electrically connected to the gate of the second thin film transistor 72 , the source of the second thin film transistor 72 is electrically connected to the read word line RWL, and the drain is electrically connected to the read bit line RBL.
  • the gate of one TFT transistor can be directly connected to the source and drain of another TFT transistor without the need for external leads. Therefore, the entire memory can be greatly reduced. volume, which is conducive to further miniaturization of memory.
  • the thin film transistor provided by the embodiment of the present disclosure can also be applied to 1T0C, 1T1C, and 2T1C memory arrays, which are not specifically limited here.
  • the present disclosure provides a display.
  • the display includes a pixel circuit, and the pixel circuit includes the thin film transistor provided in the first aspect.
  • the present disclosure has the following beneficial effects or advantages:
  • the present disclosure provides a thin film transistor, a memory and a display; wherein the gate of the thin film transistor passes through the first source-drain layer and the insulating layer, and an annular channel is arranged around the gate, forming a Channel All Around with an annular channel arranged around the gate. , referred to as CAA architecture transistor.
  • the CAA architecture transistor of the present disclosure has: first, compared with the planar channel structure, the vertical channel structure reduces the horizontal area occupation of the electrode by stacking the source/drain electrodes, and can Significantly reducing the size of the transistor is conducive to reducing the device unit density; the channel length is determined by the thickness of the insulating layer, and the shrinkage of the channel length is not limited by the photolithography process, which is conducive to achieving a smaller channel length, thereby improving the channel length.
  • the channel width to length ratio achieves greater device current and reduces power consumption;
  • the CAA architecture with an annular channel surrounding the gate can greatly increase the contact area between the gate and the channel, thus significantly enhancing the gate
  • the gate control capability of the pole to channel improves the current conduction efficiency;
  • the CAA architecture also has a larger contact between the gate and the channel area;
  • adopt a layered structure for the first source and drain layer of the thin film transistor in which the first metal layer close to the insulating layer uses a metal with a lower work function to improve the contact performance; because metals with a lower work function usually resist
  • the oxidation ability is weak, so the second metal layer far away from the insulating layer uses a metal with better conductivity and better oxidation resistance. This protects the first metal layer from oxidation and does not reduce the contact performance while reducing the source and drain electrodes.
  • the resistance of the metal leads, thereby improving the conductivity of the transistor.

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Abstract

本文公开了一种薄膜晶体管及其制备方法、存储器和显示器，其中的薄膜晶体管包括依次层叠设置的第二源漏层(2)、绝缘层(3)和第一源漏层(1)；栅极(5)和环绕所述栅极(5)的沟道层(4)，位于所述第一源漏层(1)和所述绝缘层(3)内；所述沟道层(4)与所述第一源漏层(1)和所述第二源漏层(2)接触；所述第一源漏层(1)包括第一金属层(11)和第二金属层(12)，所述第一金属层(11)靠近所述绝缘层(3)，所述第二金属层(12)远离所述绝缘层(3)；所述第一金属层(11)的材质为功函数低于钼的金属；所述第二金属层(12)的材质为导电率高于3×10 6S/m，且抗氧化性能不低于钼的金属。所述CAA架构的薄膜晶体管能够缩小晶体管尺寸、降低晶体管的功耗并提高晶体管的接触性能和导电性能。

Description

薄膜晶体管及其制备方法、存储器和显示器
相关申请的交叉引用
本申请要求于2022年6月10日提交、申请号为202210656607.X且名称为“薄膜晶体管及其制备方法、存储器和显示器”的中国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开内容涉及一种薄膜晶体管及其制备方法、存储器和显示器。
背景技术
根据摩尔定律，集成电路不断向更细微尺寸发展，而先进制程则是集成电路制造中最为顶尖的节点之一。目前，先进制程已发展至5/7nm节点，这对晶体管的进一步微型化提出了极高的要求。
目前晶体管的一个关键架构：鳍式场效应晶体管(Fin Field Effect Transistor，简称FinFET)的设计可以大幅改善电路控制并减少漏电流(leakage)，同时大幅缩短晶体管的栅长。但是FinFET架构主要适用于10～22nm的制程，对于10nm以下，如7nm，5nm，3nm的制程，则会受到FinFET宽度缩放的限制，无法在继续缩小尺寸的同时保证高性能和低功耗。另一方面，目前FinFET的源漏极还存在接触性能较差，导电性能较差的问题。
因此，如何进一步缩小晶体管尺寸、降低晶体管的功耗、提高晶体管的接触性能和导电性能，满足先进制程：高性能、低功耗的要求，成为目前亟需解决的问题。
发明内容
本公开提供了一种薄膜晶体管及其制备方法、存储器和显示器，解决了如何进一步缩小晶体管尺寸、降低晶体管的功耗、提高晶体管的接触性能和导电性能的技术问题。
在第一方面，本公开提供了一种薄膜晶体管，包括：依次层叠设置的第二源漏层、绝缘层和第一源漏层；栅极和环绕所述栅极的沟道层，位于所 述第一源漏层和所述绝缘层内；所述沟道层与所述第一源漏层和所述第二源漏层接触；其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层靠近所述绝缘层，所述第二金属层远离所述绝缘层；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×10 6S/m，且抗氧化性能不低于钼的金属。
在第二方面，本公开提供了一种薄膜晶体管的制备方法，包括：提供衬底；
在所述衬底上依次形成第二源漏层、绝缘层和第一源漏层；其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层形成在所述绝缘层上，所述第二金属层形成在所述第一金属层上；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×10 6S/m，且抗氧化性能不低于钼的金属；
在所述第一源漏层和所述绝缘层内形成延伸至所述第二源漏层的孔；
在所述孔的内壁和所述第一源漏层的表面沉积沟道材料，形成沟道层；
在所述沟道层上沉积栅极材料，形成栅极。
第三方面，本公开提供了一种存储器，所述存储器包括多个存储阵列，所述存储阵列包括第一方面提供的薄膜晶体管。
第四方面，本公开提供了一种显示器，所述显示器包括像素电路，所述像素电路包括第一方面提供的薄膜晶体管。
本公开提供了一种薄膜晶体管，其栅极下穿第一源漏层和绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极设置的Channel All Around，简称CAA架构的晶体管。本公开的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶 体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，对薄膜晶体管的第一源漏层采用分层结构，其中靠近绝缘层的第一金属层采用功函数较低的金属，以提高接触性能；由于功函数较低的金属通常抗氧化能力较弱，因此远离绝缘层的第二金属层采用导电能力更佳，抗氧化性能更好的金属，在保护第一金属层不被氧化，不降低接触性能的同时，减小源漏极金属引线的电阻，从而提高晶体管的导电性能。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
图1为根据本公开实施例的薄膜晶体管的结构示意图；
图2为根据本公开实施例的包括第三金属层的薄膜晶体管的结构示意图；
图3为根据本公开实施例的薄膜晶体管的制备方法流程示意图；
图4为根据本公开实施例的存储阵列示意图；
附图标记说明：
1、第一源漏层；11、第一金属层；12、第二金属层；13、第三金属层；2、第二源漏层；21、第四金属层；22、第五金属层；23、第六金属层；3、绝缘层；4、沟道层；5、栅极；6、栅介质层；71、第一薄膜晶体管；72、第二薄膜晶体管。
具体实施方式
为了使本公开所属技术领域中的技术人员更清楚地理解本公开，下面结合附图，通过具体实施例对本公开技术方案作详细描述。在整个说明书中，除非另有特别说明，本文使用的术语应理解为如本领域中通常所使用的含义。因此，除非另有定义，本文使用的所有技术和科学术语具有与本公开所属领域技术人员的一般理解相同的含义。若存在矛盾，本说明书优先。除非另有特别说明，本公开中用到的各种设备等，均可通过市场购买得到或者可通过 现有方法制备得到。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
此外，术语“水平”、“竖直”、“悬垂”等术语并不表示要求部件绝对水平或悬垂，而是可以稍微倾斜。如“水平”仅仅是指其方向相对“竖直”而言更加水平，并不是表示该结构一定要完全水平，而是可以稍微倾斜。
研究表明，晶体管的源漏极存在接触性能较差，导电性能较差的原因为：源漏极金属为了保证耐用性，采用的抗氧化性能较好，但功函数较高的金属，如钼(Mo)和氮化钛(TiN)，但功函数高则存在接触性能和导电性能变差的问题。而功函数较低的金属，如钛(Ti)，钨(W)能够提高接触性能和导电性能，但又容易被氧化，氧化之后接触性能仍然会变差，同时金属电阻增大。
在第一方面，本公开提供了一种薄膜晶体管TFT(Thin Film Transistor)，其结构参阅图1，包括：
依次层叠设置的第二源漏层2、绝缘层3和第一源漏层1；
栅极5和环绕栅极5的沟道层4，位于第一源漏层1和绝缘层3内；沟道层4与第一源漏层1和第二源漏层2接触。
具体的，本实施例提供的TFT晶体管为垂直沟道结构，为了方便理解，可以将第一源漏层1视为TFT的上层源漏极，将第二源漏层2视为TFT的下层源漏极。在实际使用时，第一源漏层1可以制备成源极，第二源漏层2可以制备为漏极，也可以将第一源漏层1制备成漏极，第二源漏层2制备为源极，对此不进行具体限定。
栅极5为垂直结构，栅极5的底部至少穿透第一源漏层1并进入绝缘层3。栅极5的底部还可以穿透绝缘层3进入第二源漏层2。栅极5的形状可 以是柱形的，其横截面形状可以是圆形，椭圆形或多边形；栅极5的形状还可以是环形的，其横截面形状可以是圆环，椭圆环或多边形环，可根据实际需求确定。栅极5的可选材质有：氧化铟锡(ITO，Indium Tin Oxide)，氧化铟锌(IZO，Indium Zinc Oxide)或氮化钛(TiN)。
沟道层4为垂直沟道结构，环绕第一源漏层1和绝缘层3内的栅极5部分形成。因此，本实施例的TFT晶体管属于垂直沟道全环绕栅极的CAA(Channel All Around)架构。沟道层4的横截面形状可以是圆形，椭圆形或多边形的，沟道层4的横截面形状可以与栅极5的横截面形状相同或不同。
一个较佳的沟道层形状是在沟道层4的横截面面积不变的前提下，选择横截面周长最大的形状，如此能够提高沟道层4的沟道宽度，从而进一步提高沟道宽长比，有利于提高薄膜晶体管的饱和电流。
沟道层4的材质可以是氧化铟镓锌IGZO(Indium Gallium Zinc Oxide)。
在一些实施例中，薄膜晶体管还包括栅介质层6，栅介质层6位于栅极5层和沟道层4之间。栅介质层6的可选材质包括：氧化铪、铪铝氧化物和三氧化二铝中的至少一种。
本实施例的CAA架构的晶体管相比于FinFET架构的晶体管，具有如下的特点：
1)垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层3的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；
2)通过环形沟道环绕栅极5的CAA架构，能够极大的增加栅极5和沟道层4之间的接触面积，从而显著增强栅极5对沟道层4的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极5全向场效应晶体管)架构，CAA架构也具有更大的栅极5与沟道层4之间的接触面积。
同时，为了解决目前晶体管的源漏极存在接触性能较差，导电性能较差的问题，本实施例提供的TFT晶体管，其对第一源漏层1采用了分层结构，具体如下：
第一源漏层1包括第一金属层11和第二金属层12，第一金属层11靠近绝缘层3，第二金属层12远离绝缘层3；第一金属层11的材质为功函数低于钼的金属；第二金属层12的材质为导电率高于3×10 6S/m(西门子/米)，且抗氧化性能不低于钼的金属。
相比于FinFET架构的晶体管，本实施例的CAA晶体管，通过采用不同的金属，分层形成源漏极后，还具有如下的特点：
3)靠近绝缘层3的第一金属层11采用功函数较低的金属，能够获得更好的接触性能；由于功函数较低的金属通常抗氧化能力较弱，因此远离绝缘层3、靠近顶部沟道区的第二金属层12采用导电能力更佳，抗氧化性能更好的金属，在保护第一金属层11不被氧化，不降低接触性能的同时，减小源漏极金属引线的电阻，提高晶体管的导电性能。
在分层形成第一源漏层1时，第一金属层11和第二金属层12的可选材质和厚度配比可采用如下两种方案：
方案一、第一金属层11与第二金属层12的厚度之比不低于10，第一金属层11和第二金属层12的总厚度不低于50nm。
与方案一对应的，第一金属层11的可选材质为钛(Ti)或钨(W)，第二金属层12的可选材质为银(Ag)或金(Au)。
具体的，靠近绝缘层3的第一金属层11选择功函数较低、导电率较高的金属，如Ti和W，从而获得良好的接触性能和高电导能力，为了保证接触性能和导电性能，第一金属层11越厚越好。
第二金属层12形成在第一金属层11的上表面，选择抗氧化性较强的金属，如Ag和Au，以防止抗氧化能力弱的第一金属层11被氧化。由于只起到防氧化的作用，因此第二金属层12较薄。
通过方案一中的第一金属层11和第二金属层12之间的材质和厚度配置，能够使晶体管同时具备更佳的接触性能、导电性能和抗氧化性能。
方案二、第一金属层11与第二金属层12的厚度之比为0.9～1.1，第一金属层11和第二金属层12的总厚度不低于50nm。
与之对应的，第一金属层11的材质为钛(Ti)或钨(W)，第二金属层12的材质为钼(Mo)或氮化钛(TiN)。
具体的，第一金属层11选择功函数低于Mo的金属，如Ti、W等金属，从而保证第一源漏层1与半导体，即沟道层4之间具有更佳的接触性能，可采用较厚的厚度；而第二金属层12需要同时具备较低的功函数、较高的电导和较好的抗氧化性的特点，如采用TiN、Mo等，越厚越好。因此在方案二中第一金属层11和第二金属层12两者的厚度相当，如此可以同时获得高电导率和低接触电阻的特性。
在一些实施例中，如图2所示，第一源漏层1还包括第三金属层13，第三金属层13位于第一金属层11和绝缘层3之间；第三金属层13的材质为抗氧化性能不低于钼的金属。
至此，第一金属层11、第二金属层12和第三金属层13形成了一种三层夹心结构的第一源漏层1。其中，第二金属层12为顶层，可选择Mo、TiN、Au、Ag等金属，避免第一源漏层1的顶部被氧化所导致的接触性能变差和金属走线电阻升高；第一金属层11作为中间层或夹心层，可选择功函数较低的金属，如Ti或W，从而进一步提高沟道层4与第一源漏层1之间的接触性能；第三金属层13靠近绝缘层3为底层，可选择Mo、TiN、Au、Ag等金属，是为了保护第一源漏层1的底部不被氧化，避免接触性能变差和金属走线电阻升高。
与第一源漏层1的分层形成同理，第二源漏层2也可以采用相同的分层配置。在一些实施例中，如图2所示，第二源漏层2包括第四金属层21、第五金属层22和第六金属层23；第四金属层21靠近绝缘层3，第五金属层22远离绝缘层3；第六金属层23位于第四金属层21和绝缘层3之间。
具体的，第五金属层22为第二源漏层2的底层，可选择Mo、TiN、Au、Ag等金属，避免第二源漏层2的底部被氧化所导致的接触性能变差和金属走线电阻升高；第四金属层21为第二源漏层2的中间层或夹心层，可选择功函数较低的金属，如Ti或W，从而进一步提高沟道层4与第二源漏层2之间的接触性能；第六金属层23靠近绝缘层3为第二源漏层2的顶层，可选择Mo、TiN、Au、Ag等金属，是为了保护第二源漏层2的顶部不被氧化，避免接触性能变差和金属走线电阻升高。
进一步的，如图2所示，栅极5的底部位于第四金属层21内，第四金 属层21的材质为功函数低于钼的金属。通过使用功函数低的第四金属层21包裹栅极5和沟道层4的底部，能够进一步提高接触性能。
第二方面，如图3所示，本公开提供了一种薄膜晶体管的制备方法，包括步骤S301～S305，具体如下：
S301：提供衬底；可使用硅衬底；
S302：在衬底上依次形成第二源漏层2、绝缘层3和第一源漏层1；其中，第一源漏层1包括第一金属层11和第二金属层12，第一金属层11形成在绝缘层3上，第二金属层12形成在第一金属层11上；第一金属层11的材质为功函数低于钼的金属；第二金属层12的材质为导电率高于3×10 6S/m，且抗氧化性能不低于钼的金属；
具体的，可先在衬底上沉积预氧化层，厚度为300～400nm，沉积完成后进行预清洗，然后在预氧化层上沉积形成第二源漏层2的金属材料层，具体如下：
对预氧化层进行预清洗；在预清洗后的预氧化层上沉积源漏金属材料；采用分层沉积的方式：第一层先沉积第五金属层22的材料，如Mo、TiN、Au、Ag等金属；第二层再沉积第四金属层21的材料，如Ti或W；第三层再沉积第六金属层23的材料，如Mo、TiN、Au、Ag等金属。
接着在源漏金属材料层上进行双保护层沉积，可以是SiN和SiO形成的双层保护层，双层保护层的厚度约为200nm；接下来再进行源漏金属材料层的光刻，具体是在双层保护层上覆盖光刻胶后依次进行曝光、显影、刻蚀形成第二源漏层2；
接着，在第二源漏层2上进行填平氧化层沉积，然后再进行化学机械抛光、清洗，完成后沉积绝缘层材料形成绝缘层3；
接着，在绝缘层3上沉积第一源漏层金属，同样采用分层沉积的方式：第一层先沉积第三金属层13的材料，如Mo、TiN、Au、Ag等金属；第二层再沉积第一金属层11的材料，如Ti或W；第三层再沉积第二金属层12的材料，如Mo、TiN、Au、Ag等金属；然后依次进行双保护层沉积、覆盖光刻胶、曝光、显影、刻蚀、清洗形成第一源漏层1。
S303：在第一源漏层1和绝缘层3内形成延伸至第二源漏层2的孔； 可采用深刻刻蚀方法形成所需的孔，具体如下：
在第一源漏层1上再次进行填平氧化物沉积，然后进行化学机械抛光、清洗，抛光位置停留在填平氧化层上；
形成通孔：在要形成通孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，并进行曝光、显影、刻蚀、清洗和化学机械抛光，分别形成底部到达第一源漏层1、底部到达第二源漏层2的通孔；
形成沟道孔：在要形成沟道孔的位置处进行双保护层(SiN+SiO)沉积，然后覆盖光刻胶，对准第一源漏层1后进行曝光、显影、刻蚀并清洗，形成穿透第一源漏层1和绝缘层3，且底部到达第二源漏层2的沟道孔。
S304：在孔的内壁和第一源漏层1的表面沉积沟道材料，形成沟道层4；
S305：在沟道层4上沉积栅极材料，形成栅极5。
在一些实施例中，在沉积沟道材料后，先沉积栅介质材料以形成栅介质层6，然后在栅介质层7的表面沉积栅极材料。
在沟道孔内沉积沟道材料、栅极材料和栅介质材料的方法均可以是原子层沉积。
第三方面，本公开提供了一种存储器，存储器包括多个存储阵列，存储阵列包括第一方面提供的薄膜晶体管。
图4示出了一种可选的2T0C的存储阵列结构，一个存储阵列中包括两个本公开实施例提供的：第一薄膜晶体管71和第二薄膜晶体管72，其中，第一薄膜晶体管71的栅极电连接写字线WWL，源极电连接写位线WBL，漏极电连接第二薄膜晶体管72的栅极，第二薄膜晶体管72的源极电连接读字线RWL，漏极电连接读位线RBL。
将本公开实施例提供的薄膜晶体管应用于2T0C的存储电路，可以将一个TFT晶体管的栅极与另一个TFT晶体管的源漏极直接连接，无需要外接引线，因此可以极大的缩小整个存储器的体积，有利于进一步实现存储器的小型化。
另外，本公开实施例提供的薄膜晶体管还可以应用到1T0C，1T1C，2T1C的存储阵列，在此不进行具体限定。
第四方面，本公开提供了一种显示器，显示器包括像素电路，像素电 路包括第一方面提供的薄膜晶体管。
通过本公开的一个或者多个实施例，本公开具有以下有益效果或者优点：
本公开提供了一种薄膜晶体管、存储器及显示器；其中薄膜晶体管的栅极下穿第一源漏层和绝缘层，环形沟道环绕栅极设置，形成环形沟道环绕栅极设置的Channel All Around，简称CAA架构的晶体管。本公开的CAA架构的晶体管相比于FinFET架构的晶体管，具有：第一，垂直沟道结构相对于平面沟道结构，通过将源/漏极堆叠起来，减小了电极的水平面积占用，能够显著缩小晶体管的尺寸，有利于减小器件单元密度；沟道长度由绝缘层的厚度决定，沟道长度的微缩不受光刻工艺的限制，有利于实现更小的沟道长度，从而提高沟道宽长比，实现更大的器件电流并降低功耗；第二，通过环形沟道环绕栅极的CAA架构，能够极大的增加栅极和沟道之间的接触面积，从而显著增强栅极对沟道的栅控能力，提高了电流传导效率；且相对于GAA(Gate All Around，栅极全向场效应晶体管)架构，CAA架构也具有更大的栅极与沟道之间的接触面积；第三，对薄膜晶体管的第一源漏层采用分层结构，其中靠近绝缘层的第一金属层采用功函数较低的金属，以提高接触性能；由于功函数较低的金属通常抗氧化能力较弱，因此远离绝缘层的第二金属层采用导电能力更佳，抗氧化性能更好的金属，在保护第一金属层不被氧化，不降低接触性能的同时，减小源漏极金属引线的电阻，从而提高晶体管的导电性能。
尽管已描述了本公开的优选实施例，但本领域内的普通技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种薄膜晶体管，包括：
    依次层叠设置的第二源漏层、绝缘层和第一源漏层；
    栅极和环绕所述栅极的沟道层，位于所述第一源漏层和所述绝缘层内；所述沟道层与所述第一源漏层和所述第二源漏层接触；
    其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层靠近所述绝缘层，所述第二金属层远离所述绝缘层；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×10 6S/m，且抗氧化性能不低于钼的金属。
  2. 如权利要求1所述的薄膜晶体管，其中，所述第一金属层与所述第二金属层的厚度之比不低于10，所述第一金属层和所述第二金属层的总厚度不低于50nm。
  3. 如权利要求2所述的薄膜晶体管，其中，所述第一金属层的材质为钛或钨，所述第二金属层的材质为银或金。
  4. 如权利要求1所述的薄膜晶体管，其中，所述第一金属层与所述第二金属层的厚度之比为0.9～1.1，所述第一金属层和所述第二金属层的总厚度不低于50nm。
  5. 如权利要求4所述的薄膜晶体管，其中，所述第一金属层的材质为钛或钨，所述第二金属层的材质为钼或氮化钛。
  6. 如权利要求1所述的薄膜晶体管，其中，所述第一源漏层还包括第三金属层，所述第三金属层位于所述第一金属层和所述绝缘层之间；所述第三金属层的材质为抗氧化性能不低于钼的金属。
  7. 如权利要求1所述的薄膜晶体管，其中，所述第二源漏层包括第四金属层、第五金属层和第六金属层；所述第四金属层靠近所述绝缘层，所述第五金属层远离所述绝缘层；所述第六金属层位于所述第四金属层和所述绝缘 层之间。
  8. 一种薄膜晶体管的制备方法，包括：
    提供衬底；
    在所述衬底上依次形成第二源漏层、绝缘层和第一源漏层；其中，所述第一源漏层包括第一金属层和第二金属层，所述第一金属层形成在所述绝缘层上，所述第二金属层形成在所述第一金属层上；所述第一金属层的材质为功函数低于钼的金属；所述第二金属层的材质为导电率高于3×10 6S/m，且抗氧化性能不低于钼的金属；
    在所述第一源漏层和所述绝缘层内形成延伸至所述第二源漏层的孔；
    在所述孔的内壁和所述第一源漏层的表面沉积沟道材料，形成沟道层；
    在所述沟道层上沉积栅极材料，形成栅极。
  9. 一种存储器，包括多个存储阵列，所述存储阵列包括如权利要求1～7中任一项所述的薄膜晶体管。
  10. 一种显示器，包括像素电路，所述像素电路包括如权利要求1～7中任一项所述的薄膜晶体管。
PCT/CN2022/116072 2022-06-10 2022-08-31 薄膜晶体管及其制备方法、存储器和显示器 WO2023236375A1 (zh)

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