CN116798980A - 封装基板及其制法 - Google Patents
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Abstract
一种封装基板及其制法,包括将绝缘层包覆线路层及该线路层上的导电柱,再于该绝缘层对应该导电柱之处形成凹槽,以于该凹槽中形成布线层,故无需钻孔制作盲孔,因而能避免现有线路及导电盲孔的对位问题。
Description
技术领域
本发明有关一种半导体封装技术,尤指一种具嵌埋型线路(Embedded Trace)的封装基板及其制法。
背景技术
随着电子产业的蓬勃发展,电子产品在型态上趋于轻薄短小,在功能上则朝高性能、高功能、高速化的研发方向。因此,为满足半导体装置的高集成度(Integration)及微型化(Miniaturization)需求,故于封装制程中,常常采用具有高密度及细间距的线路的封装基板。
如图1所示,现有封装基板1包含一具有多个导电柱100的核心层10、分别设于该核心层10相对两侧的多个介电层11、及设于各该介电层11上的线路层12,以借由该多个导电柱100电性导通位于该核心层10相对两侧的这些线路层12,其中,该线路层12借由导电盲孔120电性连接该导电柱100。
然而,现有封装基板1中,该导电盲孔120的制作先于该介电层11上以激光、机钻等方式形成孔洞,再于这些孔洞中填入导电材,故于形成该孔洞的过程中,往往因工作误差而偏位,导致该孔洞无法形成于预定之处,使得该导电盲孔120无法有效连接该导电柱100与线路层12,造成该封装基板1的电性连接不佳的问题。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失,本发明提供一种封装基板及其制法,能避免现有线路及导电盲孔的对位问题。
本发明的封装基板,包括:绝缘层,其于其中一侧形成有凹槽;线路层,其嵌埋于该绝缘层的另一侧;导电柱,其嵌埋于该绝缘层中以连接该线路层;以及布线层,其形成于该凹槽中以连接该导电柱。
本发明亦提供一种封装基板的制法,包括:于承载件上依序形成线路层及至少一导电柱;于该承载件上形成绝缘层,以令该绝缘层包覆该线路层及该导电柱;于该绝缘层上形成具有多个镂空区的止挡层,以令该绝缘层的部分表面外露于该镂空区;于该绝缘层对应该镂空区的表面上形成凹槽,以令各该导电柱对应外露于各该凹槽;移除该止挡层;以及于该凹槽中形成布线层。
前述的制法中,该止挡层为金属层。
前述的制法中,还包括于该布线层上进行增层作业。
前述的封装基板及其制法中,还包括于该凹槽中形成该布线层时,一并于该绝缘层上形成遮盖该布线层的对位部。例如,该对位部与该布线层为一体成形。
前述的封装基板及其制法中,该布线层齐平该绝缘层的表面。
由上可知,本发明的封装基板及其制法中,主要借由该绝缘层对应该导电柱之处形成有凹槽,以于该凹槽中形成布线层,故相较于现有技术,本发明无需钻孔制作盲孔,因而能避免现有线路及导电盲孔的对位问题。
附图说明
图1为现有封装基板的剖面示意图。
图2A至图2I为本发明的封装基板的制法的剖视示意图。
图2J为图2I的另一制法的剖视示意图。
图2K为图2I的局部放大上视示意图。
图3A至图3B为图2I的后续制程的剖视示意图。
其中,附图标记说明如下:
1,2,2a,3封装基板
10核心层
100,22导电柱
11介电层
12,21线路层
120导电盲孔
20承载件
23,33绝缘层
230,330凹槽
24止挡层
240镂空区
25,35布线层
25a金属材
25b晶种层
250盲孔部
251线路
26对位部
27光阻
38绝缘保护层
380开孔
39垫部
390表面处理层。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式,熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供熟悉此技艺的人士的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“下”及“一”等的用语,亦仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当亦视为本发明可实施的范畴。
图2A至图2I为本发明的封装基板2的制法的剖视示意图。于本实施例中,该封装基板2为具有核心层(core)或无核心层(coreless)的实施例。
如图2A所示,于承载件20上依序形成线路层21及至少一导电柱22。
于本实施例中,该承载件20上为如暂时性载板的耗材,且可借由电镀铜材的方式形成该线路层21及该导电柱22。例如,先形成该线路层21于该承载件20上,再形成图案化光阻(图略)于该承载件20与该线路层21上,以令局部该线路层21外露于该图案化光阻,之后于该线路层21的外露表面上形成该导电柱22,最后移除该图案化光阻。
如图2B所示,于该承载件20上形成绝缘层23,以令该绝缘层23包覆该线路层21及该导电柱22。
于本实施例中,形成该绝缘层23的材质为如味之素增层膜(Ajinomoto Build-upFilm,简称ABF)或其它合适的介电材。例如,该绝缘层23以压合方式形成于该承载件20上。
如图2C所示,于该绝缘层23上形成具有多个镂空区240的止挡层24,以令该绝缘层23的部分表面外露于该镂空区240。
于本实施例中,形成该止挡层24的材质为如铜材或其它合适的金属材。例如,先以溅镀方式形成铜材于该绝缘层23的全部顶面上,再于该铜材上形成图案化光阻(图略),并进行曝光显影作业,以令局部铜材外露于该图案化光阻,之后蚀刻移除该外露于该图案化光阻的铜材,以形成该镂空区240,最后剥除(striping)该图案化光阻,使保留下的铜材作为该止挡层24。
如图2D所示,于该绝缘层23对应该镂空区240的表面上形成凹槽230,以令各该导电柱22对应外露于部分该凹槽230。
于本实施例中,以等离子(Plasma)或化学蚀刻方式移除该绝缘层23的部分材质以形成该凹槽230。
如图2E所示,以蚀刻方式移除该止挡层24,以外露该绝缘层23,再针对该绝缘层23与该凹槽230的表面进行除残胶(Desmear)作业。
如图2F至图2G所示,于该绝缘层23上形成金属材25a,且该金属材25a填入该凹槽230中以接触该导电柱22。
于本实施例中,可先于该绝缘层23的表面及该凹槽230的表面上形成一如铜材的晶种层25b,如图2F所示,再借由该晶种层25b以电镀铜材的方式形成该金属材25a,如图2G所示。
如图2H所示,移除该绝缘层23的表面上的至少部分该金属材25a及其下的晶种层25b,而保留该凹槽230中的金属材25a及该晶种层25b,供作为布线层25。
于本实施例中,于该凹槽230中形成该布线层25时,可保留该绝缘层23的表面上的至少部分该金属材25a及其下的晶种层25b,以一并于该绝缘层23上形成遮盖该布线层25的对位部26。例如,先形成一图案化光阻27于该金属材25a的部分表面上,再移除该光阻27周围的金属材25a及其下的晶种层25b,使该光阻27下的金属材25a及晶种层25b形成如环体的对位部26,故该对位部26与该布线层25为一体成形。
再者,该布线层25齐平该绝缘层23的表面。
如图2I所示,移除该光阻27,以外露该对位部26。于后续制程中,可移除该承载件20,使该线路层21外露且齐平该绝缘层23的表面,如图2J所示。
于本实施例中,若该布线层25为最外层的线路配置,则可省略该对位部26的制作,可在如图2G所示形成该金属材25a后,移除该绝缘层23的表面上的该金属材25a,而得到如图2J所示的封装基板2a。
因此,本发明的制法借由该导电柱22将线路结构垫高,再以等离子体或化学蚀刻方式于该绝缘层23上形成凹槽230及内埋式线路(即该布线层25),故可免除传统激光钻孔制程。
再者,本发明的制法先借由止挡层24形成凹槽230,使该布线层25能嵌埋于该绝缘层23中,以利于细间距/细线路的设计。
又,该布线层25的线路251及盲孔部250(其连接该导电柱22)形成于同一层,如图2K所示,因而能避免该线路251及该盲孔部250的位置公差问题,故可设计无垫部(designlandless)规格(如图2J所示,该盲孔部250的宽度小于该导电柱22的宽度),以提升布线密度。
另外,于其它实施例中,接续图2I所示的制程,重复图2B至图2I的制程进行增层作业,以形成多个层数的布线层35,如图3A所示,且于最外层的绝缘层33上可形成具有多个开孔380的绝缘保护层38,如图3B所示的封装基板3。例如,于最外层的布线层35上可将原本预计形成该对位部的金属材设计成多个外露于该些开孔380的垫部39,供作为接点。进一步,可于该开孔380中的垫部39上形成表面处理层390。
因此,本发明的制法借由该对位部26的设计,以于进行该增层作业的过程中,可准确将该绝缘层33的凹槽330形成于预定之处,因而能避免工作误差所致的偏位问题。
再者,可在该增层作业的任一层制作内埋式线路(即该布线层35),故可提升该布线层35的附着性,以避免制程中刮伤及提升信赖性。
应可理解地,本发明可依该增层作业的需求形成该对位部26,并无特别限制。
本发明提供一种封装基板2,2a,3,包括:具有相对两侧的绝缘层23、一嵌埋于该绝缘层23中的线路层21、至少一嵌埋于该绝缘层23中的导电柱22、以及至少一嵌埋于该绝缘层23中的布线层25。
所述的绝缘层23于其中一侧形成有凹槽230。
所述的线路层21嵌埋于该绝缘层23的另一侧。
所述的导电柱22嵌埋于该绝缘层21中以连接该线路层21。
所述的布线层25形成于该凹槽230中以连接该导电柱22。
于一实施例中,该封装基板2,3还包括至少一设于该绝缘层21上的对位部26,其遮盖该布线层25。例如,该对位部26与该布线层25为一体。
于一实施例中,该布线层25齐平该绝缘层23的表面。
综上所述,本发明的封装基板及其制法,借由凹槽的设计,使该布线层能嵌埋于该绝缘层中,因而可免除现有钻孔制程,故本发明不仅利于细间距/细线路的设计,且能避免现有线路及导电盲孔的对位问题。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (10)
1.一种封装基板,包括:
绝缘层,其于其中一侧形成有凹槽;
线路层,其嵌埋于该绝缘层的另一侧;
至少一导电柱,其嵌埋于该绝缘层中以连接该线路层;以及
布线层,其形成于该凹槽中以连接该导电柱。
2.如权利要求1所述的封装基板,其中,该封装基板还包括设于该绝缘层上的对位部,其遮盖该布线层。
3.如权利要求2所述的封装基板,其中,该对位部与该布线层为一体。
4.如权利要求1所述的封装基板,其中,该布线层齐平该绝缘层的表面。
5.一种封装基板的制法,包括:
于承载件上依序形成线路层及至少一导电柱;
于该承载件上形成绝缘层,以令该绝缘层包覆该线路层及该导电柱;
于该绝缘层上形成具有多个镂空区的止挡层,以令该绝缘层的部分表面外露于该镂空区;
于该绝缘层对应该镂空区的表面上形成凹槽,以令各该导电柱对应外露于各该凹槽;
移除该止挡层;以及
于该凹槽中形成布线层。
6.如权利要求5所述的封装基板的制法,其中,该止挡层为金属层。
7.如权利要求5所述的封装基板的制法,其中,该制法还包括于该凹槽中形成该布线层时,一并于该绝缘层上形成遮盖该布线层的对位部。
8.如权利要求7所述的封装基板的制法,其中,该对位部与该布线层为一体成形。
9.如权利要求5所述的封装基板的制法,其中,该布线层齐平该绝缘层的表面。
10.如权利要求5所述的封装基板的制法,其中,该制法还包括于该布线层上进行增层作业。
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