CN116435409A - Heterojunction battery and preparation method thereof - Google Patents
Heterojunction battery and preparation method thereof Download PDFInfo
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- CN116435409A CN116435409A CN202310512836.9A CN202310512836A CN116435409A CN 116435409 A CN116435409 A CN 116435409A CN 202310512836 A CN202310512836 A CN 202310512836A CN 116435409 A CN116435409 A CN 116435409A
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- 238000005498 polishing Methods 0.000 claims abstract description 38
- 238000005554 pickling Methods 0.000 claims description 46
- 230000003647 oxidation Effects 0.000 claims description 32
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the technical field of solar cell preparation, and particularly provides a heterojunction cell and a preparation method thereof. The preparation method of the heterojunction battery comprises the following steps: providing a semiconductor substrate layer, wherein the semiconductor substrate layer comprises a first surface and a second surface which are opposite; texturing the first surface and the second surface of the semiconductor substrate layer to form a textured surface on the first surface and the second surface; forming a patterned mask on the second surface of the semiconductor substrate layer, wherein the patterned mask covers part of the suede of the second surface; polishing the area of the second surface of the semiconductor substrate layer not covered by the patterned mask; and removing the patterned mask to form the semiconductor substrate layer with the first surface being full-faced and the second surface being a part of smooth surface and a part of textured surface. According to the preparation method of the heterojunction battery, provided by the invention, the passivation effect of the semiconductor substrate layer is improved, and meanwhile, the adhesiveness between the slurry and the semiconductor substrate layer is improved, so that the photoelectric conversion efficiency of the heterojunction battery is improved.
Description
Technical Field
The invention relates to the technical field of solar cell preparation, in particular to a heterojunction cell and a preparation method thereof.
Background
At present, solar energy is increasingly valued as green clean energy under the pushing of a double-carbon background, and in the application technology of solar energy, the photovoltaic industry is coming to the development period of unprecedented prosperity. Silicon-based heterojunction solar cells are one of the important objects of current high-efficiency solar cells. Silicon-based heterojunction solar cells are generally prepared from textured N-type monocrystalline silicon wafers having a double-sided pyramid structure. Firstly, depositing an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer (microcrystalline silicon layer) on the front surface of a textured semiconductor substrate layer, depositing the intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer (microcrystalline silicon layer) on the back surface of the semiconductor substrate layer, and then forming a transparent conductive film and a metal electrode on two sides of the semiconductor substrate layer respectively. The pyramid suede on the back of the semiconductor substrate layer is unfavorable for secondary reflection and absorption of incident light, and the thickness uniformity of the amorphous silicon layer deposited on the surface of the pyramid is relatively poor, so that the difficulty of passivation of the back of the semiconductor substrate layer is higher, and the optimized passivation space is smaller. In the current production process of heterojunction batteries, polishing treatment is generally selected for the back surface of the semiconductor substrate layer, but after polishing treatment, the textured structure of the back surface of the semiconductor substrate layer can lead to the decrease of the adhesive force of the slurry to the semiconductor substrate layer in the screen printing process, so that if the slurry is in poor contact with the semiconductor substrate layer, part of grid lines fall off, and the photoelectric conversion efficiency of the heterojunction batteries is low.
However, there are two main approaches to the above problem with needles: one is to develop high quality, tailored low temperature slurries to increase adhesion between the slurry and the semiconductor substrate layer, which is relatively costly and difficult; the other mode adopts a semi-polishing mode to reduce the suede structure on the back surface of the semiconductor substrate layer, but the back surface of the semiconductor substrate layer formed in the way still cannot improve the adhesiveness between the slurry and the semiconductor substrate layer while guaranteeing the passivation effect.
Therefore, it is desirable to provide a solution that ensures the adhesion between the paste and the back surface of the semiconductor substrate layer while ensuring a good passivation effect on the back surface of the semiconductor substrate layer, thereby improving the photoelectric conversion efficiency of the heterojunction cell.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects of low photoelectric conversion efficiency of the heterojunction battery caused by poor passivation effect of the semiconductor substrate layer and low adhesiveness of the slurry and the semiconductor substrate layer in the prior art, thereby providing the heterojunction battery and the preparation method thereof.
The invention provides a preparation method of a heterojunction battery, which comprises the following steps: providing a semiconductor substrate layer comprising opposing first and second surfaces; texturing the first surface and the second surface of the semiconductor substrate layer to render the first surface and the second surface textured; forming a patterned mask on the second surface of the semiconductor substrate layer, wherein the patterned mask covers part of the suede of the second surface; after the patterned mask is formed, polishing the area of the second surface of the semiconductor substrate layer which is not covered by the patterned mask; and removing the patterned mask to form the semiconductor substrate layer with the first surface having the full-face texture and the second surface having the partial-face texture.
Optionally, the patterned mask is strip-shaped; the number of the patterned masks is a plurality of, and the patterned masks are parallel to each other and are arranged at intervals; methods of forming the patterned mask include one or more of screen printing, spraying, photolithography, deposition, or physical sputtering.
Optionally, the polishing treatment adopts an alkaline polishing solution, wherein the alkaline polishing solution comprises a KOH solution or a NaOH solution, the mass percentage concentration of the alkaline polishing solution is 1% -5%, the temperature of the polishing treatment is 40-80 ℃, and the time of the polishing treatment is 60-300 s.
Optionally, the method further comprises: performing an oxidation treatment on the first surface and the second surface of the semiconductor substrate layer after performing a texturing treatment on the first surface and the second surface of the semiconductor substrate layer and before forming a patterned mask on the second surface of the semiconductor substrate layer, so as to form a first oxide layer on the first surface of the semiconductor substrate layer and a second oxide layer on the second surface of the semiconductor substrate layer; and after the oxidation treatment, removing the second oxide layer before forming a patterned mask on the second surface of the semiconductor substrate layer.
Optionally, the oxidation treatment is performed in a tube diffusion furnace; the gas source of the oxidation treatment comprises an oxidizing gas and an inert gas; the flow rate of the oxidizing gas adopted in the oxidation treatment is 0.1slm-30slm, and the flow rate of the inert gas adopted in the oxidation treatment is 0.1slm-30slm; the temperature adopted in the oxidation treatment is 500-900 ℃ and the time is 60-900 s; alternatively, the oxidation treatment is performed in an oxidation tank containing an oxidizing agent; the oxidizing agent comprises nitric acid; the mass percentage concentration of the nitric acid is 1% -50%; the temperature adopted in the oxidation treatment is 25-50 ℃ and the time is 5-600 s; the thickness of the first oxide layer and the second oxide layer is 5nm-300nm.
Optionally, the step of removing the second oxide layer includes: carrying out first pickling treatment on the second oxide layer by adopting a chain pickling machine; the interior of the chain pickling machine is used for containing a first pickling solution; the mass percentage concentration of the first pickling solution is 0.001-38%, the temperature of the first pickling treatment is 25-30 ℃, and the time of the first pickling treatment is 10-600 s.
Optionally, the step of removing the patterned mask includes: providing a pickling tank, wherein the interior of the pickling tank is used for containing a second pickling solution; placing the semiconductor substrate layer in the pickling tank to carry out second pickling treatment on the patterned mask; the preparation method of the heterojunction battery further comprises the following steps: removing the first oxide layer in the process of carrying out second acid washing treatment on the patterned mask; the mass percentage concentration of the second pickling solution is 0.001-38%, the temperature of the second pickling treatment is 25-30 ℃, and the time of the second pickling treatment is 10-600 s.
Optionally, the method further comprises: forming a first grid line on one side of a first surface of the semiconductor substrate layer, and forming a second grid line on one side of a second surface of the semiconductor substrate layer; the second grid line is arranged corresponding to the suede of the second surface, and the first grid line is arranged corresponding to the second grid line; further comprises: after removing the patterning mask, forming a first intrinsic semiconductor layer on a first surface of the semiconductor substrate layer and forming a second intrinsic semiconductor layer on a second surface of the semiconductor substrate layer; forming a first doped semiconductor layer on a side of the first intrinsic semiconductor layer facing away from the semiconductor substrate layer and forming a second doped semiconductor layer on a side of the second intrinsic semiconductor layer facing away from the semiconductor substrate layer; forming a first transparent conductive film on one side of the first doped semiconductor layer away from the semiconductor substrate layer; forming a second transparent conductive film on one side of the second doped semiconductor layer away from the semiconductor substrate layer; forming a first gate line on a side of the first transparent conductive film facing away from the semiconductor substrate layer after forming the first transparent conductive film and the second transparent conductive film; forming a second grid line on one side of the second transparent conductive film away from the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer.
The present invention provides a heterojunction battery comprising: the first surface of the semiconductor substrate layer is full-face textured, and the second surface of the semiconductor substrate layer is partially smooth and partially textured.
Optionally, the method further comprises: a first gate line located at a first surface side of the semiconductor substrate layer; a second gate line located at a second surface side of the semiconductor substrate layer; the second grid line is arranged corresponding to the suede of the second surface, and the first grid line is arranged corresponding to the second grid line; further comprises: a first intrinsic semiconductor layer located on a first surface of the semiconductor substrate layer and located on a side of the first gate line facing the semiconductor substrate layer; a second intrinsic semiconductor layer located on a second surface of the semiconductor substrate layer and located on a side of the second gate line facing the semiconductor substrate layer; a first doped semiconductor layer located on a side of the first intrinsic semiconductor layer facing away from the semiconductor substrate layer and on a side of the first gate line facing toward the semiconductor substrate layer; a second doped semiconductor layer located on a side of the second intrinsic semiconductor layer facing away from the semiconductor substrate layer and on a side of the second gate line facing toward the semiconductor substrate layer; the first transparent conductive film is positioned on one side of the first doped semiconductor layer, which is away from the semiconductor substrate layer, and is positioned on one side of the first grid line, which is towards the semiconductor substrate layer; the second transparent conductive film is positioned on one side of the second doped semiconductor layer, which is away from the semiconductor substrate layer, and is positioned on one side of the second grid line, which is towards the semiconductor substrate layer; wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer.
The invention has the beneficial effects that:
according to the preparation method of the heterojunction battery, the comprehensive suede is formed on the first surface of the semiconductor substrate layer, when light irradiates from the first surface of the heterojunction battery, the quantity of incident sunlight reflected by the semiconductor substrate layer is reduced, and therefore more solar energy incident from the first surface of the heterojunction battery enters the semiconductor substrate layer. The area of the second surface of the semiconductor substrate layer, on which the patterned mask is not formed, is polished to form a smooth surface, which is favorable for long-wave absorption of the semiconductor substrate layer, avoids the recombination of photo-generated carriers on the second surface of the semiconductor substrate layer, and prolongs the service life of minority carriers; secondly, the flatness of the area of the second surface with the smooth surface is higher, which is beneficial to improving the uniformity of the subsequent deposited intrinsic semiconductor layer and the passivation effect of the intrinsic semiconductor layer, thereby improving the photoelectric conversion efficiency of the heterojunction battery; the region of forming the patterned mask on the second surface of the semiconductor substrate layer is not affected by polishing treatment, and is textured after the patterned mask is removed, so that the adhesion between the subsequently printed slurry and the semiconductor substrate layer is improved, the subsequently formed second grid line is prevented from being removed, and the photoelectric conversion efficiency of the heterojunction battery is further improved. In addition, the existing slurry can meet the preparation of heterojunction batteries, special low-temperature slurry does not need to be developed, and the process cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for preparing a heterojunction battery in embodiment 1 of the present invention;
fig. 2 to 12 are schematic structural views of each process in the preparation method of the heterojunction battery in embodiment 1 of the present invention;
reference numerals illustrate:
1-a semiconductor substrate layer; 2-a first oxide layer; 3-a second oxide layer; 4-patterning the mask; 5-a first intrinsic semiconductor layer; 6-a second intrinsic semiconductor layer; 7-a first doped semiconductor layer; 8-a second doped semiconductor layer; 9-a first transparent conductive film; 10-a second transparent conductive film; 11-a first gate line; 12-a second gate line.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
The embodiment of the invention provides a preparation method of a heterojunction battery, referring to fig. 1, comprising the following steps:
s1: providing a semiconductor substrate layer comprising opposing first and second surfaces;
s2: texturing the first surface and the second surface of the semiconductor substrate layer to render the first surface and the second surface textured;
s3: forming a patterned mask on the second surface of the semiconductor substrate layer, wherein the patterned mask covers part of the suede of the second surface;
s4: after the patterned mask is formed, polishing the area of the second surface of the semiconductor substrate layer which is not covered by the patterned mask;
s5: and removing the patterned mask to form the semiconductor substrate layer with the first surface having the full-face texture and the second surface having the partial-face texture.
In this embodiment, a full-face suede is formed on the first surface of the semiconductor substrate layer, and when light irradiates from the first surface of the heterojunction cell, the amount of incident sunlight reflected by the semiconductor substrate layer is reduced, so that more solar energy incident from the first surface of the heterojunction cell enters the semiconductor substrate layer. The area of the second surface of the semiconductor substrate layer, on which the patterned mask is not formed, is polished to form a smooth surface, which is favorable for long-wave absorption of the semiconductor substrate layer, avoids the recombination of photo-generated carriers on the second surface of the semiconductor substrate layer, and prolongs the service life of minority carriers; secondly, the flatness of the area of the second surface with the smooth surface is higher, which is beneficial to improving the uniformity of the subsequent deposited intrinsic semiconductor layer and the passivation effect of the intrinsic semiconductor layer, thereby improving the photoelectric conversion efficiency of the heterojunction battery; the region of forming the patterned mask on the second surface of the semiconductor substrate layer is not affected by polishing treatment, and is textured after the patterned mask is removed, so that the adhesion between the subsequently printed slurry and the semiconductor substrate layer is improved, the subsequently formed second grid line is prevented from being removed, and the photoelectric conversion efficiency of the heterojunction battery is further improved. In addition, the existing slurry can meet the preparation of heterojunction batteries, special low-temperature slurry does not need to be developed, and the process cost is reduced.
The preparation method of the heterojunction battery further comprises the following steps: performing an oxidation treatment on the first surface and the second surface of the semiconductor substrate layer after performing a texturing treatment on the first surface and the second surface of the semiconductor substrate layer and before forming a patterned mask on the second surface of the semiconductor substrate layer, so as to form a first oxide layer on the first surface of the semiconductor substrate layer and a second oxide layer on the second surface of the semiconductor substrate layer; and after the oxidation treatment, removing the second oxide layer before forming a patterned mask on the second surface of the semiconductor substrate layer.
The preparation method of the heterojunction battery further comprises the following steps: forming a first grid line on one side of a first surface of the semiconductor substrate layer, and forming a second grid line on one side of a second surface of the semiconductor substrate layer;
the second grid lines are arranged corresponding to the suede of the second surface, and the first grid lines are arranged corresponding to the second grid lines.
The method of fabricating the heterojunction cell is described in detail below with reference to fig. 2 to 12.
Referring to fig. 2, a semiconductor substrate layer 1 is provided.
The semiconductor substrate layer 1 comprises opposite first and second surfaces.
Specifically, the first surface of the semiconductor substrate layer 1 is the front surface of the semiconductor substrate layer 1, and the second surface of the semiconductor substrate layer 1 is the back surface of the semiconductor substrate layer 1. In other embodiments, the first surface of the semiconductor substrate layer may be a back surface of the semiconductor substrate layer, and the second surface of the semiconductor substrate layer may be a front surface of the semiconductor substrate layer.
The material of the semiconductor substrate layer 1 comprises monocrystalline silicon. In other embodiments, the material of the semiconductor substrate layer is other semiconductor materials, such as silicon or silicon germanium. The material of the semiconductor substrate layer may also be other semiconductor materials.
In this embodiment, the conductivity type of the semiconductor substrate layer 1 is N-type, for example, N-type silicon wafer, which is suitable for the preparation of heterojunction cells.
Referring to fig. 3, the first surface and the second surface of the semiconductor substrate layer 1 are subjected to a texturing process.
After the texturing process, the first surface of the semiconductor substrate layer 1 forms a full-face textured surface, and when light irradiates from the first surface of the heterojunction cell, the amount of incident sunlight reflected by the semiconductor substrate layer 1 is reduced, so that more sunlight incident from the first surface of the heterojunction cell enters the initial semiconductor substrate layer 1.
In this embodiment, the pile surface is pyramidal. In other embodiments, the pile surface may have other shapes, without limitation.
In one embodiment, the pyramid-shaped light trapping texture is formed by alkali texturing. The texturing treatment adopts an alkaline texturing solution, wherein the alkaline texturing solution comprises a KOH solution or a NaOH solution, and the mass percentage concentration of the alkaline texturing solution is 0.5% -5%, for example 1%, 2%, 3%, 4%, or 5%; the temperature of the texturing treatment is 40-80 ℃, such as 40 ℃, 50 ℃, 60 ℃, 70 ℃ or 80 ℃, and the time of the texturing treatment is 300-900 s, such as 400s, 500s, 600s, 700s, 800s or 900s.
Referring to fig. 4, the first surface and the second surface of the semiconductor substrate layer 1 are subjected to an oxidation treatment.
After the first surface and the second surface of the semiconductor substrate layer 1 are subjected to texturing treatment, the first surface and the second surface of the semiconductor substrate layer 1 are subjected to oxidation treatment to form a first oxide layer 2 on the first surface of the semiconductor substrate layer 1 and a second oxide layer 3 on the second surface of the semiconductor substrate layer 1. When the material of the semiconductor substrate layer 1 is silicon, the first oxide layer 2 is SiO 2 The second oxide layer 3 is SiO 2 。
In one embodiment, the oxidation treatment is performed in a tube diffusion furnace; the gas source for the oxidation treatment comprises an oxidizing gas and an inert gas. The inert gas is used for exhausting air in the tubular diffusion furnace, so that impurity gas in the furnace is avoided; the oxidizing gas oxidizes the first surface and the second surface of the semiconductor substrate layer.
In one embodiment, the oxidizing process employs an oxidizing gas flow rate of 0.1slm to 30slm, such as 0.1slm, 10slm, 20slm, or 30slm; the flow rate of the inert gas adopted by the oxidation treatment is 0.1slm-30slm, for example, 0.1slm, 10slm, 20slm or 30slm.
In one embodiment, the oxidizing gas comprises oxygen; the inert gas includes nitrogen. In other embodiments, the oxidizing gas includes other forms of oxidizing gas; the inert gas includes other forms of inert gas.
In one embodiment, the oxidation treatment is carried out at a temperature of 500 ℃ to 900 ℃, such as 500 ℃, 600 ℃, 700 ℃, 800 ℃ or 900 ℃, for a time of 60s to 900s, such as 60s, 100s, 200s, 400s, 500s, 700s or 900s.
In another embodiment, the oxidation treatment is performed in an oxidation tank containing an oxidizing agent; the oxidizing agent comprises nitric acid.
In one embodiment, the nitric acid is present at a concentration of 1% to 50% by mass, such as 1%, 10%, 20%, 30%, 40% or 50%; the oxidation treatment is carried out at a temperature of 25 ℃ to 50 ℃, for example 25 ℃, 30 ℃, 35 ℃, 40 ℃ or 50 ℃; the time is 5s-600s, for example 5s, 20s, 100s, 200s, 300s, 400s, 500s or 600s.
In one embodiment, the thickness of the first oxide layer 2 and the second oxide layer 3 is 5nm-300nm, for example 5nm, 20nm, 60nm, 100nm, 200nm or 300nm. If the thickness of the first oxide layer is too large, the process cost is high, and resource waste is easily caused; if the thickness of the first oxide layer is too small, the protection effect of the suede structure on the first surface of the semiconductor substrate layer is small in the subsequent polishing treatment process, and the effect of improving the photoelectric conversion efficiency of the heterojunction battery is weak.
Referring to fig. 5, the second oxide layer 3 is removed.
After the first surface and the second surface of the semiconductor substrate layer 1 are subjected to oxidation treatment, the second oxide layer 3 is removed. The first oxide layer 2 is still positioned on the first surface of the semiconductor substrate layer 1, and the first oxide layer 2 is used as a protective layer of the first surface of the semiconductor substrate layer 1, so that damage to a suede structure of the first surface caused by polishing solution can be avoided when polishing is carried out subsequently; and, the first oxide layer 2 is always present before the subsequent removal of the patterned mask.
In one embodiment, the step of removing the second oxide layer 3 comprises: carrying out first acid cleaning treatment on a second oxide layer on the second surface of the semiconductor substrate layer 1 by adopting a chain acid cleaning machine; the interior of the chain pickling machine is used for containing a first pickling solution. The chain type pickling machine can only carry out the first pickling treatment on the second oxide layer 3 on the second surface, so that the contact probability of the first pickling solution and the first oxide layer 2 is reduced, and the suede structure of the first surface is further protected.
In one embodiment, the first pickling solution comprises an HF solution, at a concentration of 0.001% -38% by mass, for example 0.001%, 0.02%, 5%, 10%, 20%, 30% or 38%; the temperature of the first acid wash treatment is from 25 ℃ to 30 ℃, for example 25 ℃, 28 ℃ or 30 ℃; the time of the first pickling treatment is 10s-600s, for example 10s, 100s, 300s, 500s or 600s.
Referring to fig. 6, a patterned mask 4 is formed on the second surface of the semiconductor substrate layer 1.
After removing the second oxide layer 3, a patterned mask 4 is formed on the second surface of the semiconductor substrate layer 1. The patterned mask 4 is an alkali-resistant and acid-resistant mask, and the alkaline polishing solution is adopted in the subsequent polishing treatment, so that the area of the semiconductor substrate layer 1 shielded by the patterned mask 4 is not affected by the polishing treatment, and the patterned mask 4 is suede after being removed, thereby being beneficial to improving the adhesiveness between the subsequently printed slurry and the semiconductor substrate layer, avoiding the grid stripping of the subsequently formed second grid line and improving the reliability of the heterojunction battery.
In one embodiment, the patterned mask 4 is in the shape of a bar; the number of the patterned masks 4 is a plurality of, and the patterned masks 4 are parallel to each other and are arranged at intervals.
In one embodiment, the method of forming the patterned mask 4 includes one or more of screen printing, spraying, photolithography, deposition, or physical sputtering.
Referring to fig. 7, the second surface of the semiconductor substrate layer 1 is subjected to polishing treatment.
After forming the patterned mask 4 on the second surface of the semiconductor substrate layer 1, the second surface of the semiconductor substrate layer 1 is subjected to polishing treatment.
After polishing treatment, the second surface part of the semiconductor substrate layer 1 presents a smooth surface, which is beneficial to keeping the flatness of the second surface of the semiconductor substrate layer, improving the uniformity of the subsequent deposited intrinsic semiconductor layer and increasing the passivation effect of the intrinsic semiconductor layer; and in addition, the long-wave absorption of the semiconductor substrate layer is facilitated, the recombination of photo-generated carriers on the second surface of the semiconductor substrate layer is avoided, the service life of minority carriers is prolonged, and the photoelectric conversion efficiency of the heterojunction battery is improved.
In one embodiment, the polishing treatment employs an alkaline polishing solution comprising a KOH solution or NaOH solution, the alkaline polishing solution having a mass percent concentration of 1% -5%, such as 1%, 2%, 3% or 5%; the temperature of the polishing treatment is 40 ℃ to 80 ℃, for example 40 ℃, 50 ℃, 60 ℃, 70 ℃ or 80 ℃; the polishing treatment is performed for a period of 60s to 300s, for example, 60s, 100s, 200s or 300s.
Referring to fig. 8, the patterned mask 4 and the first oxide layer 2 are removed.
And after polishing the second surface of the semiconductor substrate layer 1, removing the patterned mask 4 and the first oxide layer 2 to form the semiconductor substrate layer with the first surface having a full-face texture and the second surface having a partial-face texture.
In one embodiment, the step of removing the patterned mask 4 comprises: providing a pickling tank, wherein the interior of the pickling tank is used for containing a second pickling solution; placing the semiconductor substrate layer 1 in a pickling tank to carry out second pickling treatment on the patterned mask 4; the preparation method of the heterojunction battery further comprises the following steps: and removing the first oxide layer 2 in the process of carrying out second acid washing treatment on the patterned mask 4. The first oxide layer 2 on the first surface and the patterned mask 4 on the second surface of the semiconductor substrate layer 1 are immersed in a pickling tank, and the patterned mask 4 is removed and the first oxide layer 2 is removed at the same time, so that the production process is simplified.
In one embodiment, the second pickling solution comprises an HF solution, the second pickling solution having a concentration of 0.001% -38% by mass, for example 0.001%, 0.02%, 5%, 10%, 20%, 30% or 38%; the temperature of the second acid wash treatment is from 25 ℃ to 30 ℃, for example 25 ℃, 28 ℃ or 30 ℃; the second pickling treatment is performed for 10s to 600s, for example, 10s, 100s, 300s, 500s or 600s.
In this embodiment, after the patterned mask 4 is removed, rinsing treatment is performed on the first surface and the second surface of the semiconductor substrate layer 1; after the first surface and the second surface of the semiconductor substrate layer 1 are rinsed, the first surface and the second surface of the semiconductor substrate layer 1 are baked.
Referring to fig. 9, a first intrinsic semiconductor layer 5 is formed on a first surface of the semiconductor substrate layer 1 and a second intrinsic semiconductor layer 6 is formed on a second surface of the semiconductor substrate layer 1.
After the first and second surfaces of the semiconductor substrate layer 1 are subjected to a baking process, a first intrinsic semiconductor layer 5 is formed on the first surface of the semiconductor substrate layer 1 and a second intrinsic semiconductor layer 6 is formed on the second surface of the semiconductor substrate layer 1.
In other embodiments, no drying or rinsing is required; after removal of the patterned mask 4, a first intrinsic semiconductor layer 5 is formed on the first surface of the semiconductor substrate layer 1 and a second intrinsic semiconductor layer 6 is formed on the second surface of the semiconductor substrate layer 1.
The process of forming the first intrinsic semiconductor layer 5 includes a vapor deposition process. The process of forming the second intrinsic semiconductor layer 6 includes a vapor deposition process. By forming the first and second intrinsic semiconductor layers 5 and 6, dangling bonds of the semiconductor substrate layer 1 can be effectively hydrogenated and surface defects can be reduced, thereby improving minority carrier lifetime, increasing open-circuit voltage, and ultimately improving heterojunction cell efficiency.
Referring to fig. 10, a first doped semiconductor layer 7 is formed on a side of the first intrinsic semiconductor layer 5 facing away from the semiconductor substrate layer 1 and a second doped semiconductor layer 8 is formed on a side of the second intrinsic semiconductor layer 6 facing away from the semiconductor substrate layer 1.
After forming the first intrinsic semiconductor layer 5 on the first surface of the semiconductor substrate layer 1 and the second intrinsic semiconductor layer 6 on the second surface of the semiconductor substrate layer 1, a first doped semiconductor layer 7 is formed on the side of the first intrinsic semiconductor layer 5 facing away from the semiconductor substrate layer 1 and a second doped semiconductor layer 8 is formed on the side of the second intrinsic semiconductor layer 6 facing away from the semiconductor substrate layer 1. Wherein the conductivity type of the second doped semiconductor layer 8 is opposite to the conductivity type of the first doped semiconductor layer 7.
In the present embodiment, the conductivity type of the first doped semiconductor layer 7 is N-type, and the conductivity type of the second doped semiconductor layer 8 is P-type as an example.
The process of forming the first doped semiconductor layer 7 includes a vapor deposition process. The process of forming the second doped semiconductor layer 8 includes a vapor deposition process.
Referring to fig. 11, a first transparent conductive film 9 is formed on a side of the first doped semiconductor layer 7 facing away from the semiconductor substrate layer 1; a second transparent conductive film 10 is formed on the side of the second doped semiconductor layer 8 facing away from the semiconductor substrate layer 1.
After forming a first doped semiconductor layer 7 on a side surface of the first intrinsic semiconductor layer 5 facing away from the semiconductor substrate layer 1 and a second doped semiconductor layer 8 on a side surface of the second intrinsic semiconductor layer 6 facing away from the semiconductor substrate layer 1, forming a first transparent conductive film 9 on a side of the first doped semiconductor layer 7 facing away from the semiconductor substrate layer 1; a second transparent conductive film 10 is formed on the side of the second doped semiconductor layer 8 facing away from the semiconductor substrate layer 1.
Referring to fig. 12, a first gate line 11 is formed on a side of the first transparent conductive film 9 facing away from the semiconductor substrate layer 1; a second gate line 12 is formed on a side of the second transparent conductive film 10 facing away from the semiconductor substrate layer 1.
Forming a first transparent conductive film 9 on a side of the first doped semiconductor layer 7 facing away from the semiconductor substrate layer 1; after forming a second transparent conductive film 10 on the side of the second doped semiconductor layer 8 facing away from the semiconductor substrate layer 1, forming a first gate line 11 on the side of the first transparent conductive film 9 facing away from the semiconductor substrate layer 1; a second gate line 12 is formed on a side of the second transparent conductive film 10 facing away from the semiconductor substrate layer 1.
Specifically, the second gate line 12 is disposed corresponding to the pile surface of the second surface, and the first gate line 11 is disposed corresponding to the second gate line 12.
Example 2
The present embodiment provides a heterojunction battery, referring to fig. 12, including:
the semiconductor substrate layer 1, the first surface of the semiconductor substrate layer 1 presents a full surface texture, and the second surface of the semiconductor substrate layer presents a partial smooth surface and a partial texture.
In this embodiment, the first surface of the semiconductor substrate layer 1 is fully textured, and when light irradiates from the first surface of the heterojunction cell, the amount of incident sunlight reflected by the semiconductor substrate layer 1 is reduced, so that more solar energy incident from the first surface of the heterojunction cell enters the semiconductor substrate layer 1. The second surface of the semiconductor substrate layer 1 is a partial smooth surface, which is beneficial to keeping the flatness of the second surface of the semiconductor substrate layer 1, improving the uniformity of the subsequent deposited intrinsic semiconductor layer and increasing the passivation effect of the intrinsic semiconductor layer; in addition, the long wave absorption of the semiconductor substrate layer 1 is facilitated, the recombination of photo-generated carriers on the second surface of the semiconductor substrate layer is avoided, the service life of minority carriers is prolonged, and therefore the photoelectric conversion efficiency of the heterojunction battery is improved; the second surface of the semiconductor substrate layer 1 is partially textured, so that the adhesion between the subsequently printed slurry and the semiconductor substrate layer 1 is improved, the subsequently formed second grid line is prevented from being removed, and the reliability of the heterojunction battery is improved.
The heterojunction cell further comprises: a first gate line 11 located on the first surface side of the semiconductor substrate layer 1; and a second gate line 12 positioned on the second surface side of the semiconductor substrate layer 1.
In this embodiment, the second gate line 12 is disposed corresponding to the suede of the second surface, and the first gate line 11 is disposed corresponding to the second gate line 12. The suede structure is favorable for keeping the adhesiveness of the printed sizing agent and the semiconductor substrate layer 1, so that the first grid line 11 and the second grid line 12 can be prevented from being separated from the grid, and the reliability of the heterojunction battery is improved.
The heterojunction cell further comprises: a first intrinsic semiconductor layer 5 located on the first surface of the semiconductor substrate layer 1 and on a side of the first gate line 11 facing the semiconductor substrate layer 1; a second intrinsic semiconductor layer 6 located on the second surface of the semiconductor substrate layer 1 and on a side of the second gate line 12 facing the semiconductor substrate layer 1; a first doped semiconductor layer 7 on a side of the first intrinsic semiconductor layer 5 facing away from the semiconductor substrate layer 1 and on a side of the first gate line 11 facing toward the semiconductor substrate layer 1; a second doped semiconductor layer 8 on a side of the second intrinsic semiconductor layer 6 facing away from the semiconductor substrate layer 1 and on a side of the second gate line 12 facing toward the semiconductor substrate layer 1; a first transparent conductive film 9 on a side of the first doped semiconductor layer 7 facing away from the semiconductor substrate layer 1 and on a side of the first gate line 11 facing toward the semiconductor substrate layer 1; a second transparent conductive film 10 is located on a side of the second doped semiconductor layer 8 facing away from the semiconductor substrate layer 1, and on a side of the second gate line 12 facing toward the semiconductor substrate layer 1.
The conductivity type of the second doped semiconductor layer 8 is opposite to the conductivity type of the first doped semiconductor layer 7. In the present embodiment, the conductivity type of the first doped semiconductor layer 7 is N-type, and the conductivity type of the second doped semiconductor layer 8 is P-type as an example.
The invention is different from the semi-polishing mode in the prior art, and reduces the suede structure on the back of the semiconductor substrate layer. Specifically, the first surface is the front surface of the semiconductor substrate layer 1, and the second surface is the back surface of the semiconductor substrate layer 1; the area, on which the patterned mask is not formed, of the second surface of the semiconductor substrate layer is polished, so that the flatness of the polished surface is high, the uniformity of the intrinsic semiconductor layer deposited later is improved, the passivation effect of the intrinsic semiconductor layer is improved, and the photoelectric conversion efficiency of the heterojunction battery is improved; the region of forming the patterned mask on the back surface of the semiconductor substrate layer is not affected by polishing treatment, and is in a suede shape after the patterned mask is removed, so that the adhesion between the subsequently printed sizing agent and the semiconductor substrate layer is improved, the subsequently formed second grid line is prevented from being removed, and the photoelectric conversion efficiency of the heterojunction battery is further improved by about 0.05% -0.2%. In addition, the existing slurry can meet the preparation of heterojunction batteries, special low-temperature slurry is not required to be developed, and the process cost is reduced.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (10)
1. A method of fabricating a heterojunction cell, comprising:
providing a semiconductor substrate layer comprising opposing first and second surfaces;
texturing the first surface and the second surface of the semiconductor substrate layer to render the first surface and the second surface textured;
forming a patterned mask on the second surface of the semiconductor substrate layer, wherein the patterned mask covers part of the suede of the second surface;
after the patterned mask is formed, polishing the area of the second surface of the semiconductor substrate layer which is not covered by the patterned mask;
and removing the patterned mask to form the semiconductor substrate layer with the first surface having the full-face texture and the second surface having the partial-face texture.
2. The method of manufacturing a heterojunction cell as claimed in claim 1, wherein the patterned mask is in a stripe shape; the number of the patterned masks is a plurality of, and the patterned masks are parallel to each other and are arranged at intervals;
methods of forming the patterned mask include one or more of screen printing, spraying, photolithography, deposition, or physical sputtering.
3. The method for preparing the heterojunction cell as claimed in claim 1, wherein the polishing treatment adopts an alkaline polishing solution, the alkaline polishing solution comprises a KOH solution or a NaOH solution, the mass percentage concentration of the alkaline polishing solution is 1% -5%, the temperature of the polishing treatment is 40-80 ℃, and the time of the polishing treatment is 60-300 s.
4. The method of manufacturing a heterojunction cell as claimed in claim 1, further comprising: performing oxidation treatment on the first surface and the second surface of the semiconductor substrate layer after performing texturing treatment on the first surface and the second surface of the semiconductor substrate layer and before forming a patterned mask on the second surface of the semiconductor substrate layer to form a first oxide layer on the first surface of the semiconductor substrate layer and a second oxide layer on the second surface of the semiconductor substrate layer;
after performing the oxidation treatment, the second oxide layer is removed before the second surface of the semiconductor substrate layer forms a patterned mask.
5. The method for producing a heterojunction cell as claimed in claim 4, wherein the oxidation treatment is performed in a tube-type diffusion furnace; the gas source of the oxidation treatment comprises an oxidizing gas and an inert gas; the flow rate of the oxidizing gas adopted in the oxidation treatment is 0.1slm-30slm, and the flow rate of the inert gas adopted in the oxidation treatment is 0.1slm-30slm; the temperature adopted in the oxidation treatment is 500-900 ℃ and the time is 60-900 s;
alternatively, the oxidation treatment is performed in an oxidation tank containing an oxidizing agent; the oxidizing agent comprises nitric acid; the mass percentage concentration of the nitric acid is 1% -50%; the temperature adopted in the oxidation treatment is 25-50 ℃ and the time is 5-600 s;
the thickness of the first oxide layer and the second oxide layer is 5nm-300nm.
6. The method of manufacturing a heterojunction cell as claimed in claim 4, wherein the step of removing the second oxide layer comprises: carrying out first pickling treatment on the second oxide layer by adopting a chain pickling machine; the interior of the chain pickling machine is used for containing a first pickling solution;
the mass percentage concentration of the first pickling solution is 0.001-38%, the temperature of the first pickling treatment is 25-30 ℃, and the time of the first pickling treatment is 10-600 s.
7. The method of manufacturing a heterojunction cell as claimed in claim 4, wherein the step of removing the patterned mask comprises: providing a pickling tank, wherein the interior of the pickling tank is used for containing a second pickling solution; placing the semiconductor substrate layer in the pickling tank to carry out second pickling treatment on the patterned mask;
the preparation method of the heterojunction battery further comprises the following steps: removing the first oxide layer in the process of carrying out second acid washing treatment on the patterned mask;
the mass percentage concentration of the second pickling solution is 0.001-38%, the temperature of the second pickling treatment is 25-30 ℃, and the time of the second pickling treatment is 10-600 s.
8. The method of manufacturing a heterojunction cell as claimed in claim 1, further comprising: forming a first grid line on one side of a first surface of the semiconductor substrate layer, and forming a second grid line on one side of a second surface of the semiconductor substrate layer;
the second grid line is arranged corresponding to the suede of the second surface, and the first grid line is arranged corresponding to the second grid line;
further comprises: after removing the patterning mask, forming a first intrinsic semiconductor layer on a first surface of the semiconductor substrate layer and forming a second intrinsic semiconductor layer on a second surface of the semiconductor substrate layer; forming a first doped semiconductor layer on a side of the first intrinsic semiconductor layer facing away from the semiconductor substrate layer and forming a second doped semiconductor layer on a side of the second intrinsic semiconductor layer facing away from the semiconductor substrate layer; forming a first transparent conductive film on one side of the first doped semiconductor layer away from the semiconductor substrate layer; forming a second transparent conductive film on one side of the second doped semiconductor layer away from the semiconductor substrate layer; forming a first gate line on a side of the first transparent conductive film facing away from the semiconductor substrate layer after forming the first transparent conductive film and the second transparent conductive film; forming a second grid line on one side of the second transparent conductive film away from the semiconductor substrate layer;
wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer.
9. A heterojunction battery, comprising:
the first surface of the semiconductor substrate layer is full-face textured, and the second surface of the semiconductor substrate layer is partially smooth and partially textured.
10. The heterojunction cell of claim 9, further comprising: a first gate line located at a first surface side of the semiconductor substrate layer; a second gate line located at a second surface side of the semiconductor substrate layer;
the second grid line is arranged corresponding to the suede of the second surface, and the first grid line is arranged corresponding to the second grid line;
further comprises: a first intrinsic semiconductor layer located on a first surface of the semiconductor substrate layer and located on a side of the first gate line facing the semiconductor substrate layer; a second intrinsic semiconductor layer located on a second surface of the semiconductor substrate layer and located on a side of the second gate line facing the semiconductor substrate layer; a first doped semiconductor layer located on a side of the first intrinsic semiconductor layer facing away from the semiconductor substrate layer and on a side of the first gate line facing toward the semiconductor substrate layer; a second doped semiconductor layer located on a side of the second intrinsic semiconductor layer facing away from the semiconductor substrate layer and on a side of the second gate line facing toward the semiconductor substrate layer; the first transparent conductive film is positioned on one side of the first doped semiconductor layer, which is away from the semiconductor substrate layer, and is positioned on one side of the first grid line, which is towards the semiconductor substrate layer; the second transparent conductive film is positioned on one side of the second doped semiconductor layer, which is away from the semiconductor substrate layer, and is positioned on one side of the second grid line, which is towards the semiconductor substrate layer;
wherein the conductivity type of the second doped semiconductor layer is opposite to the conductivity type of the first doped semiconductor layer.
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