CN116112002A - Comparison circuit - Google Patents
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- CN116112002A CN116112002A CN202310385333.XA CN202310385333A CN116112002A CN 116112002 A CN116112002 A CN 116112002A CN 202310385333 A CN202310385333 A CN 202310385333A CN 116112002 A CN116112002 A CN 116112002A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to the field of semiconductors, and provides a comparison circuit aiming at the problem that the time sequence of the comparison circuit is not easy to control, wherein the comparison circuit comprises a comparison unit and a reference unit, and the reference unit carries out consistency comparison on a first preset parameter and a second preset parameter to generate and output a first result signal; the comparison unit carries out consistency comparison on the first parameter to be processed and the second parameter to be processed and generates a second result signal; when the first result signal is in the second state, the second result signal is output as the target result signal, so that a correct parameter comparison function can be realized, and the time sequence of a comparison process can be optimized.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a comparison circuit.
Background
In integrated circuits, it is often referred to a comparison circuit that compares whether different parameters are identical. For a comparison circuit, the parameter comparison process takes a certain time to complete, i.e. the output signal of the comparison circuit needs to be after a period of time from the start of the comparison to be able to characterize the result of the parameter comparison. Because of the reasons of process, environmental parameters, etc., the time required for comparing parameters by the comparison circuit is also different, so that the timing control of the comparison circuit becomes a difficult problem.
Disclosure of Invention
The present disclosure provides a comparison circuit.
The technical scheme of the present disclosure is realized as follows:
in a first aspect, embodiments of the present disclosure provide a comparison circuit comprising:
the reference unit is configured to start at a first moment, compare the consistency of the first preset parameter with the consistency of the second preset parameter, and generate and output a first result signal; the first result signal is in a first state at the first moment, and if the first result signal is adjusted from the first state to a second state, the reference unit is represented to complete the consistency comparison;
the comparison unit is connected with the reference unit and is configured to carry out consistency comparison on the first parameter to be processed and the second parameter to be processed from the second moment to generate a second result signal; and outputting the second result signal as a target result signal when the first result signal is in a second state;
wherein the second time is no later than the first time.
In some embodiments, the comparing unit is further configured to mask the second result signal when the first result signal is in the first state.
In some embodiments, the first parameter to be processed and the second parameter to be processed have the same number of sub-parameters; the comparison unit comprises a main comparator and a first output device;
the main comparator is configured to compare the subparameters of the first parameter to be processed and the second parameter to be processed in a one-to-one correspondence manner from a second moment to generate the second result signal;
the first outputter is connected with the main comparator and the reference unit and is configured to receive the first result signal and the second result signal, perform logic operation on the first result signal and the second result signal and output the target result signal.
In some embodiments, the first preset parameter and the second preset parameter have the same number of sub-parameters, and the reference unit includes a reference comparator and a second outputter;
the reference comparator is specifically configured to compare the subparameter of the first preset parameter and the subparameter of the second preset parameter in a one-to-one correspondence manner from a first moment to generate an intermediate result signal;
the second output device is connected with the reference comparator and is configured to receive the intermediate result signal and a preset enabling signal; performing logic operation on the intermediate result signal and the preset enabling signal, and outputting the first result signal;
Wherein the reference comparator has the same structure as the main comparator, and the second output device has the same structure as the first output device; the preset enable signal is in an active state so that the level states of the first result signal and the intermediate result signal are the same.
In some embodiments, the main comparator is specifically configured to control the second result signal to maintain the third state unchanged if the sub-parameters of the first parameter to be processed and the sub-parameters of the second parameter to be processed are all the same; and if the sub-parameters of the first parameter to be processed and the sub-parameters of the second parameter to be processed have corresponding different sub-parameters, controlling the second result signal to be adjusted from a third state to a fourth state.
In some embodiments, the reference comparator is specifically configured to control the intermediate result signal to maintain the first state unchanged if the sub-parameters of the first preset parameter and the second preset parameter are all the same; if the sub-parameters of the first preset parameter and the sub-parameters of the second preset parameter have corresponding different sub-parameters, controlling the intermediate result signal to be adjusted from a first state to a second state;
Wherein the first preset parameter and the second preset parameter are set to be different in correspondence with only 1-bit subparameters.
In some embodiments, the master comparator comprises a plurality of first logic gates and 1 second logic gate;
the first input end of the ith first logic gate receives the ith subparameter of the first parameter to be processed, the second input end of the ith first logic gate receives the ith subparameter of the second parameter to be processed, the output end of each first logic gate is connected with the input end of the second logic gate, the output end of the second logic gate outputs a second result signal, and i is a positive integer;
wherein the first logic gate comprises at least one of the following devices: the second logic gate comprises at least one of the following devices: and gate, or gate, nand gate, nor gate.
In some embodiments, the reference comparator comprises a plurality of third logic gates and 1 fourth logic gate;
the first input end of the j-th third logic gate receives the j-th subparameter of the first preset parameter, the second input end of the j-th third logic gate receives the j-th subparameter of the second preset parameter, the output end of each third logic gate is connected with the input end of the fourth logic gate, the output end of the fourth logic gate outputs an intermediate result signal, and j is a positive integer;
Wherein the third logic gate is identical to the first logic gate and the fourth logic gate is identical to the second logic gate.
In some embodiments, the first outputter includes a first and gate with the first state being low and the second state being high;
the first input end of the first AND gate receives the first result signal, the second input end of the first AND gate receives the second result signal, and the output end of the first AND gate outputs the target result signal.
In some embodiments, the first output comprises a first or gate with the first state being high and the second state being low;
the first input end of the first OR gate receives the first result signal, the second input end of the first OR gate receives the second result signal, and the output end of the first OR gate outputs the target result signal.
In some embodiments, the comparing unit is further configured to reset the second result signal to a third state upon receiving a first reset signal;
the reference unit is further configured to reset the first result signal to a first state upon receiving a second reset signal.
In some embodiments, the master comparator is further configured to receive a first enable signal, and after the first enable signal is valid, begin performing a consistency comparison of a first parameter to be processed and a second parameter to be processed;
the reference comparator is further configured to receive a second enabling signal, and after the second enabling signal is valid, start to execute consistency comparison of the first preset parameter and the second preset parameter;
wherein the first enable signal and the second enable signal are the same signal when the first time and the second time are the same.
In some embodiments, the number of sub-parameters of the first preset parameter is the same as the number of sub-parameters of the first parameter to be processed, and the number of sub-parameters of the second preset parameter is the same as the number of sub-parameters of the second parameter to be processed.
In some embodiments, the comparing circuit is applied to the memory, and the comparing circuit is specifically configured to compare the target row address selected in the present operation with the stored a replaced row addresses, so as to determine whether the word line pointed to by the target row address is replaced; a is a positive integer;
Correspondingly, the number of the reference units is 1, and the number of the comparison units is A; the first to-be-processed parameters received by all the comparison units are the target row addresses, and the second to-be-processed parameters received by the a-th comparison unit are the a-th replaced row addresses; all the first result signals received by the comparison units come from the reference units, a and A are positive integers, and a is smaller than or equal to A.
In some embodiments, the memory further comprises a determination module;
the judging module is configured to receive a target result signals, and if the a target result signals are in a fourth state, it is determined that the word line pointed by the target row address is not replaced; if one of the target result signals is in the third state, determining that the word line pointed by the target row address is replaced;
the moment when the judging module enters the enabling state is later than the moment when the first result signal is adjusted to the second state.
The embodiment of the disclosure provides a comparison circuit which not only can realize a correct parameter comparison function, but also can optimize the time sequence of a comparison process.
Drawings
Fig. 1 is a schematic structural diagram of a comparison circuit according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of another comparison circuit according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of a specific structure of a comparison circuit according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a comparing unit according to an embodiment of the disclosure;
fig. 5 is a schematic diagram ii of a comparison unit according to an embodiment of the disclosure;
fig. 6 is a schematic diagram III of a comparison unit according to an embodiment of the disclosure;
fig. 7 is a schematic structural diagram of a comparing unit according to an embodiment of the disclosure;
FIG. 8 is a signal diagram of a comparison unit according to an embodiment of the disclosure;
fig. 9 is a schematic diagram fifth of a comparing unit according to an embodiment of the disclosure;
FIG. 10 is a schematic diagram of signal timing provided by an embodiment of the disclosure;
fig. 11 is an application scenario schematic diagram of a comparison circuit provided in an embodiment of the disclosure;
FIG. 12 is a schematic diagram of another signal timing provided by an embodiment of the disclosure;
fig. 13 is a schematic structural diagram of a memory according to an embodiment of the disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure. In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict. It should be noted that the term "first/second/third" in relation to the embodiments of the present disclosure is merely used to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if allowed, to enable the embodiments of the present disclosure described herein to be implemented in an order other than illustrated or described.
The following is a description of terms and relationships related to embodiments of the present disclosure:
dynamic random access memory (Dynamic Random Access Memory, DRAM);
a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM);
double Data Rate memory (DDR);
process, voltage, temperature (Process, voltage, temperature, PVT).
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In one embodiment of the present disclosure, referring to fig. 1, a schematic diagram of a comparison circuit 10 provided in an embodiment of the present disclosure is shown. As shown in fig. 1, the comparison circuit 10 includes:
a reference unit 11 configured to generate and output a first result signal by performing a consistency comparison between a first preset parameter and a second preset parameter from a first time; wherein, the first result signal is in a first state at the first moment, and if the first result signal is adjusted from the first state to the second state, the reference unit 11 is characterized to complete the consistency comparison;
a comparing unit 12, connected to the reference unit 11, configured to perform consistency comparison on the first parameter to be processed and the second parameter to be processed from the second moment, and generate a second result signal; and outputting the second result signal as a target result signal when the first result signal is in the second state;
Wherein the second time is no later than the first time.
It should be noted that the comparison circuit 10 may be applied to various electronic devices, such as a computing device, a storage device, a control device, and the like. In other words, the comparison circuit 10 provided in the embodiments of the present disclosure may be utilized to implement the function of parameter comparison in any integrated circuit.
It should be appreciated that, for the comparison unit 12, the level state of the second result signal may only characterize whether the first parameter to be processed and the second parameter to be processed are identical after the end of the consistency comparison, so that a certain time must be reserved after the second moment in time for the second result signal to be output as the target result signal. However, due to process effects, different comparison units 12 have different time consuming performance of the consistency comparison, which may cause the target result signal to be erroneous if the reservation time is too short; if the reservation time is longer, the performance of the whole circuit is reduced; in addition, the time taken to perform the consistency comparison in different environments (e.g., temperature, voltage) also varies for the same comparison unit 12, further exacerbating this problem.
In order to solve the above-described problem, a reference unit 11 is introduced, the reference unit 11 being able to simulate the time at which the comparison unit 12 performs the consistency comparison. It should be understood that the circuit structures of the reference unit 11 and the comparison unit 12 are identical, and not only are the process parameters similar in production and manufacturing, but also the working environment is identical in normal operation, so that the working performance of the reference unit 11 and the comparison unit 12 can be regarded as almost identical. That is, the operating parameters of the reference unit 11 and the comparison unit 12 will also exhibit the same degree of variation in PVT variations.
In addition, the second time is no later than the first time. Thus, with the comparison circuit 10, since the reference unit 11 and the comparison unit 12 start synchronously or the comparison unit 12 performs the coincidence comparison earlier than the reference unit 11, if the reference unit 11 completes the coincidence comparison, the comparison unit 12 must also complete the coincidence comparison at this time. Based on this, the output enable of the comparing unit 12 is performed with the first result signal of the second state, the second result signal at this point in time must already be able to characterize whether the first parameter to be processed and the second parameter to be processed are the same, so the obtained target result signal is correct, and the output timing of the comparing unit 12 can be maximized; in particular, because the architectures of the reference unit 11 and the comparison unit 12 are similar, even if PVT conditions change, the working parameters of the reference unit 11 and the comparison unit 12 are always similar, so that the control timing sequence of the comparison unit 12 can be adaptively adjusted along with the working environment, and the redundancy time is reduced to the greatest extent.
Here, if the second time is the same as the first time (within the error allowable range), the redundancy time is minimum, and the operation efficiency of the comparison circuit 10 is improved to the greatest extent; if the second moment is earlier than the first moment, the redundant time is more, the correctness of the target result signal is ensured to the greatest extent, and meanwhile flexible time sequence control is realized.
In some embodiments, the comparison unit 12 is further configured to mask the second result signal when the first result signal is in the first state.
Therefore, before consistency comparison is finished, the level state of the target result signal does not change along with the level state of the second result signal, meaningless level turnover is avoided, and energy consumption is saved.
It should be noted that, as shown in fig. 2, the first parameter to be processed TGTCode1[ N-1:0], the second parameter to be processed TGTCode2[ N-1:0], the first preset parameter DafCode1[ N-1:0], and the second preset parameter DafCode2[ N-1:0] are each composed of multiple sub-parameters. Note that the number of sub-parameters of the first parameter to be processed, the number of sub-parameters of the second parameter to be processed, the number of sub-parameters of the first preset parameter, and the number of sub-parameters of the second preset parameter are all the same.
In some embodiments, as shown in fig. 2, the comparison unit 12 includes a master comparator 121 and a first outputter 122;
a main comparator 121 configured to compare the sub-parameters of the first to-be-processed parameter and the sub-parameters of the second to-be-processed parameter in one-to-one correspondence from the second time instant, i.e., to compare whether TGTCode1[0] and TGTCode2[0] are the same, to compare whether TGTCode1[1] and TGTCode2[1] are the same … …, to compare whether TGTCode1[ N-1] and TGTCode2[ N-1] are the same, and to finally generate a second result signal;
The first outputter 122, connected to the main comparator 121 and the reference unit 11, is configured to receive the first result signal and the second result signal, perform a logic operation on the first result signal and the second result signal, and output a target result signal.
Here, the first result signal is used to enable the first outputter 122, thereby realizing timing control of the comparison unit 12.
As shown in fig. 2, the reference unit 11 includes a reference comparator 111 and a second outputter 112;
the reference comparator 111 is specifically configured to compare the sub-parameters of the first preset parameter DafCode1[ N-1:0] and the second preset parameter DafCode2[ N-1:0] in a one-to-one correspondence from the first time, that is, compare if DafCode1[0] and DafCode2[0] are the same, compare if DafCode1[1] and DafCode2[1] are the same … …, compare if DafCode1[ N-1] and DafCode2[ N-1] are the same, and finally generate an intermediate result signal;
a second output 112 connected to the reference comparator 111 and configured to receive the intermediate result signal and the preset enable signal; and performing logic operation on the intermediate result signal and a preset enabling signal, and outputting a first result signal.
The reference comparator 111 and the main comparator 121 have the same structure, and the second output 112 and the first output 122 have the same structure. During operation of the reference comparator 111, the preset enable signal is fixed in an active state such that the level states of the first result signal and the intermediate result signal are the same.
It should be noted that the preset enable signal is used to enable the second output 112. In this way, the structures of the reference unit 11 and the comparison unit 12 are identical, and the operation performances of the reference unit 11 and the comparison unit 12 are identical under various PVT conditions, and the slowest-case consistency comparison performed by the reference unit 11 (this point is further described later), i.e. the point in time when the first result signal transitions to the second state can ensure that the consistency comparison of the comparison unit 12 in each case is ended, thereby ensuring a correct execution of the comparison function.
The functions and specific structures of the main comparator 121 and the reference comparator 111 are explained below.
In a specific embodiment, as shown in fig. 3, the master comparator 121 includes a plurality of first logic gates 21 and 1 second logic gate 22; the first input end of the ith first logic gate 21 receives the ith sub-parameter TGTCode1[ i-1] of the first parameter to be processed, the second input end of the ith first logic gate 21 receives the ith sub-parameter TGTCode2[ i-1] of the second parameter to be processed, the output end of each first logic gate 21 is connected with the input end of the second logic gate 22, the output end of the second logic gate 22 outputs a second result signal, i is a positive integer, and i is less than or equal to N; wherein the first logic gate 21 comprises less than one of the following devices: the second logic gate 22 comprises at least one of the following: and gate, or gate, not gate, nand gate, nor gate.
At this time, as shown in fig. 3, the reference comparator 111 includes a plurality of third logic gates 23 and 1 fourth logic gate 24; the first input end of the j-th third logic gate 23 receives the j-th subparameter DafCode1[ j-1] of the first preset parameter, the second input end of the j-th third logic gate 23 receives the j-th subparameter DafCode2[ j-1] of the second preset parameter, the output end of each third logic gate 23 is connected with the input end of the fourth logic gate 24, the output end of the fourth logic gate 24 outputs an intermediate result signal, j is a positive integer, and j is less than or equal to N; the third logic gate 23 is the same as the first logic gate 21, and the fourth logic gate 24 is the same as the second logic gate 22.
Note that, the first logic gate 21, the second logic gate 22, the third logic gate 23, and the fourth logic gate 24 are each formed of transistors, and the designated nodes can be charged/discharged by controlling the switching states of the transistors, thereby completing the consistency comparison process, which is also a cause of requiring a certain time consumption for the consistency comparison.
It should be noted that the number of the first logic gates 21 is N, and the number of the third logic gates 23 is also N, so that the circuit structures of the reference comparator 111 and the main comparator 121 are identical, and the operation performances of the reference comparator 111 and the main comparator 121 are identical under different PVT conditions, so that the timing control effect can be maximally realized.
It should be appreciated that the comparison principle of the main comparator 121/reference comparator 111 is different when the specific devices selected for the logic gates are different, and several descriptions are provided below.
(1) In the first case, the main comparator 121 is specifically configured to control the second result signal to maintain the third state unchanged if the sub-parameters of the first parameter to be processed and the sub-parameters of the second parameter to be processed are all corresponding to the same; if the sub-parameters of the first to-be-processed parameter and the sub-parameters of the second to-be-processed parameter have different corresponding sub-parameters, controlling the second result signal to be adjusted from the third state to the fourth state; here, the logic potentials of the third state and the fourth state are different.
Similarly, since the circuit structures of the reference comparator 111 and the main comparator 121 are the same. Therefore, the reference unit 11 is specifically configured to control the first result signal to maintain the first state unchanged if the sub-parameters of the first preset parameter and the sub-parameters of the second preset parameter are all corresponding to the same; if the sub-parameters of the first preset parameter and the sub-parameters of the second preset parameter have different corresponding sub-parameters, the first result signal is controlled to be adjusted from the first state to the second state. Here, the first state=the third state, and the second state=the fourth state (this will be described later).
To achieve this, please refer to fig. 4 and 5, the following provides 2 options for logic gates. It should be understood that fig. 4 and 5 each show the circuit configuration of the comparing unit 12, but since the configurations of the reference unit 11 and the comparing unit 12 are the same, the configuration of the reference comparator 111 can also be adaptively understood with reference to fig. 4 and 5.
(a) Assuming that the first state=third state=0, the second state=fourth state=1, please refer to fig. 4, the first logic gate 21 and the third logic gate 23 may employ an exclusive or gate, and the second logic gate 22 and the fourth logic gate 24 may employ an or gate. Specifically, if TGTCode1[ i ] is different from TGTCode2[ i ], the output signal A [ i-1] of the ith exclusive OR gate gradually changes from 0 to 1, so that the output signal of the OR gate is 1; if TGTCode1[ N-1:0] and TGTCode2[ N-1:0] are all corresponding to the same, then the output signals A [ N-1:0] of the N exclusive OR gates are all 0, so that the output signals of the OR gates are 0.
(b) Assuming that the first state=third state=1, the second state=fourth state=0, please refer to fig. 5, the first logic gate 21 and the third logic gate 23 may be an exclusive or gate, and the second logic gate 22 and the fourth logic gate 24 may be an exclusive or gate. Specifically, if TGTCode1[ i ] is different from TGTCode2[ i ], the output signal B [ i-1] of the ith exclusive OR gate gradually changes from 1 to 0, so that the output signal of the AND gate is 0; if TGTCode1[ N-1:0] and TGTCode2[ N-1:0] are all corresponding to the same, then the output signals B [ N-1:0] of the N exclusive OR gates are all 1, so that the output signals of the AND gates are 1.
Note that the more sub-parameters that are correspondingly different between the first parameter to be processed and the second parameter to be processed, the shorter the time it takes for the second result signal to be adjusted from the third state to the fourth state. The reasons are as follows: taking fig. 4 as an example, on the one hand, if there are different sub-parameters corresponding to TGTCode1[ N-1:0] and TGTCode2[ N-1:0], the output end of the or gate needs to be changed from 0 to 1, specifically, the output end of the or gate is charged by a power signal; therefore, if there are more sub-parameters corresponding to TGTCode1[ N-1:0] and TGTCode2[ N-1:0], the more paths the power supply signal charges the output terminal of the or gate, the faster the level raising speed of the output terminal of the or gate, that is, the shorter the time it takes for the second result signal to be adjusted from the third state to the fourth state; on the other hand, although the structure theory of different exclusive-or gates is the same, slight differences exist in the working parameters of the different exclusive-or gates due to reasons such as technology, and the speed of gradually changing from 0 to 1 at the output end of the exclusive-or gate is different for different input signals; if the more different subparameters are corresponding to TGTCode1[ N-1:0] and TGTCode2[ N-1:0], the output 1 of the fastest one of the more exclusive OR gates can lead to the output of the OR gate being 1; conversely, if TGTCode1[ N-1:0] and TGTCode2[ N-1:0] have fewer sub-parameters, then the output of 1, which can only depend on the "fastest one of fewer exclusive or gates", results in an output of 1 or gate, and the high probability speed is slow. Fig. 5 is also similar.
In this way, the time taken to perform a consistency comparison is highest when the first parameter to be processed and the second parameter to be processed differ by only 1 bit. Similarly, if there are more sub-parameters corresponding to different ones of the first preset parameter and the second preset parameter, the time taken for the first result signal to be adjusted from the first state to the second state is shorter. Meanwhile, since the reference comparator 111 needs to simulate the longest time of the consistency process, the first preset parameter and the second preset parameter are fixedly set to be different and only 1-bit sub-parameters are correspondingly different.
It should be noted that the first preset parameter and the second preset parameter may be fixed; alternatively, the first preset parameter and the second preset parameter may vary, but it is necessary to ensure that there is a 1-bit sub-parameter difference between the two. In this way, the operating parameters of the reference comparator 111 and the main comparator 121 for performing the consistency comparison are the same, and the consistency comparison of the reference comparator 111 is already the slowest case, at whatever PVT, it can be ensured that the main comparator 121 in all cases must have completed the consistency comparison.
(2) In the second case, the main comparator 121 is specifically configured to control the second result signal to maintain the third state unchanged if the sub-parameters of the first to-be-processed parameter and the sub-parameters of the second to-be-processed parameter are all correspondingly different; and if the first preset parameter and the second preset parameter have the same corresponding sub-parameters, controlling the second result signal to be adjusted from the third state to the fourth state.
Similarly, the reference comparator 111 is specifically configured to control the first result signal to maintain the first state unchanged if the sub-parameters of the first parameter to be processed and the sub-parameters of the second parameter to be processed are all correspondingly different; and if the sub-parameters of the first preset parameter and the sub-parameters of the second preset parameter have the same corresponding sub-parameters, controlling the first result signal to be adjusted from the first state to the second state.
If the first parameter to be processed and the second parameter to be processed are corresponding to the same sub-parameters, the time for adjusting the second result signal to the fourth state is shorter.
To achieve this, 2 options for logic gates are provided below.
(c) Assuming that the first state=third state=0, the second state=fourth state=1, please refer to fig. 6, the first logic gate 21 and the third logic gate 23 may be an exclusive or gate, and the second logic gate 22 and the fourth logic gate 24 may be an exclusive or gate. Specifically, if TGTCode1[ i ] is the same as TGTCode2[ i ], the output signal C [ i-1] of the ith exclusive OR gate gradually changes from 0 to 1, so that the output signal of the OR gate is 1; if TGTCode1[ N-1:0] and TGTCode2[ N-1:0] are all corresponding different, then the output signals C [ N-1:0] of the N exclusive OR gates are all 0, so that the output signals of the OR gates are 0.
(d) Assuming that the first state=third state=1, the second state=fourth state=0, please refer to fig. 7, the first logic gate 21 and the third logic gate 23 may employ an exclusive or gate, and the second logic gate 22 and the fourth logic gate 24 may employ an and gate. Specifically, if TGTCode1[ i ] is the same as TGTCode2[ i ], the output signal D [ i-1] of the ith exclusive or gate gradually changes from 1 to 0, so that the output signal of the and gate is 0; if TGTCode1[ N-1:0] and TGTCode2[ N-1:0] are all correspondingly different, then the output signals D [ N-1:0] of the N exclusive OR gates are all 1, so that the output signals of the AND gates are 1.
Similarly, the more sub-parameters corresponding to the same parameters are between the first parameter to be processed and the second parameter to be processed, the shorter the time required for adjusting the second result signal from the third state to the fourth state. Thus, the first preset parameter and the second preset parameter are fixedly set such that only 1-bit sub-parameters are correspondingly identical. The first preset parameter and the second preset parameter may be fixed; alternatively, the first preset parameter and the second preset parameter may vary, but it is necessary to ensure that there is only a 1-bit sub-parameter between the two. In this way, the consistency comparison by the reference comparator 111 is already the longest time consuming, and it can be ensured that the main comparator 121 must have also completed the consistency comparison at this time.
The structure of the first and second outputters 122 and 112 will be described below.
In one possibility, referring to fig. 4 or fig. 6, in the case that the first state is low and the second state is high, the first output 122 includes a first and gate; the first input end of the first AND gate receives the first result signal, the second input end of the first AND gate receives the second result signal, and the output end of the first AND gate outputs the target result signal.
In another possibility, referring to fig. 5 or fig. 7, in the case that the first state is high and the second state is low, the first output 122 includes a first or gate; the first input end of the first OR gate receives the first result signal, the second input end of the first OR gate receives the second result signal, and the output end of the first OR gate outputs the target result signal.
In some embodiments, the comparing unit 12 is configured to reset the second result signal to the third state upon receiving the first reset signal; the reference unit 11 is further configured to reset the first result signal to the first state upon receiving the second reset signal; here, the first reset signal and the second reset signal may be the same signal.
In some embodiments, as shown in fig. 2 or 3, the master comparator 121 is further configured to receive a first enable signal, and after the first enable signal is valid, start to perform a consistency comparison of the first parameter to be processed and the second parameter to be processed; the reference comparator 111 is further configured to receive a second enable signal, and after the second enable signal is valid, start to perform a consistency comparison of the first preset parameter and the second preset parameter; wherein, when the first time and the second time are the same, the first enabling signal and the second enabling signal are the same signal.
Here, as shown in fig. 4 to 7, the first enable signal is specifically used to enable the first logic gate 21, and the second enable signal is specifically used to enable the third logic gate 23.
A scenario is provided: the first enable signal and the second enable signal are both active high signals, the first state=third state=0, the second state=fourth state=1, and the overall operation of the comparison circuit 10 is described.
Firstly, after the system is powered on, the comparison circuit 10 performs initialization, that is, the first reset signal and the second reset signal are valid, so that the first result signal and the second result signal are both low level; in addition, the first enabling signal and the second enabling signal are also in a low level;
then, when the first parameter to be processed and the second parameter to be processed need to be compared, the first enable signal and the second enable signal are turned to high level, the reference comparator 111 and the main comparator 121 start to perform consistency comparison, and since the first preset parameter and the second preset parameter are fixed and different, the first result signal is gradually adjusted from low level to high level, and after the first result signal is adjusted to high level, the first output device 122 is enabled to output the second result signal as the target result signal;
Finally, after the comparison flow is finished, the first enabling signal and the second enabling signal are turned to be low level, and the first reset signal and the second reset signal are valid, so that the first result signal and the second result signal are reset to be low level and wait for the next work.
In particular, if the first time instant and the second time instant are the same, the first enable signal and the second enable signal may be the same signal; if the first time is later than the second time, the first enabling signal and the second enabling signal can be obtained from the homologous signal respectively with different delays.
From the above, it can be seen that the embodiment of the disclosure provides a comparison circuit 10, which can adaptively control the time sequence in the comparison process, adaptively generate the optimal time sequence under different PVT conditions, and ensure that the comparison function is correct and simultaneously realize the optimal time sequence. Specifically, in the comparison circuit 10, a reference unit having the same structure as the comparison unit is provided, and the comparison unit is output enabled by using the first result signal output by the reference unit, so that not only the normal execution of the comparison function is ensured, but also the redundancy time is reduced, and the optimal timing control is realized.
The comparison circuit 10 described above may be used in various types of integrated circuits, such as volatile or nonvolatile memory. Such as DRAM, SDRAM, DDR, LPDDR, etc. In another embodiment provided by the present disclosure, a specific application of the comparison circuit 10 is provided for a scenario in which the row redundancy logic function in the DRAM is implemented.
First, the row redundancy function in DRAM is to repair damaged memory rows (or word lines) with redundant rows to improve the yield of chips. Thus, the DRAM needs to compare the target row address (i.e., the input row address) with the address bank of the defective row each time before performing certain operations (e.g., activate operations, read operations, write operations, etc.) on the selected memory row: (1) If the target row address is different from all damaged rows in the address library, the storage row is not repaired, and the operation can be directly performed by taking the target row address as final addressing information; (2) If the target row address is the same as a defective row in the address library, indicating that the memory row is repaired, it is necessary to relocate it to a redundant row that repairs the memory row for operation.
Thus, the DRAM needs to implement a comparison between the target row address and the repaired row address (i.e., the damaged row) using the address comparator. Referring to fig. 8 and 9, a schematic diagram of an address comparator is provided. The Address comparator may be regarded as being composed of a plurality of exclusive or gates, an or gate, and specifically receives a target Row Address Row (including multi-bit sub-signals, which may be denoted as Row Address [ N-1:0 ]), a repaired Row Address Row to Repair (including multi-bit sub-signals, which may be denoted as Row to Repair [ N-1:0 ]), an Address enable signal Address Valid, and a Compare enable signal Address Valid, and after the Address enable signal Address Valid is Valid, the Address comparator starts to perform a consistency comparison of the target Row Address and the repaired Row Address Row to Repair; meanwhile, the output end of the address comparator is connected with an AND gate, and the AND gate outputs a comparison Result Compare Result as a target Result signal after the comparison enabling signal Compare Valid. In other words, the Address Valid signal corresponds to the first enable signal/the second enable signal, and the Compare Valid signal corresponds to the preset enable signal (with respect to the reference comparator)/the first result signal (with respect to the main comparator). In particular, the Row address Row to Repair is one of the addresses in the address bank of the defective Row, and a plurality of similar address comparators are present in the DRAM, thereby achieving a traversal comparison of the addresses.
Referring to fig. 10, a schematic diagram of signal timing of the address comparator is provided. As shown in fig. 10, the Compare enable signal Compare Valid signal needs to come after the comparison is completed (i.e., the Compare Result has Valid parameters) otherwise a Result error may Result. Meanwhile, the time required for the Address comparator to perform signal comparison is related to the input Address, and the more different subparameters in the input Address (namely, row to reply and Row Address), the faster the comparison speed is, namely, the smaller the Delay in fig. 10 is.
In short, it takes a certain time to compare the target Row Address Row and the repaired Row Address Row to Repair. In order to ensure the correctness of the comparison result, a certain waiting time is reserved to read the comparison result, the reserved waiting time is too short, the risk of errors exists, and the reserved waiting time is too long, so that the performance is affected.
The comparison circuit 10 provided by the embodiments of the present disclosure can solve this problem. That is, the comparison circuit 10 is applied to the memory, and the comparison circuit 10 is specifically configured to compare the target row address selected in the present operation with the stored a replaced row addresses to determine whether the word line to which the target row address points is replaced; a is a positive integer.
Correspondingly, as shown in fig. 11, the number of the reference units 11 is 1, and the number of the comparison units 12 is a, that is, the comparison units 12_1 to 12_a; all the first parameters to be processed received by the comparison unit 12 refer to the target Row Address (which has N subparameters, namely, may be specifically expressed as Row Address [ N-1:0 ]), and the second parameters to be processed received by the a-th comparison unit 12_a refer to the a-th replaced Row Address Row to repair_a (which also has N subparameters Row to repair_a [ N-1:0 ]); all the comparison units 12 receive the first Result signal Compare Result1 from the reference unit 11, a and A are positive integers, and a is less than or equal to A.
That is, the 1 st comparing unit 12_1 compares the N-bit subparameter Row Address [ N-1:0] of the target Row Address Row Address with the N-bit subparameter Row to Repair_1[N-1:0 of the 1 st replaced Row Address Row to Repair_1 in one-to-one correspondence; the 2 nd comparing unit 12_2 compares … … the N-bit subparameter Row Address [ N-1:0] of the target Row Address and the N-bit subparameter Row to repair_2[ N-1:0] of the 2 nd replaced Row Address Row to repair_2[ N-1:0] in one-to-one correspondence, and the first Result signal computer Result1 output by the reference unit 11 is used for enabling output of all the comparing units 12.
It should be noted that, the two input signals of the reference unit 11 are fixed with 1-bit different preset addresses (i.e. the first preset parameter and the second preset parameter), for example, 0x0000 and 0x0001 (x is a plurality of 0 s, depending on the total number of bits of the addresses), the comparison enable signal Compare Valid of the reference unit 11 is fixed to be high level, and the first Result signal Compare Result1 outputted by the reference unit 11 is used as the comparison enable signal Compare Valid of all the comparison units 12.
Referring to fig. 12, after the Address Valid signal is asserted, the reference unit 11 starts comparing, for example, 0x0000 and 0x0001, while the comparison unit 12 starts comparing the target row Address and the repaired row Address; since the comparison enable signal Compare Valid of the reference unit 11 is fixed to be at high level, the first Result signal Compare Result1 outputted by the reference unit 11 gradually becomes at high level along with the comparison process, which indicates that the consistency comparison of the reference unit 11 is ended; the comparison unit 12, after receiving the high-level first Result signal component Result1, has the internal comparison Result component Result (corresponding to the aforementioned second Result signal) already representing whether the target row address and the repaired row address are identical, and can thus output them as the target Result signal. Thus, since the comparing unit 12 and the reference unit 11 have the same structure, and the reference unit 11 performs the slowest consistency comparison under such PVT conditions, the output result of the reference unit 11 is used to output the output enable of the comparing unit 12, so that not only the worst case timing can be satisfied, but also the adaptation can be performed according to the PVT conditions.
In particular, in this application scenario, the specific functions of the a-th comparing unit 12 are: if the N subparameters Row Address [ N-1:0] of the Row Address signal and the N subparameters Row to Repair_a [ N-1:0] of the a replaced Row Address are corresponding to the same, controlling the a target result signal to maintain the third state unchanged; if the N subparameters Row Address [ N-1:0] of the Row Address signal and the N subparameters Row to Repair_a [ N-1:0] of the a-th replaced Row Address are not completely corresponding to the same, controlling the a-th target result signal to be adjusted from the third state to the fourth state.
In some embodiments, the memory further includes a determination module (not shown); the judging module is configured to receive the A target result signals, and if the A target result signals are in a fourth state, the word line pointed by the target row address is determined not to be replaced; if one of the target result signals is in the third state, determining that the word line pointed by the target row address is replaced; the moment when the judging module enters the enabling state is later than the moment when the first result signal is adjusted to the second state.
In this way, the reference unit 11 and the comparison unit 12 have the same circuit structure and port, but the Address input of the reference unit 11 is a fixed value, the comparison enable signal Compare Valid is also fixed at a high level, and after the Address enable signal Address Valid arrives (the port of the reference unit 11 and the port of the comparison unit 12 are the same signal), the reference unit 11 outputs a comparison result after a delay, and the comparison result is the comparison enable signal Compare Valid of the other comparison unit 12, so that the worst case timing can be satisfied exactly.
In yet another embodiment of the present disclosure, reference is made to fig. 13, which illustrates a schematic diagram of the composition and structure of a memory 30 provided by an embodiment of the present disclosure. As shown in fig. 13, the memory 30 includes at least the aforementioned comparison circuit 10.
The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments. The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure.
Claims (15)
1. A comparison circuit, the comparison circuit comprising:
the reference unit is configured to start at a first moment, compare the consistency of the first preset parameter with the consistency of the second preset parameter, and generate and output a first result signal; the first result signal is in a first state at the first moment, and if the first result signal is adjusted from the first state to a second state, the reference unit is represented to complete the consistency comparison;
the comparison unit is connected with the reference unit and is configured to carry out consistency comparison on the first parameter to be processed and the second parameter to be processed from the second moment to generate a second result signal; and outputting the second result signal as a target result signal when the first result signal is in a second state;
wherein the second time is no later than the first time.
2. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,
the comparing unit is further configured to mask the second result signal when the first result signal is in the first state.
3. The circuit of claim 1, wherein the first parameter to be processed and the second parameter to be processed have the same number of sub-parameters; the comparison unit comprises a main comparator and a first output device;
The main comparator is configured to compare the subparameters of the first parameter to be processed and the second parameter to be processed in a one-to-one correspondence manner from a second moment to generate the second result signal;
the first outputter is connected with the main comparator and the reference unit and is configured to receive the first result signal and the second result signal, perform logic operation on the first result signal and the second result signal and output the target result signal.
4. A circuit according to claim 3, wherein the first preset parameter and the second preset parameter have the same number of sub-parameters, the reference unit comprising a reference comparator and a second output;
the reference comparator is specifically configured to compare the subparameter of the first preset parameter and the subparameter of the second preset parameter in a one-to-one correspondence manner from a first moment to generate an intermediate result signal;
the second output device is connected with the reference comparator and is configured to receive the intermediate result signal and a preset enabling signal; performing logic operation on the intermediate result signal and the preset enabling signal, and outputting the first result signal;
Wherein the reference comparator has the same structure as the main comparator, and the second output device has the same structure as the first output device; the preset enable signal is in an active state so that the level states of the first result signal and the intermediate result signal are the same.
5. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
the main comparator is specifically configured to control the second result signal to maintain a third state unchanged if the sub-parameters of the first parameter to be processed and the sub-parameters of the second parameter to be processed are all the same; and if the sub-parameters of the first parameter to be processed and the sub-parameters of the second parameter to be processed have corresponding different sub-parameters, controlling the second result signal to be adjusted from a third state to a fourth state.
6. The circuit of claim 5, wherein the circuit further comprises a logic circuit,
the reference comparator is specifically configured to control the intermediate result signal to maintain the first state unchanged if the sub-parameters of the first preset parameter and the second preset parameter are all the same; if the sub-parameters of the first preset parameter and the sub-parameters of the second preset parameter have corresponding different sub-parameters, controlling the intermediate result signal to be adjusted from a first state to a second state;
Wherein the first preset parameter and the second preset parameter are set to be different in correspondence with only 1-bit subparameters.
7. The circuit of claim 4, wherein the master comparator comprises a plurality of first logic gates and 1 second logic gate;
the first input end of the ith first logic gate receives the ith subparameter of the first parameter to be processed, the second input end of the ith first logic gate receives the ith subparameter of the second parameter to be processed, the output end of each first logic gate is connected with the input end of the second logic gate, the output end of the second logic gate outputs a second result signal, and i is a positive integer;
wherein the first logic gate comprises at least one of the following devices: the second logic gate comprises at least one of the following devices: and gate, or gate, nand gate, nor gate.
8. The circuit of claim 7, wherein the reference comparator comprises a plurality of third logic gates and 1 fourth logic gate;
the first input end of the j-th third logic gate receives the j-th subparameter of the first preset parameter, the second input end of the j-th third logic gate receives the j-th subparameter of the second preset parameter, the output end of each third logic gate is connected with the input end of the fourth logic gate, the output end of the fourth logic gate outputs an intermediate result signal, and j is a positive integer;
Wherein the third logic gate is identical to the first logic gate and the fourth logic gate is identical to the second logic gate.
9. A circuit according to claim 3, wherein the first output comprises a first and gate in the case that the first state is low and the second state is high;
the first input end of the first AND gate receives the first result signal, the second input end of the first AND gate receives the second result signal, and the output end of the first AND gate outputs the target result signal.
10. A circuit according to claim 3, wherein the first output comprises a first or gate with the first state high and the second state low;
the first input end of the first OR gate receives the first result signal, the second input end of the first OR gate receives the second result signal, and the output end of the first OR gate outputs the target result signal.
11. The circuit of claim 3, wherein the circuit comprises a plurality of transistors,
the comparing unit is further configured to reset the second result signal to a third state when receiving a first reset signal;
The reference unit is further configured to reset the first result signal to a first state upon receiving a second reset signal.
12. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
the main comparator is further configured to receive a first enabling signal, and after the first enabling signal is valid, start to execute consistency comparison of a first parameter to be processed and a second parameter to be processed;
the reference comparator is further configured to receive a second enabling signal, and after the second enabling signal is valid, start to execute consistency comparison of the first preset parameter and the second preset parameter;
wherein the first enable signal and the second enable signal are the same signal when the first time and the second time are the same.
13. The circuit of claim 1, wherein the number of sub-parameters of the first preset parameter and the number of sub-parameters of the first parameter to be processed are the same, and the number of sub-parameters of the second preset parameter and the number of sub-parameters of the second parameter to be processed are the same.
14. The circuit according to any one of claims 1-13, wherein the comparing circuit is applied to a memory, and wherein the comparing circuit is specifically configured to compare a target row address selected by the present operation with the stored a replaced row addresses to determine whether a word line pointed to by the target row address is replaced; a is a positive integer;
Correspondingly, the number of the reference units is 1, and the number of the comparison units is A; the first to-be-processed parameters received by all the comparison units are the target row addresses, and the second to-be-processed parameters received by the a-th comparison unit are the a-th replaced row addresses; all the first result signals received by the comparison units come from the reference units, a and A are positive integers, and a is smaller than or equal to A.
15. The circuit of claim 14, wherein the memory further comprises a determination module;
the judging module is configured to receive a target result signals, and if the a target result signals are in a fourth state, it is determined that the word line pointed by the target row address is not replaced; if one of the target result signals is in the third state, determining that the word line pointed by the target row address is replaced;
the moment when the judging module enters the enabling state is later than the moment when the first result signal is adjusted to the second state.
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Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150710A (en) * | 1995-08-11 | 1997-05-28 | 三星电子株式会社 | Method and apparatus for preventing excessive current flow in motor |
| US6512704B1 (en) * | 2001-09-14 | 2003-01-28 | Sun Microsystems, Inc. | Data strobe receiver |
| US20110006804A1 (en) * | 2009-07-10 | 2011-01-13 | Gay James G | Circuit for controlling data communication with synchronous storage circuitry and method of operation |
| CN102288835A (en) * | 2011-06-16 | 2011-12-21 | 四川和芯微电子股份有限公司 | Signal detection circuit and method |
| US20160094226A1 (en) * | 2014-09-25 | 2016-03-31 | Yang Wang | Power switch control between usb and wireless power system |
| CN105679226A (en) * | 2015-12-29 | 2016-06-15 | 格科微电子（上海）有限公司 | Power good signal output method and device |
| CN106535412A (en) * | 2016-12-21 | 2017-03-22 | 贵州恒芯微电子科技有限公司 | Digital-analogue dimming circuit with shared port |
| CN107294058A (en) * | 2017-06-27 | 2017-10-24 | 合肥尚硕新能源有限公司 | A kind of overvoltage undervoltage detection circuit applied to solar energy power accumulating power supply |
| CN109584917A (en) * | 2013-11-07 | 2019-04-05 | 瑞萨电子株式会社 | Semiconductor devices |
| CN109910616A (en) * | 2019-03-21 | 2019-06-21 | 奇瑞新能源汽车技术有限公司 | A kind of heating protection circuit of power system of electric automobile |
| US20200143090A1 (en) * | 2018-11-01 | 2020-05-07 | Nvidia Corporation | Protecting circuits from hacking using a digital reset detector |
| CN210490451U (en) * | 2019-09-10 | 2020-05-08 | 沈阳微控新能源技术有限公司 | IPM protection system for flywheel energy storage device |
| CN111241780A (en) * | 2018-11-29 | 2020-06-05 | 御芯微电子(厦门)有限公司 | Method for preventing fault injection control signal for integrated circuit and integrated circuit |
| CN210925503U (en) * | 2020-02-24 | 2020-07-03 | 长鑫存储技术(上海)有限公司 | Repair circuit and memory |
| CN111641187A (en) * | 2020-06-12 | 2020-09-08 | 上海艾为电子技术股份有限公司 | Overcurrent protection circuit, overcurrent protection method and electronic equipment |
| US20220416773A1 (en) * | 2020-12-28 | 2022-12-29 | Texas Instruments Incorporated | Deglitching circuit |
| CN115580375A (en) * | 2022-12-09 | 2023-01-06 | 杭州飞仕得科技股份有限公司 | Signal transmission circuit and control method |
| WO2023035411A1 (en) * | 2021-09-10 | 2023-03-16 | 长鑫存储技术有限公司 | Signal shielding circuit and semiconductor memory |
| CN115903977A (en) * | 2022-11-03 | 2023-04-04 | 广州大学 | DLDO circuit for eliminating LCO oscillation by adopting logic control |
-
2023
- 2023-04-12 CN CN202310385333.XA patent/CN116112002B/en active Active
Patent Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150710A (en) * | 1995-08-11 | 1997-05-28 | 三星电子株式会社 | Method and apparatus for preventing excessive current flow in motor |
| US6512704B1 (en) * | 2001-09-14 | 2003-01-28 | Sun Microsystems, Inc. | Data strobe receiver |
| US20110006804A1 (en) * | 2009-07-10 | 2011-01-13 | Gay James G | Circuit for controlling data communication with synchronous storage circuitry and method of operation |
| CN102288835A (en) * | 2011-06-16 | 2011-12-21 | 四川和芯微电子股份有限公司 | Signal detection circuit and method |
| CN109584917A (en) * | 2013-11-07 | 2019-04-05 | 瑞萨电子株式会社 | Semiconductor devices |
| US20160094226A1 (en) * | 2014-09-25 | 2016-03-31 | Yang Wang | Power switch control between usb and wireless power system |
| CN105679226A (en) * | 2015-12-29 | 2016-06-15 | 格科微电子（上海）有限公司 | Power good signal output method and device |
| CN106535412A (en) * | 2016-12-21 | 2017-03-22 | 贵州恒芯微电子科技有限公司 | Digital-analogue dimming circuit with shared port |
| CN107294058A (en) * | 2017-06-27 | 2017-10-24 | 合肥尚硕新能源有限公司 | A kind of overvoltage undervoltage detection circuit applied to solar energy power accumulating power supply |
| US20200143090A1 (en) * | 2018-11-01 | 2020-05-07 | Nvidia Corporation | Protecting circuits from hacking using a digital reset detector |
| CN111241780A (en) * | 2018-11-29 | 2020-06-05 | 御芯微电子(厦门)有限公司 | Method for preventing fault injection control signal for integrated circuit and integrated circuit |
| CN109910616A (en) * | 2019-03-21 | 2019-06-21 | 奇瑞新能源汽车技术有限公司 | A kind of heating protection circuit of power system of electric automobile |
| CN210490451U (en) * | 2019-09-10 | 2020-05-08 | 沈阳微控新能源技术有限公司 | IPM protection system for flywheel energy storage device |
| CN210925503U (en) * | 2020-02-24 | 2020-07-03 | 长鑫存储技术(上海)有限公司 | Repair circuit and memory |
| CN111641187A (en) * | 2020-06-12 | 2020-09-08 | 上海艾为电子技术股份有限公司 | Overcurrent protection circuit, overcurrent protection method and electronic equipment |
| US20220416773A1 (en) * | 2020-12-28 | 2022-12-29 | Texas Instruments Incorporated | Deglitching circuit |
| WO2023035411A1 (en) * | 2021-09-10 | 2023-03-16 | 长鑫存储技术有限公司 | Signal shielding circuit and semiconductor memory |
| CN115903977A (en) * | 2022-11-03 | 2023-04-04 | 广州大学 | DLDO circuit for eliminating LCO oscillation by adopting logic control |
| CN115580375A (en) * | 2022-12-09 | 2023-01-06 | 杭州飞仕得科技股份有限公司 | Signal transmission circuit and control method |
Non-Patent Citations (1)
| Title |
|---|
| 元国军: "基于自适应时序匹配的低延迟寄存器堆", 《高技术通讯》 * |
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| CN116112002B (en) | 2023-07-25 |
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