CN105679226A - Power good signal output method and device - Google Patents
Power good signal output method and device Download PDFInfo
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- CN105679226A CN105679226A CN201511006305.4A CN201511006305A CN105679226A CN 105679226 A CN105679226 A CN 105679226A CN 201511006305 A CN201511006305 A CN 201511006305A CN 105679226 A CN105679226 A CN 105679226A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a power good signal output method and a power good signal output device. The power good signal output device comprises a voltage dividing module, a forward direction judgment module or a reverse direction judgment module, a logic and gate, wherein the voltage dividing module is provide with an enable switch and is used for converting an input power supply voltage into a detection divided voltage to be judged, and the enable switch responds to an enable signal; the detection divided voltage is judged by means of the forward direction judgment module when the enable switch is connected to a position closed to a high potential end in the voltage dividing module, the detection divided voltage is judged by means of the reverse direction judgment module when the enable switch is connected to a position closed to a low potential end in the voltage dividing module, and a marking signal is output; and the logic and gate is used for processing the enable signal and the marking signal, and outputting a power good signal. The power good signal output method and the power good signal output device can achieve zero-power-consumption static current in a deep sleep or shutdown mode, can solve the competition and risk problems caused by different time delay of the enable switch and the judgment module, eliminates burr phenomenon in actual response output, and increases judgment accuracy of a power good state.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of power good signal output intent and device.
Background technology
Along with becoming increasingly popular of smart mobile phone, the display effect of mobile intelligent terminal be it is also proposed increasingly higher requirement by people, and the high-resolution high performance display effect of widescreen becomes main flow. Therefore, the display driver chip function of handheld device and performance it is also proposed increasingly higher challenge.
The electric charge pump in multi-output power supply administrative unit critically important in display driver chip provides positive back bias voltage for liquid crystal, in the process of electrifying startup or shutdown power down, electric charge pump module needs the discharge and recharge of several clock cycle, can be only achieved stable state, therefore, the state of the positive negative output voltage of multichannel of detection electric charge pump module, thus orderly start load circuit is particularly important.
On the other hand, raising along with screen of hand-held device resolution, to WVGA, the widescreen high resolution displaies such as HD, when frame frequency is certain, output is driven to reach 95% steady-state value within 1/3 row time the voltage of the GAMMA curvature correction that display needs, so along with the increase of pixel-matrix, electric current is also by proportional increase, therefore, when big electric current, the exception of detection output voltage/electric current, so that starting protection circuit or prevent latch-up(latch-up) etc. other response be particularly important, so stability and capability of fast response to detection the good output unit of power supply of fed-back output voltage and current status propose higher challenge.
The power sense circuit structure of display driver chip is generally as shown in Figure 1; multi-output power supply administrative unit 10 exports multiple supply voltage VDD1 ~ VDDN; supply voltage VDD1 ~ VDDN is detected by each subelement 20 of the good output unit of power supply respectively; if meeting the state of good output, the good signal VDD1_POWERGOOD ~ VDDN_POWERGOOD of out-put supply respectively; then all of power good signal is carried out logic phase with; judge that all of power supply exports all in the state of good output with this, thus coming starting load or protection circuit unit 30.
Fig. 2 illustrates that existing power supply exports well the module map of subelement, and Fig. 3, Fig. 4 illustrate that existing power supply exports well the circuit diagram of two exemplary embodiments of subelement. Existing power supply exports well subelement 20 and includes division module 21, it is judged that module 22 and logical AND gate 23. Wherein, multi-output power supply administrative unit 10 the supply voltage VDDN inputted is converted to the detection dividing potential drop VDDN ' being available for judging by division module 21 by electric resistance partial pressure. In order to reduce the overall power of display driver chip, division module 21 is provided with enable switch 24, enables switch 24 in response to enabling signal, by enabling the control of signal EN, can meeting under deep sleep or shutdown mode, the quiescent dissipation of divider resistance string is zero. Judge module 22 is used for judging detection dividing potential drop VDDN ', output identification signal FLAG. Judge module 22 can include the schmitt inverter 25 of single or multiple series connection, and the realization of schmitt inverter is based entirely on digital CMOS Complementary logic circuitry, is absent from the impact of quiescent dissipation; Complementary PMOS that relatively precision is realized by physical circuit and the size ratio of NMOS tube and chip internal LDO(low-dropout regulator) the power supply voltage DVDD that produces determines, do not need extra reference voltage generating circuit, without the impact being subject to offset voltage. Logical AND gate 23 will be for enabling signal EN and marking signal FLAG phase and, the good signal VDDN_POWERGOOD of out-put supply.
For the supply voltage VDDN that inputted by multi-output power supply administrative unit 10 on the occasion of (such as 3.0V), the positive threshold voltage assuming judge module 22 is 1.6V, negative threshold voltage is 0.8V, existing power supply shown in Fig. 3 exports well the signal response output procedure of subelement as it is shown in figure 5, specifically include such as the next stage:
The 0-t1 stage: enabling signal EN is low level, namely now the enable switch 24 of division module 21 disconnects, namely one end level of the resistance string for detecting disconnects with positive voltage end, and the other end couples with ground terminal all the time, dividing potential drop VDDN ' is equal to ground wire voltage (0V) in detection, after the schmitt inverter 25 of judge module 22 judges, the marking signal FLAG of output is high level, logical AND gate 23 will enable signal EN with marking signal FLAG phase with afterwards, and the power good signal VDDN_POWERGOOD of output is low level.
The t1-t3 stage: enabling signal EN is high level, i.e. enable switch 24 Guan Bi of division module 21, the supply voltage VDDN of input is in startup ascent stage, but without reaching desired voltage state, therefore, detection dividing potential drop VDDN ' after division module 21 is changed not yet reaches the preset threshold range of schmitt inverter 25, ideally after schmitt inverter 25 judges, the marking signal FLAG of output should as low level, but due to the non-ideal characteristic that schmitt inverter 25 compares, there is certain comparison td time delay, that is, the high level FLAG signal that the t1 moment exports can form certain delay within the td time period, until t2=t1+td moment FLAG signal just overturns as low level. therefore, the FLAG signal that the t1-t2 stage exports is high level, logical AND gate 23 will enable signal EN with marking signal FLAG phase with afterwards, the power good signal VDDN_POWERGOOD of output is high level, but now power supply does not really meet the state of good output, therefore follow-up protection circuit can be produced maloperation, thus bringing adverse influence, the FLAG signal that the t2-t3 stage exports is low level, and logical AND gate 23 will enable signal EN with marking signal FLAG phase with afterwards, and the power good signal VDDN_POWERGOOD of output is low level.
The t3-t4 stage: enable signal EN and continue to keep high level, supply voltage VDDN reaches and is maintained at desired voltage state, therefore, detection dividing potential drop VDDN ' after division module 21 is changed reaches and is maintained at the preset threshold range of judge module 22, the marking signal FLAG of judge module 22 output is high level, logical AND gate 23 will enable signal EN with marking signal FLAG phase with afterwards, the power good signal VDDN_POWERGOOD of output is high level, and now supply voltage just really meets the state of good output.
Based on same principle, the signal response output procedure that the existing power supply shown in Fig. 4 exports well subelement is also similar to the above embodiments, does not repeat them here.
Visible; owing to enabling competition and the risk problem that switch and judge module different delayed time cause; real response output there will be burr phenomena (t1-t2 stage); affect the judgment accuracy of the good state of power supply; follow-up protection circuit can be produced maloperation, and then affect the overall performance of display driver chip.
Summary of the invention
It is an object of the invention to provide a kind of power good signal output intent and device, improve the judgment accuracy of the good state of power supply, improve the overall performance of display driver chip.
Based on considerations above, one aspect of the present invention provides a kind of power good signal output intent, comprises the steps:
By the supply voltage of input being converted to the detection dividing potential drop being available for judging with the division module enabling switch, the described switch that enables is in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module near hot end;
Described detection dividing potential drop, output identification signal is judged by forward judge module;
Described enable signal and marking signal is processed, the good signal of out-put supply by logical AND gate.
Preferably, described supply voltage be on the occasion of time, described enable switch is connected in described division module near power voltage terminal, and wherein, signal response output procedure includes such as the next stage:
In the 0-T1 stage: enable signal is low level, detection dividing potential drop is equal to ground wire voltage, and marking signal is low level, and power good signal is low level;
In the T1-T2 stage: enable signal is high level, detection dividing potential drop is not up to preset threshold range, and marking signal is low level, and power good signal is low level;
In the T2-T3 stage: enable signal is high level, detection dividing potential drop reaches preset threshold range, and marking signal is high level, and power good signal is high level;
In the T3-T4 stage: enable signal is low level, detection dividing potential drop is equal to ground wire voltage, and marking signal is high level, and power good signal is low level;
T4 after-stage: enable signal is low level, detection dividing potential drop is equal to ground wire voltage, and marking signal is low level, and power good signal is low level.
Preferably, described forward judge module includes hysteresis comparator or the phase inverter of even number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
Preferably, described schmitt inverter is powered by built-in power.
Another aspect of the present invention provides a kind of power good signal output intent, comprises the steps:
By the supply voltage of input being converted to the detection dividing potential drop being available for judging with the division module enabling switch, the described switch that enables is in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module near cold end;
Described detection dividing potential drop, output identification signal is judged by reverse judge module;
Described enable signal and marking signal is processed, the good signal of out-put supply by logical AND gate.
Preferably, described supply voltage be on the occasion of time, described enable switch is connected in described division module closely line end, and wherein, signal response output procedure includes such as the next stage:
In the 0-T1 ' stage: enable signal is low level, detection dividing potential drop is equal to supply voltage, and marking signal is low level, and power good signal is low level;
In the T1 '-T2 ' stage: enable signal is high level, detection dividing potential drop is not up to preset threshold range, and marking signal is low level, and power good signal is low level;
In the T2 '-T3 ' stage: enable signal is high level, detection dividing potential drop reaches preset threshold range, and marking signal is high level, and power good signal is high level;
In the T3 '-T4 ' stage: enable signal is low level, detection dividing potential drop is equal to supply voltage, and marking signal is high level, and power good signal is low level;
T4 ' after-stage: enable signal is low level, detection dividing potential drop is equal to supply voltage, and marking signal is low level, and power good signal is low level.
Preferably, described reverse judge module includes hysteresis comparator or single schmitt inverter or the phase inverter of odd number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
Preferably, described schmitt inverter is powered by built-in power.
Another aspect of the present invention provides a kind of power good signal output device, including:
With the division module enabling switch, for the supply voltage of input being converted to the detection dividing potential drop being available for judging, the described switch that enables in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module close hot end;
Forward judge module, is used for judging described detection dividing potential drop, output identification signal;
Logical AND gate, is used for processing described enable signal and marking signal, the good signal of out-put supply.
Preferably, described forward judge module includes hysteresis comparator or the phase inverter of even number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
Preferably, described schmitt inverter is powered by built-in power.
Another aspect of the present invention provides a kind of power good signal output device, including:
With the division module enabling switch, for the supply voltage of input being converted to the detection dividing potential drop being available for judging, the described switch that enables in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module close cold end;
Reverse judge module, is used for judging described detection dividing potential drop, output identification signal;
Logical AND gate, is used for processing described enable signal and marking signal, the good signal of out-put supply.
Preferably, described reverse judge module includes hysteresis comparator or single schmitt inverter or the phase inverter of odd number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
Preferably, described schmitt inverter is powered by built-in power.
The power good signal output intent of the present invention and device, the connected mode of switch and the judgment mode of judge module is enabled by reasonable disposition, zero-power quiescent current can be realized under deep sleep or shutdown mode, can solve again to enable and switch the competition and risk problem caused with judge module different delayed time, eliminate the burr phenomena in real response output, improve the judgment accuracy of the good state of power supply, improve the overall performance of display driver chip.
Accompanying drawing explanation
Reading the following detailed description to non-limiting example by referring to accompanying drawing, the other features, objects and advantages of the present invention will become more apparent upon.
Fig. 1 is the power sense circuit figure of existing display driver chip;
Fig. 2 is the module map that existing power supply exports well subelement;
Fig. 3, Fig. 4 are the circuit diagram that existing power supply exports well subelement;
Fig. 5 is the design sketch that existing power supply exports well subelement;
The power supply that Fig. 6 (A) is the embodiment of the present invention one exports well the circuit diagram of subelement;
The power supply that Fig. 6 (B) is the embodiment of the present invention one exports well the design sketch of subelement;
The power supply that Fig. 7 (A) is the embodiment of the present invention two exports well the circuit diagram of subelement;
The power supply that Fig. 7 (B) is the embodiment of the present invention two exports well the design sketch of subelement.
In the drawings, running through different diagrams, same or similar accompanying drawing labelling represents same or analogous device (module) or step.
Detailed description of the invention
For solving above-mentioned the problems of the prior art, the present invention provides a kind of power good signal output intent and device, the connected mode of switch and the judgment mode of judge module is enabled by reasonable disposition, zero-power quiescent current can be realized under deep sleep or shutdown mode, can solve again to enable and switch the competition and risk problem caused with judge module different delayed time, eliminate the burr phenomena in real response output, improve the judgment accuracy of the good state of power supply, improve the overall performance of display driver chip.
In the specific descriptions of following preferred embodiment, reference is constituted the accompanying drawing appended by a present invention part. Appended accompanying drawing has been illustrated by way of example and has been capable of specific embodiment. The embodiment of example is not intended as the limit all embodiments according to the present invention. It is appreciated that under the premise not necessarily departing from the scope of the present invention, it is possible to use other embodiments, it is also possible to carry out structural or logicality amendment. Therefore, following specific descriptions are also nonrestrictive, and the scope of the present invention is defined by the claims appended hereto.
Embodiment one
Fig. 6 (A) illustrates the circuit diagram of the power good signal output subelement of the embodiment of the present invention one, and Fig. 6 (B) illustrates the design sketch of the power good signal output subelement of the embodiment of the present invention one.
As shown in Fig. 6 (A), the power good signal output subelement of the present invention includes with the division module 121 enabling switch 124, forward judge module 122 and logical AND gate 123, wherein, input supply voltage VDDN be on the occasion of, enable switch 124 near hot end, i.e. power voltage terminal (VDDN end).
Wherein, the supply voltage VDDN of input is converted to the detection dividing potential drop VDDN ' being available for judging by division module 121 by electric resistance partial pressure. Owing to division module 121 being provided with in response to the enable switch 124 enabling signal EN, by enabling the control of signal EN, it is possible to meeting under deep sleep or shutdown mode, the quiescent dissipation of divider resistance string is zero.
Forward judge module 122 is used for judging detection dividing potential drop VDDN ', output identification signal FLAG. Schmitt inverter 125 except two shown in the present embodiment series connection, also can adopt the phase inverter that even number is connected, described phase inverter includes at least one and is connected to the schmitt inverter 125 near described division module 121 outfan, to increase driving force, or directly adopt hysteresis comparator.
Logical AND gate 123 will be for enabling signal EN and marking signal FLAG phase and, the good signal VDDN_POWERGOOD of out-put supply.
For the supply voltage VDDN that inputted by multi-output power supply administrative unit for 3.0V, the positive threshold voltage assuming judge module is 1.6V, negative threshold voltage is 0.8V, and the power supply of the present embodiment exports well shown in signal response output procedure such as Fig. 6 (B) of subelement, specifically includes such as the next stage:
The 0-T1 stage: enabling signal EN is low level, namely now the enable switch 124 of division module 121 disconnects, namely one end level of the resistance string for detecting disconnects with positive voltage end, and the other end couples with ground terminal all the time, dividing potential drop VDDN ' is equal to ground wire voltage (0V) in detection, after forward judge module 122 judges, the marking signal FLAG of output is low level, logical AND gate 123 will enable signal EN with marking signal FLAG phase with afterwards, and the power good signal VDDN_POWERGOOD of output is low level;
The T1-T2 stage: enabling signal EN is high level, i.e. enable switch 124 Guan Bi of division module 121, the supply voltage VDDN of input is in startup ascent stage, but without reaching desired voltage state, therefore, detection dividing potential drop VDDN ' after division module 121 is changed not yet reaches the preset threshold range of forward judge module 122, ideally after forward judge module 122 judges, the marking signal FLAG of output should as low level, although by the non-ideal characteristic that forward judge module 122 compares, there is certain comparison td time delay, but the FLAG logic state signal exported due to the T1 moment is also low level, impact thus without the FLAG signal that the T1-T2 stage is exported, the FLAG signal that the whole T1-T2 stage exports is low level, logical AND gate 123 will enable signal EN with marking signal FLAG phase with afterwards, the power good signal VDDN_POWERGOOD of output is low level,
The T2-T3 stage: enable signal EN and continue to keep high level, supply voltage VDDN reaches and is maintained at desired voltage state, therefore, detection dividing potential drop VDDN ' after division module 121 is changed reaches and is maintained at the preset threshold range of forward judge module 122, the marking signal FLAG of forward judge module 122 output is high level, logical AND gate 123 will enable signal EN with marking signal FLAG phase with afterwards, and the power good signal VDDN_POWERGOOD of output is high level;
T3 after-stage: enabling signal EN is low level, i.e. enable switch 124 disconnection of division module 121, detection dividing potential drop VDDN ' is again equal to ground wire voltage (0V), ideally after forward judge module 122 judges, the marking signal FLAG of output should as low level, but due to the non-ideal characteristic that forward judge module 122 compares, there is certain comparison td time delay, that is, the high level FLAG signal that the T3 moment exports can form certain delay within the td time period, until T4=T3+td moment FLAG signal just overturns as low level, but in the stage after whole T3, logical AND gate 123 will enable signal EN with marking signal FLAG phase with afterwards, the good signal VDDN_POWERGOOD of out-put supply is low level, show that supply voltage VDDN has been no longer on output state, it is off-mode.
Embodiment two
Fig. 7 (A) illustrates the circuit diagram of the power good signal output subelement of the embodiment of the present invention two, and Fig. 7 (B) illustrates the design sketch of the power good signal output subelement of the embodiment of the present invention two.
As shown in Fig. 7 (A), the power good signal output subelement of the present invention includes with the division module 221 enabling switch 224, reverse judge module 222 and logical AND gate 223, wherein, input supply voltage VDDN be on the occasion of, enable switch 224 near cold end, i.e. ground terminal (GND end).
Wherein, the supply voltage VDDN of input is converted to the detection dividing potential drop VDDN ' being available for judging by division module 221 by electric resistance partial pressure. Owing to division module 221 being provided with in response to the enable switch 224 enabling signal EN, by enabling the control of signal EN, it is possible to meeting under deep sleep or shutdown mode, the quiescent dissipation of divider resistance string is zero.
Reverse judge module 222 is used for judging detection dividing potential drop VDDN ', output identification signal FLAG. Except the single schmitt inverter 225 shown in the present embodiment, also can adopt the phase inverter that odd number is connected, described phase inverter includes at least one and is connected to the schmitt inverter 225 near described division module 221 outfan, to increase driving force, or directly adopts hysteresis comparator.
Logical AND gate 223 will be for enabling signal EN and marking signal FLAG phase and, the good signal VDDN_POWERGOOD of out-put supply.
For the supply voltage VDDN that inputted by multi-output power supply administrative unit for 3.0V, the positive threshold voltage assuming judge module is 1.6V, negative threshold voltage is 0.8V, and the power supply of the present embodiment exports well shown in signal response output procedure such as Fig. 7 (B) of subelement, specifically includes such as the next stage:
0-T1 ' the stage: enabling signal EN is low level, namely now the enable switch 224 of division module 221 disconnects, namely one end level of the resistance string for detecting disconnects with ground end, and the other end couples with the positive voltage of output all the time, detection dividing potential drop VDDN ' is equal to supply voltage VDDN(3V), after reverse judge module 222 judges, the marking signal FLAG of output is low level, logical AND gate 223 will enable signal EN with marking signal FLAG phase with afterwards, and the power good signal VDDN_POWERGOOD of output is low level;
T1 '-T2 ' the stage: enabling signal EN is high level, i.e. enable switch 224 Guan Bi of division module 221, the supply voltage VDDN of input is in startup ascent stage, but without reaching desired voltage state, therefore, detection dividing potential drop VDDN ' after division module 221 is changed not yet reaches the preset threshold range of reverse judge module 222, ideally after reverse judge module 222 judges, the marking signal FLAG of output should as low level, although by the non-ideal characteristic that reverse judge module 222 compares, there is certain comparison td time delay, but the FLAG logic state signal exported due to the T1 ' moment is also low level, impact thus without the FLAG signal that the T1 '-T2 ' stage is exported, the FLAG signal that the whole T1 '-T2 ' stage exports is low level, logical AND gate 223 will enable signal EN with marking signal FLAG phase with afterwards, the power good signal VDDN_POWERGOOD of output is low level,
T2 '-T3 ' the stage: enable signal EN and continue to keep high level, supply voltage VDDN reaches and is maintained at desired voltage state, therefore, detection dividing potential drop VDDN ' after division module 221 is changed reaches and is maintained at the preset threshold range of reverse judge module 222, the marking signal FLAG of reverse judge module 222 output is high level, logical AND gate 223 will enable signal EN with marking signal FLAG phase with afterwards, and the power good signal VDDN_POWERGOOD of output is high level;
T3 ' after-stage: enabling signal EN is low level, i.e. enable switch 224 disconnection of division module 221, detection dividing potential drop VDDN ' is again equal to supply voltage VDDN(3V), ideally after reverse judge module 222 judges, the marking signal FLAG of output should as low level, but due to the non-ideal characteristic that reverse judge module 222 compares, there is certain comparison td time delay, that is, the high level FLAG signal that the T3 ' moment exports can form certain delay within the td time period, until T4 '=T3 '+td moment FLAG signal just overturns as low level, but in the stage after whole T3 ', logical AND gate 223 will enable signal EN with marking signal FLAG phase with afterwards, the good signal VDDN_POWERGOOD of out-put supply is low level, show that supply voltage VDDN has been no longer on output state, it is off-mode.
It will be understood by those skilled in the art that the power good signal output intent of the present invention and device are also applied for the situation that supply voltage VDDN is negative value of input. When supply voltage VDDN is negative value, the hot end in division module should be fixed voltage end (vdd terminal), and cold end should be power voltage terminal (VDDN end). Similarly, enable switch adopts forward judge module to judge detection dividing potential drop VDDN ' when hot end, enable switch adopts reverse judge module to judge detection dividing potential drop VDDN ' when cold end, then can reach the effect similar with above-mentioned the present embodiment, not repeat them here.
The power good signal output intent of the present invention and device, the connected mode of switch and the judgment mode of judge module is enabled by reasonable disposition, zero-power quiescent current can be realized under deep sleep or shutdown mode, can solve again to enable and switch the competition and risk problem caused with judge module different delayed time, eliminate the burr phenomena in real response output, improve the judgment accuracy of the good state of power supply, improve the overall performance of display driver chip.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when without departing substantially from the spirit of the present invention or basic feature, it is possible to realize the present invention in other specific forms. Therefore, in any case, embodiment all should be regarded as exemplary, and be nonrestrictive. Additionally, it will be evident that " including " word is not excluded for other elements and step, and wording " one " is not excluded for plural number. In device claim, multiple elements of statement can also be realized by an element. The first, the second word such as grade is used for representing title, and is not offered as any specific order.
Claims (14)
1. a power good signal output intent, it is characterised in that comprise the steps:
By the supply voltage of input being converted to the detection dividing potential drop being available for judging with the division module enabling switch, the described switch that enables is in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module near hot end;
Described detection dividing potential drop, output identification signal is judged by forward judge module;
Described enable signal and marking signal is processed, the good signal of out-put supply by logical AND gate.
2. power good signal output intent as claimed in claim 1, it is characterised in that
Described supply voltage be on the occasion of time, described enable switch is connected in described division module near power voltage terminal, and wherein, signal response output procedure includes such as the next stage:
In the 0-T1 stage: enable signal is low level, detection dividing potential drop is equal to ground wire voltage, and marking signal is low level, and power good signal is low level;
In the T1-T2 stage: enable signal is high level, detection dividing potential drop is not up to preset threshold range, and marking signal is low level, and power good signal is low level;
In the T2-T3 stage: enable signal is high level, detection dividing potential drop reaches preset threshold range, and marking signal is high level, and power good signal is high level;
In the T3-T4 stage: enable signal is low level, detection dividing potential drop is equal to ground wire voltage, and marking signal is high level, and power good signal is low level;
T4 after-stage: enable signal is low level, detection dividing potential drop is equal to ground wire voltage, and marking signal is low level, and power good signal is low level.
3. power good signal output intent as claimed in claim 1, it is characterized in that, described forward judge module includes hysteresis comparator or the phase inverter of even number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
4. power good signal output intent as claimed in claim 3, it is characterised in that described schmitt inverter is powered by built-in power.
5. a power good signal output intent, it is characterised in that comprise the steps:
By the supply voltage of input being converted to the detection dividing potential drop being available for judging with the division module enabling switch, the described switch that enables is in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module near cold end;
Described detection dividing potential drop, output identification signal is judged by reverse judge module;
Described enable signal and marking signal is processed, the good signal of out-put supply by logical AND gate.
6. power good signal output intent as claimed in claim 5, it is characterised in that
Described supply voltage be on the occasion of time, described enable switch is connected in described division module closely line end, and wherein, signal response output procedure includes such as the next stage:
In the 0-T1 ' stage: enable signal is low level, detection dividing potential drop is equal to supply voltage, and marking signal is low level, and power good signal is low level;
In the T1 '-T2 ' stage: enable signal is high level, detection dividing potential drop is not up to preset threshold range, and marking signal is low level, and power good signal is low level;
In the T2 '-T3 ' stage: enable signal is high level, detection dividing potential drop reaches preset threshold range, and marking signal is high level, and power good signal is high level;
In the T3 '-T4 ' stage: enable signal is low level, detection dividing potential drop is equal to supply voltage, and marking signal is high level, and power good signal is low level;
T4 ' after-stage: enable signal is low level, detection dividing potential drop is equal to supply voltage, and marking signal is low level, and power good signal is low level.
7. power good signal output intent as claimed in claim 5, it is characterized in that, described reverse judge module includes hysteresis comparator or single schmitt inverter or the phase inverter of odd number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
8. power good signal output intent as claimed in claim 7, it is characterised in that described schmitt inverter is powered by built-in power.
9. a power good signal output device, it is characterised in that including:
With the division module enabling switch, for the supply voltage of input being converted to the detection dividing potential drop being available for judging, the described switch that enables in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module close hot end;
Forward judge module, is used for judging described detection dividing potential drop, output identification signal;
Logical AND gate, is used for processing described enable signal and marking signal, the good signal of out-put supply.
10. power good signal output device as claimed in claim 9, it is characterized in that, described forward judge module includes hysteresis comparator or the phase inverter of even number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
11. power good signal output device as claimed in claim 10, it is characterised in that described schmitt inverter is powered by built-in power.
12. a power good signal output device, it is characterised in that including:
With the division module enabling switch, for the supply voltage of input being converted to the detection dividing potential drop being available for judging, the described switch that enables in response to enabling signal, described supply voltage be on the occasion of or negative value, described enable switch is connected in described division module close cold end;
Reverse judge module, is used for judging described detection dividing potential drop, output identification signal;
Logical AND gate, is used for processing described enable signal and marking signal, the good signal of out-put supply.
13. power good signal output device as claimed in claim 12, it is characterized in that, described reverse judge module includes hysteresis comparator or single schmitt inverter or the phase inverter of odd number series connection, and described phase inverter includes at least one and is connected to the schmitt inverter near described division module outfan.
14. power good signal output device as claimed in claim 13, it is characterised in that described schmitt inverter is powered by built-in power.
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| CN201511006305.4A CN105679226B (en) | 2015-12-29 | 2015-12-29 | Power good signal output method and device |
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| CN201511006305.4A CN105679226B (en) | 2015-12-29 | 2015-12-29 | Power good signal output method and device |
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| CN105679226B CN105679226B (en) | 2020-09-25 |
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| CN116112002A (en) * | 2023-04-12 | 2023-05-12 | 长鑫存储技术有限公司 | Comparison circuit |
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| CN105679226B (en) | 2020-09-25 |
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