CN115903977A - DLDO circuit for eliminating LCO oscillation by adopting logic control - Google Patents
DLDO circuit for eliminating LCO oscillation by adopting logic control Download PDFInfo
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- CN115903977A CN115903977A CN202211370805.6A CN202211370805A CN115903977A CN 115903977 A CN115903977 A CN 115903977A CN 202211370805 A CN202211370805 A CN 202211370805A CN 115903977 A CN115903977 A CN 115903977A
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Abstract
The invention relates to the technical field of dust collecting circuits, and discloses a DLDO (digital Living do) circuit for eliminating LCO (lower control threshold) oscillation by adopting logic control OUT The output end of the window comparator is connected with the input end of the fine adjustment circuit, and the input end of the single limit comparator is connected with the circuit output voltage V OUT And the output end of the single limit comparator is connected with the input end of the fine tuning circuit, and the fine tuning circuit comprises a stable state detection circuit, a bidirectional shift register group and a small-size PMOS array. The DLDO circuit adopting logic control to eliminate LCO oscillation adopts a dynamic comparator technology, effectively avoids unexpected overturn of output signals of the comparator, reduces power consumption of the comparator, and improves transient response speed and reduces errors of output voltage by using a technology of combining a coarse regulation circuit and a fine regulation circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a DLDO circuit for eliminating LCO oscillation by adopting logic control.
Background
DLDO is an abbreviation of Digital Low dropout regulator, namely, a Digital Low dropout linear regulator. A digital low dropout linear regulator is a circuit that uses digital logic to implement low dropout conversion between an input and an output, where the dropout is the minimum of the difference between the input voltage and the output voltage required to maintain the output voltage within 100mV of its nominal value. Digital LDOs have smaller power transistors, fewer stability problems, and better process scalability than analog LDOs, and are therefore used in mobile power supply systems.
However, compared with the analog LDO, the conventional digital LDO has the disadvantages of continuous LCO oscillation, large oscillation error, large static power consumption, and slow transient response, so a DLDO circuit capable of stabilizing output voltage, eliminating LCO oscillation, reducing power consumption, and reducing a stabilization error on the premise of increasing a transient response speed needs to be invented to solve the above problems.
Disclosure of Invention
The present invention is directed to a DLDO circuit for eliminating LCO oscillation by logic control, so as to solve the above problems in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme: a DLDO circuit for eliminating LCO oscillation by adopting logic control comprises a fine tuning circuit, a coarse tuning circuit, a window comparator, a dynamic single-limit comparator and a load circuit, wherein the input end of the window comparator and the output voltage V of the circuit OUT The output end of the window comparator is connected with the input end of the fine adjustment circuit, and the input end of the single limit comparator is connected with the circuit output voltage V OUT And the output end of the single-limit comparator is connected with the input end of the fine adjustment circuit.
The fine adjustment circuit comprises a stable state detection circuit, a bidirectional shift register group and a small-size PMOS array, wherein the input ends of the stable state detection circuit, the bidirectional shift register group and the small-size PMOS array are connected with the input ends of a window comparator and a single limit comparator, the output end of the stable state detection circuit is connected with the input end of a bidirectional shift register, and the output end of the bidirectional shift register is connected with the input end of the small-size PMOS array.
The coarse tuning circuit comprises coarse tuning logic and a large-size PMOS array, the output end of the coarse tuning logic is connected with the input end of the large-size PMOS array, and the output end of the large-size PMOS array is connected with the output end of the small-size PMOS array to be used as the output voltage V of the circuit OUT 。
Preferably, the one-way comparator outputs a voltage V OUT And a reference voltage V REF Comparing to obtain direction FD signal for controlling the adjusting directions of the coarse adjusting circuit and the fine adjusting circuit when V is less than V OUT >V REF FD =0 is obtained for controlling the bidirectional shift register set and the coarse logic module in the fine tuning logic to adjust toward the direction of closing the PMOS tube, so as to make the output voltage V OUT Approaches to the reference voltage V REF And conversely, the correct adjustment direction of the output voltage is ensured.
Preferably, the window comparator outputs a voltage V OUT And window upper and lower limit voltages V REFH And V REFL Comparing to obtain a window signal EN for controlling the enabling of the bidirectional shift register group in the fine adjustment logic and the coarse adjustment logic; when the output voltage V is OUT When the window is out, enabling the coarse tuning logic and disabling the bidirectional shift register in the fine tuning logic; when the output voltage V is OUT When the circuit is in the window, the bidirectional shift register in the fine adjustment logic is enabled, the bidirectional coarse adjustment logic is disabled, the circuit is ensured to be capable of adaptively selecting proper adjustment logic according to the state of the output voltage, and the coarse adjustment circuit is combined with the fine adjustment circuit, so that the transient response speed is improved, and meanwhile, the error of the output voltage is reduced.
Preferably, the dynamic single-limit comparator adopts a dynamic technology to perform voltage comparison, when the clock signal CLK is at a high level, the input node of the SR flip-flop is charged, and the SR flip-flop stabilizes the output of the comparator; when the clock signal CLK is at a low level, the side with high input voltage discharges an input node of the SR trigger, the SR trigger locks the output of the comparator, the window comparator is built by adopting a dynamic single-limit comparator, and the dynamic technology is adopted, so that the unexpected overturn of the output signal of the comparator is effectively avoided, and the power consumption of the comparator is reduced.
Preferably, the steady state detection module detects the steady state by using a D flip-flop, a D flip-flop with an asynchronous set, and an exclusive-or gate, and determines the steady state of the output voltage if the direction signal FD is inverted and does not exceed the window within the window range, so as to disable the bidirectional shift register set in the fine tuning logic, thereby realizing effective detection of the steady state of the output voltage, effectively eliminating LCO oscillation of the output voltage, and reducing static power consumption.
Preferably, the bidirectional shift register adopts a TG transmission gate, a NOT gate and an NMOS tube to realize bidirectional selective shift of the register.
Preferably, when the bidirectional shift register group realizes FD =1, the register group moves to 1 right, i.e. the PMOS transistor is turned on; when FD =0, the register group moves in 0 to the left, namely the PMOS tube is closed, the bidirectional shift register group is a limited register and is connected to a small-size PMOS array, the accurate control of output voltage is realized, and the output error is reduced.
Compared with the prior art, the DLDO circuit for eliminating LCO oscillation by adopting logic control has the following beneficial effects:
1. the DLDO circuit adopting logic control to eliminate LCO oscillation effectively avoids the unexpected overturn of the output signal of the comparator by adopting the dynamic comparator technology, reduces the power consumption of the comparator, and improves the transient response speed and reduces the error of the output voltage by adopting the technology of combining a coarse regulation circuit and a fine regulation circuit.
2. The DLDO circuit which adopts logic control to eliminate LCO oscillation judges the stable state STD of the output voltage by adopting a stable state detection module technology, and can timely lose the bidirectional shift register group in the fine adjustment logic. LCO oscillation of output voltage is eliminated, static power consumption is reduced, a limited bidirectional shift register group technology is adopted, a small-size PMOS array is accessed, accurate and accurate adjustment of the output voltage is achieved, and output errors are reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive labor:
FIG. 1 is an overall structure diagram of a DLDO circuit of the present invention;
FIG. 2 is a circuit diagram of a dynamic single-limit comparator according to the present invention;
FIG. 3 is a block diagram of a window comparator according to the present invention;
FIG. 4 is a block diagram of a steady state detection module according to the present invention;
FIG. 5 is a circuit diagram of a bidirectional shift register according to the present invention;
FIG. 6 is a diagram of a bidirectional shift register set according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1-6, the present invention provides a technical solution: a DLDO circuit for eliminating LCO oscillation by logic control comprises a fine tuning circuit, a coarse tuning circuit, a window comparator,Dynamic single-limit comparator and load circuit, input end of window comparator and circuit output voltage V OUT The output end of the window comparator is connected with the input end of the fine adjustment circuit, and the input end of the single limit comparator is connected with the output voltage V of the circuit OUT And the output end of the single-limit comparator is connected with the input end of the fine adjustment circuit.
The fine adjustment circuit comprises a stable state detection circuit, a bidirectional shift register group and a small-size PMOS array, wherein the input ends of the stable state detection circuit, the bidirectional shift register group and the small-size PMOS array are connected with the input ends of a window comparator and a single limit comparator, the output end of the stable state detection circuit is connected with the input end of a bidirectional shift register, and the output end of the bidirectional shift register is connected with the input end of the small-size PMOS array.
The coarse tuning circuit comprises coarse tuning logic and a large-size PMOS array, wherein the output end of the coarse tuning logic is connected with the input end of the large-size PMOS array, and the output end of the large-size PMOS array is connected with the output end of the small-size PMOS array to be used as the output voltage V of the circuit OUT 。
Further, the single-limit comparator outputs the voltage V OUT And a reference voltage V REF Comparing to obtain direction FD signal for controlling the adjusting directions of the coarse adjusting circuit and the fine adjusting circuit when V is OUT >V REF FD =0 is obtained for controlling the bidirectional shift register set and the coarse logic module in the fine tuning logic to adjust toward the direction of closing the PMOS tube, so as to make the output voltage V OUT Approaches a reference voltage V REF And conversely, the correct adjustment direction of the output voltage is ensured.
Further, the window comparator outputs a voltage V OUT And window upper and lower limit voltages V REFH And V REFL Comparing to obtain a window signal EN for controlling the enabling of the bidirectional shift register group in the fine adjustment logic and the coarse adjustment logic; when the output voltage V is OUT When the window is out, the coarse tuning logic is enabled, and the bidirectional shift register in the fine tuning logic is disabled; when the output voltage V is OUT When in the window, the bidirectional shift register in the fine tuning logic is enabled, the bidirectional coarse tuning logic is disabled,the circuit can be ensured to select proper adjusting logic in a self-adaptive mode according to the state of the output voltage, and the coarse adjusting circuit is combined with the fine adjusting circuit, so that the transient response speed is improved, and meanwhile, the error of the output voltage is reduced.
Furthermore, the dynamic one-limit comparator adopts a dynamic technology to carry out voltage comparison, when the clock signal CLK is at a high level, the input node of the SR trigger is charged, and the SR trigger stabilizes the output of the comparator; when the clock signal CLK is at a low level, the side with high input voltage discharges an input node of the SR trigger, the SR trigger locks the output of the comparator, the window comparator is built by adopting a dynamic single-limit comparator, and the dynamic technology is adopted, so that the unexpected overturn of the output signal of the comparator is effectively avoided, and the power consumption of the comparator is reduced.
Further, the stable state detection module detects the stable state by adopting a D trigger, a D trigger with an asynchronous setting and an exclusive-OR gate, and in a window range, if a direction signal FD is overturned and does not exceed a window, the stable state of the output voltage is judged to be the stable state of the output voltage and is used for disabling a bidirectional shift register set in the fine tuning logic, so that the effective detection of the stable state of the output voltage is realized, the LCO oscillation of the output voltage is effectively eliminated, and the static power consumption is reduced.
Furthermore, the bidirectional shift register adopts TG transmission gates, NOT gates and NMOS tubes to realize bidirectional selective shift of the register.
Further, when the bidirectional shift register group realizes FD =1, the register group moves into 1 to the right, namely, the PMOS tube is opened; when FD =0, the register bank moves in 0 to the left, namely the PMOS tube is closed, the bidirectional shift register bank is a limit register and is accessed to a small-size PMOS array, the accurate control of the output voltage is realized, and the output error is reduced.
In the actual operation process, when the device is used, a voltage signal output by the PMOS array is input into the dynamic single-limit comparator and the window comparator, and the dynamic single-limit comparator detects and judges the signal so as to control the circuit to adjust the direction; the window comparator detects and judges the signal to control the circuit to enable coarse adjustment or fine adjustment;
when the coarse tuning mode is enabled, the coarse tuning control word is calculated by the coarse tuning logic, when the fine tuning mode is enabled, the fine tuning control word is initialized, then the shifting direction of the bidirectional shifting register set is controlled by the FD signal, and when the stable state detection module detects the stable state STD, the bidirectional shifting register set is enabled, so that the output voltage is kept stable;
the control word is output to the PMOS array to control the on or off of the PMOS array so as to adapt to the change of load current, stabilize output voltage and realize adjustment.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
Claims (7)
1. A DLDO circuit for eliminating LCO oscillation by adopting logic control comprises a fine tuning circuit, a coarse tuning circuit, a window comparator, a dynamic single-limit comparator and a load circuit, and is characterized in that: the input end of the window comparator and the circuit output voltage V OUT The output end of the window comparator is connected with the input end of the fine adjustment circuit, and the input end of the single limit comparator is connected with the circuit output voltage V OUT The output end of the single-limit comparator is connected with the input end of the fine adjustment circuit;
the fine adjustment circuit comprises a stable state detection circuit, a bidirectional shift register group and a small-size PMOS array, wherein the input ends of the stable state detection circuit, the bidirectional shift register group and the small-size PMOS array are connected with the input ends of a window comparator and a single limit comparator, the output end of the stable state detection circuit is connected with the input end of a bidirectional shift register, and the output end of the bidirectional shift register is connected with the input end of the small-size PMOS array;
the coarse tuning circuit comprises coarse tuning logic and a large-size PMOS array, the output end of the coarse tuning logic is connected with the input end of the large-size PMOS array, and the output end of the large-size PMOS array is connected with the output end of the small-size PMOS array to be used as the output voltage V of the circuit OUT 。
2. The DLDO circuit with logic control for eliminating LCO oscillations as claimed in claim 1, wherein: the single limit comparator outputs a voltage V OUT And a reference voltage V REF Comparing to obtain direction FD signal for controlling the adjusting directions of the coarse adjusting circuit and the fine adjusting circuit when V is OUT >V REF FD =0 is obtained for controlling the bidirectional shift register set and the coarse logic module in the fine tuning logic to adjust toward the direction of closing the PMOS tube, so as to make the output voltage V OUT Approaches a reference voltage V REF And conversely, the correct adjustment direction of the output voltage is ensured.
3. The DLDO circuit for eliminating LCO oscillations with logic control as claimed in claim 1, wherein: the window comparator outputs a voltage V OUT And window upper and lower limit voltages V REFH And V REFL Comparing to obtain a window signal EN for controlling the enabling of the bidirectional shift register group in the fine tuning logic and the coarse tuning logic; when the output voltage V is OUT When the window is out, enabling the coarse tuning logic and disabling the bidirectional shift register in the fine tuning logic; when the output voltage V is OUT When in the window, the bidirectional shift register in the fine tuning logic is enabled, and the bidirectional coarse tuning logic is disabled.
4. The DLDO circuit with logic control for eliminating LCO oscillations as claimed in claim 1, wherein: the dynamic single-limit comparator adopts a dynamic technology to carry out voltage comparison, when the clock signal CLK is at a high level, the input node of the SR trigger is charged, and the SR trigger stabilizes the output of the comparator; when the clock signal CLK is at a low level, the side with high input voltage discharges the input node of the SR trigger, the SR trigger locks the output of the comparator, and the window comparator is built by adopting a dynamic one-limit comparator.
5. The DLDO circuit with logic control for eliminating LCO oscillations as claimed in claim 1, wherein: the stable state detection module detects the stable state by adopting a D trigger, a D trigger with an asynchronous setting and an exclusive-OR gate, and determines the stable state of the output voltage if a direction signal FD overturns within a window range and does not exceed the window, so that the stable state detection module can lose the two-way shift register group in the fine adjustment logic.
6. The DLDO circuit with logic control for eliminating LCO oscillations as claimed in claim 1, wherein: the bidirectional shift register adopts TG transmission gates, NOT gates and NMOS tubes to realize bidirectional selective shift of the register.
7. The DLDO circuit for eliminating LCO oscillation with logic control as claimed in claim 6, wherein: when the FD =1 is realized by the bidirectional shift register group, the register group is shifted into 1 to the right, namely, the PMOS tube is opened; when FD =0, the register bank is shifted in to 0 on the left, namely the PMOS tube is closed, and the bidirectional shift register bank is a limited register and is accessed to a small-size PMOS array.
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| CN202211370805.6A CN115903977A (en) | 2022-11-03 | 2022-11-03 | DLDO circuit for eliminating LCO oscillation by adopting logic control |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116112002A (en) * | 2023-04-12 | 2023-05-12 | 长鑫存储技术有限公司 | Comparison circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116112002A (en) * | 2023-04-12 | 2023-05-12 | 长鑫存储技术有限公司 | Comparison circuit |
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