CN115985783B - Packaging structure and technology of MOSFET chip - Google Patents
Packaging structure and technology of MOSFET chip Download PDFInfo
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- CN115985783B CN115985783B CN202310268172.6A CN202310268172A CN115985783B CN 115985783 B CN115985783 B CN 115985783B CN 202310268172 A CN202310268172 A CN 202310268172A CN 115985783 B CN115985783 B CN 115985783B
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Abstract
The application of the invention discloses a packaging process of a MOSFET chip, which comprises the following steps: bump formation step: electroplating on the active surface of the wafer, and forming a bump electrically connected with the grid and the source electrode respectively, wherein the heights of the bump on the grid and the bump on the source electrode are equal; and (3) a patch encapsulation step: after cutting the wafer into single chips, respectively bonding the passive surfaces of the single chips to corresponding carriers, and integrally encapsulating and grinding the active surfaces; drilling: drilling the area of the top surface of the encapsulation so that the drilling is vertically connected with the bonding pad at the bottom of the encapsulation; electroplating and encapsulating: electroplating the connecting column in the drill hole, and electroplating a wiring layer between the connecting column and the bump; and a cutting step, wherein the bump is directly electroplated in the chip area, the electroplated connecting column is directly and flatly connected with the wiring layer, the packaging size is further compressed under the same other conditions, the performances of process electrical property, heat dissipation and the like are not changed, the structure is simple, and the cost is reduced.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to a packaging structure and a packaging process of a MOSFET chip.
Background
With the continuous development of the electronic industry, the integrated circuit packaging technology is also continuously advanced, the variety and the number of electronic devices integrated on a printed circuit board (PCB board) are also increasing, and a MOSFET chip is one of them, so that in order to integrate more devices on the circuit board, miniaturization of a single device has become a necessary trend of the development of a device packaging process.
The MOSFET chip is a Metal-Oxide-semiconductor field effect transistor (MOSFET), which is a field effect transistor widely used in analog circuits and digital circuits, and the packaging of the conventional MOSFET product of the semiconductor device is generally electrically connected through a wire bonding process, that is, electrodes in the semiconductor chip are led to pins by using leads such as aluminum, copper or gold to be welded, so that the electrical connection is realized, but the wire bonding process is more complex, and the leads are longer, so that the internal resistance is larger; besides the wire Bonding, namely copper jumper wire Bonding, even though a packaging process for realizing connection between a chip and a frame or a substrate by using a solid copper bridge welded to solder is adopted, the copper bridge is formed by a copper sheet, the copper sheet is designed into an arch bridge shape with high and low drop height, and the packaging size is large, the whole size and thickness are large, the stress is large, and the process is complex, so that the MOSFET chip packaging structure with simple structure, low cost, high reliability and small packaging size and the process for realizing the structure are needed.
Disclosure of Invention
In order to solve the above problems in the prior art, the present application provides a packaging structure and process of a MOSFET chip.
In order to achieve the above object, the packaging process of the MOSFET chip provided by the present invention includes the following steps:
bump formation step: electroplating on the active surface of the wafer, and forming a bump electrically connected with the grid and the source electrode respectively, wherein the heights of the bump on the grid and the bump on the source electrode are equal;
and (3) a patch encapsulation step: after cutting the wafer into single chips, respectively bonding the passive surfaces of the single chips to corresponding carriers, and integrally encapsulating and grinding the active surfaces to enable the encapsulated top surfaces to be coplanar with the bump top surfaces;
drilling: drilling the area of the top surface of the encapsulation so that the drilling is vertically connected with the bonding pad at the bottom of the encapsulation;
electroplating and encapsulating: electroplating a connecting column in the drilled hole, electroplating a wiring layer between the connecting column and the bump, connecting and flattening the top surfaces of the connecting column and the bump, and integrally encapsulating the connecting column, the bump and the wiring layer, wherein the electrical property of the chip electrode is transmitted to a bonding pad;
cutting: cutting the encapsulated package body at the cutting path to obtain a single product.
In the bump forming step, the bump is a metal copper block with a flat upper surface, which is respectively electroplated on the exposed surfaces of the grid electrode and the source electrode, and the areas of the bump are respectively smaller than those of the grid electrode and the source electrode.
Further, in the bump forming step, the height of the bump is > 40 μm to prevent electrical interconnection.
Further, in the patch encapsulation step, the chip is adhered to a carrier, which is a lead frame or a substrate, by a conductive silver paste.
Further, in the patch encapsulation step, the chip is adhered to a carrier, which is a lead frame or a substrate, by a conductive silver paste.
Further, in the step of dicing, the solder pad surface exposed to the bottom surface of the package after encapsulation is plated with tin or gold to prevent oxidation.
The utility model provides a packaging structure of MOSFET chip, includes the encapsulation body, the encapsulation body encapsulates and has chip, carrier, pad and spliced pole, the encapsulation body encapsulates the chip of bonding on the carrier, carrier and pad bottom surface and encapsulation body bottom surface coplane, spliced pole bottom and pad electric connection, electroplate respectively on the grid and the source of chip and bonding surface opposite face has a lug, electroplate between lug and the spliced pole and have the wiring layer, and three top surface is connected and is leveled, and is in same horizontal plane.
Further, the bump is a metal copper block with a flat upper surface, the metal copper block is respectively electroplated on the exposed surfaces of the grid electrode and the source electrode of the chip, the areas of the metal copper block are respectively smaller than the grid electrode and the source electrode, the height of the bump is more than 40 mu m, so that the electrical interconnection is prevented, and the connecting column, the bump and the wiring layer are all made of the same material.
Further, the chip is attached to a carrier, which is a lead frame or a substrate, by means of a conductive silver paste.
Further, the bonding pads are exposed to the bottom surface of the package after encapsulation and plated with tin or gold to prevent oxidation.
The application of the invention: the bump is directly electroplated in the chip area, the rear electroplating connecting column is directly connected with the wiring layer in a flat mode, the packaging size is further compressed depending on the height of the bump under the same other conditions, the performances of process electrical property, heat dissipation and the like are similar, the structure is simple, and the cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art MOSFET chip wire-bonding package;
FIG. 2 is a schematic diagram of a prior art MOSFET chip copper jumper package;
FIG. 3 is a schematic diagram of a prior art MOSFET chip rewiring package structure;
fig. 4 is a cross-sectional view of a MOSFET chip package according to the present invention;
fig. 5 is a partial top view of a MOSFET die package according to the present invention.
The figure indicates: package 1, pad 2, bump 3, connection post 4, wiring layer 5, chip 6, gate 7, and source 8.
Detailed Description
The MOSFET chip can be called as MOS tube, can divide into PMOS and NMOS etc. according to the ion type difference of implanting, MOS tube's characteristic has that input resistance is high, the noise is little, the consumption is low, dynamic range is big, easily integrated, do not have secondary breakdown phenomenon, safe operating region advantage such as wide, MOS tube is the power switch device commonly used in the circuit design, is voltage-controlled, has three electrode, is respectively: a gate G, a source S and a drain D; the grid G is a control end, the name is Gate, and the high and low levels are added into the G end to control the on-off of the MOS tube; source S, named Source; drain D, named Drain, source S and Drain D may be outflow or inflow ends, respectively, for different MOS transistors.
Referring to fig. 1, when a MOSFET chip is packaged, electrical properties of electrodes of the MOSFET chip need to be led out through a routing manner, the specific process is that a passive surface of a MOS tube is bonded or soldered on a lead frame or a base island of a substrate through a paste adhesive (DA adhesive), a connecting wire is formed between a bonding pad of the lead frame or the substrate and the electrodes of the MOS tube, the connecting wire can be made of gold (Au), copper (Cu) or aluminum (Al) and the like, and then the whole is encapsulated, the electrical properties of the MOS tube are led out of a package body 1 through the bonding pad after being conducted through the connecting wire, the routing requires larger space routing, the whole packaging size is larger, the internal resistance is larger due to the number and the length of the connecting wire, and the electrical reliability is low.
Referring to fig. 2, in the copper bridge process, the passive surface of the MOS tube is soldered on the lead frame or the substrate by solder paste, the active surface of the MOS tube is soldered by solder paste, the copper bridge is formed by copper sheets, the copper sheets are designed into arch bridge shapes with high and low drop heights, the package size is larger, the thermal stress is large due to solder paste soldering, the residual tin is solidified to form soldering after solder paste reflow soldering, the chip 6 is easily damaged due to the large stress, and the reflow soldering requires a high temperature condition of 370 ℃ or above, and the process is complex and the safety is low.
Referring to fig. 3, after forming a plurality of bumps electrically connected to each other at the electrode of the MOS transistor, the bumps are encapsulated and ground, and then re-wired to achieve electrical extraction.
In order to better understand the objects, structures and functions of the present application, a process for packaging a MOSFET chip according to the present application is described in further detail below with reference to fig. 1-5.
The process specifically comprises the following steps:
and (3) a patch encapsulation step: after cutting the wafer into single chips 6, respectively bonding the passive surfaces of the single chips 6 to corresponding carriers, and integrally encapsulating and grinding the active surfaces to enable the encapsulated top surfaces to be coplanar with the top surfaces of the bumps 3;
drilling: drilling the area of the top surface of the encapsulation so that the drilling is vertically connected with the bonding pad 2 at the bottom of the drilling;
electroplating and encapsulating: electroplating a connecting column 4 in the drilled hole, electroplating a wiring layer 5 between the connecting column 4 and the bump 3, connecting and leveling the top surfaces of the connecting column, the bump 3 and the wiring layer 5, and integrally encapsulating the connecting column, the bump 3 and the wiring layer 5, wherein the electrode electricity of the chip 6 is transmitted to the bonding pad 2;
cutting: the encapsulated package 1 is cut at the dicing lane to be a single product.
In the step of forming the bump 3, the bump 3 is a metal copper block with a flat upper surface, which is respectively electroplated on the exposed surfaces of the gate 7 and the source 8, and the areas are respectively smaller than the gate 7 and the source 8, and the height of the bump 3 is more than 40 μm, so as to prevent electrical interconnection, and the surfaces of the gate 7 and the source 8 are respectively electroplated with a bump 3.
The patch encapsulation step further comprises the step of processing the wafer: s1, pasting a patch adhesive on a passive surface of a wafer, and pasting a blue film; s2, cutting the wafer into single crystal grains in a cutting path, namely, a single chip 6, cutting the adhesive tape by a cutting knife without cutting off a blue film, picking up the chip 6 by a chip 6 pick-up device commonly used in the field, and adhering the cut adhesive tape to the bottom (passive surface) of the chip 6; s3, bonding the chip 6 to a carrier through a chip bonding adhesive, wherein the carrier is a lead frame or a substrate commonly used in the field, one side of the lead frame or the substrate is provided with a bonding pad 2 with the same height, and the top surface of the encapsulation is coplanar with the top surface of the bump 3 through a mechanical grinding mode after encapsulation; the adhesive has small stress, less influence on the chip 6, lower temperature (less than 200 ℃) in the whole process than high-temperature reflow solidification of solder paste, and safer and more stable.
In the step of electroplating and packaging, the connecting column 4 is electroplated after drilling is formed by a laser drilling mode, the connecting column 4, the convex block 3 and the wiring layer 5 are all made of the same material, and the positions and the sizes of the connecting column 4, the convex block 3 and the wiring layer 5 are matched with those of a product which is actually produced; the bump 3 is directly electroplated in the area of the chip 6, the rear electroplating connecting column 4 and the wiring layer 5 are directly and flatly connected, the packaging size depends on the height of the bump 3 when other conditions are the same, the packaging size is further compressed, the performances of process electrical property, heat dissipation and the like are similar, the structure is simple, and the cost is reduced.
In the dicing step, the surface of the bonding pad 2 exposed to the bottom surface of the package body 1 after encapsulation is plated with tin or gold to prevent oxidation.
Referring to fig. 4-5, a MOSFET chip package structure includes a package body 1, wherein the package body 1 encapsulates a chip 6, a carrier, a bonding pad 2 and a connection post 4, the package body 1 encapsulates the chip 6 adhered to the carrier, the bottom surfaces of the carrier and the bonding pad 2 are coplanar with the bottom surface of the package body 1, the bottom of the connection post 4 is electrically connected with the bonding pad 2, the chip 6 is adhered to the carrier through conductive silver adhesive, the carrier is a lead frame or a substrate, and the bonding pad 2 is exposed to the bottom surface of the package body 1 after encapsulation and is plated with tin or gold to prevent oxidation.
The grid electrode 7 and the source electrode 8 on the opposite surfaces of the chip 6 and the bonding surface are respectively electroplated with a bump 3, a wiring layer 5 is electroplated between the bump 3 and the connecting column 4, the top surfaces of the three are connected and leveled and are positioned on the same horizontal plane, the bump 3 is a metal copper block with a leveled upper surface, the metal copper block is respectively electroplated on the exposed surfaces of the grid electrode 7 and the source electrode 8 of the chip 6, the areas of the metal copper block are respectively smaller than the grid electrode 7 and the source electrode 8, the height of the bump 3 is more than 40 mu m, so that the electric intercommunication is prevented, and the connecting column 4, the bump 3 and the wiring layer 5 are all made of the same material.
The application of the invention: the bump 3 is directly electroplated in the area of the chip 6, the rear electroplating connecting column 4 and the wiring layer 5 are directly and flatly connected, and when other conditions are the same, the packaging size depends on the height of the bump 3, the packaging size is further compressed, the performances of process electrical property, heat dissipation and the like are similar, the structure is simple, and the cost is reduced.
All the steps using the electroplating process form electroplating protection on the surface through the photoetching technology of exposure and development, then form a metal seed layer in a to-be-electroplated area through sputtering or copper deposition, the metal seed layer is made of copper, the metal seed layer is used for guaranteeing the binding force between the subsequently electroplated metal and plastic packaging materials, and meanwhile, the surface to which conductive ions are attached is provided for electroplating, so that the electroplating effect is guaranteed.
All the steps of the packaging process are carried out by using a mode of injection molding of plastic packaging materials to form packaging through cooperation with mould pressing, and the plastic packaging materials adopted in the application are epoxy resin plastic packaging materials, so that the cost is low and the curing performance is good.
It will be understood that the present application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the present application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A process for packaging a MOSFET chip, comprising the steps of:
bump formation step: electroplating on the active surface of the wafer, and forming a bump electrically connected with the grid and the source electrode respectively, wherein the heights of the bump on the grid and the bump on the source electrode are equal;
and (3) a patch encapsulation step: after cutting the wafer into single chips, respectively bonding the passive surfaces of the single chips to corresponding carriers, and integrally encapsulating and grinding the active surfaces to enable the encapsulated top surfaces to be coplanar with the bump top surfaces;
drilling: drilling the area of the top surface of the encapsulation so that the drilling is vertically connected with the bonding pad at the bottom of the encapsulation;
electroplating and encapsulating: electroplating a connecting column in the drilled hole, electroplating a wiring layer between the connecting column and the bump, wherein the top surfaces of the connecting column, the bump and the wiring layer are connected and leveled and are in the same horizontal plane, the packaging size depends on the height of the bump, the whole packaging is carried out, and the electrical property of the chip electrode is transmitted to the bonding pad through the bump and the wiring layer;
cutting: cutting the encapsulated package body at the cutting path to obtain a single product.
2. The process of claim 1, wherein in the bump forming step, the bump is a metal copper block with a flat upper surface, which is electroplated on the exposed surfaces of the gate and the source, respectively, and has an area smaller than the areas of the gate and the source, respectively.
3. The process of claim 2, wherein in the bump forming step, the height of the bump is greater than 40 μm to prevent electrical interconnection.
4. A MOSFET chip packaging process according to claim 3, wherein in the chip encapsulation step, the chip is attached to a carrier, which is a lead frame or a substrate, by means of a conductive silver paste.
5. The process of claim 4, wherein the connecting pillars, bumps and wiring layers are made of the same material in the electroplating and encapsulating steps.
6. The process of claim 5, wherein the dicing step further comprises plating tin or gold on the land surface exposed to the bottom surface of the package after encapsulation to prevent oxidation.
7. The utility model provides a packaging structure of MOSFET chip, includes the packaging body, the packaging body encapsulates has chip, carrier, pad and spliced pole, the packaging body encapsulates the chip of bonding on the carrier, carrier and pad bottom surface and packaging body bottom surface coplane, spliced pole bottom and pad electric connection, its characterized in that, electroplate respectively on the grid and the source of chip and bonding surface opposite face has a lug, electroplate between lug and the spliced pole has the wiring layer, and three top surface is connected and is leveled, and is in same horizontal plane, and the encapsulation size depends on the height of lug.
8. The MOSFET die package of claim 7 wherein said bumps are metal copper bumps with flat upper surfaces, which are plated on exposed surfaces of the gate and source of the die, respectively, and have areas smaller than the gate and source, respectively, and have a height of > 40 μm to prevent electrical interconnection, and said connection posts, bumps, and wiring layers are all of the same material.
9. The MOSFET die package of claim 7, wherein the die is bonded to a carrier, which is a leadframe or a substrate, by conductive silver paste.
10. The MOSFET die package of claim 7 wherein said bond pads are encapsulated and then exposed to the bottom surface of the package and plated with tin or gold to prevent oxidation.
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| JP2004327757A (en) * | 2003-04-25 | 2004-11-18 | Toshiba Corp | Semiconductor device |
| JP2007529105A (en) * | 2003-07-16 | 2007-10-18 | 松下電器産業株式会社 | Semiconductor light emitting device, method of manufacturing the same, lighting device and display device |
| US20060145319A1 (en) * | 2004-12-31 | 2006-07-06 | Ming Sun | Flip chip contact (FCC) power package |
| KR100601493B1 (en) * | 2004-12-30 | 2006-07-18 | 삼성전기주식회사 | BGA package having a bonding pad become half etching and cut plating gold lines and manufacturing method thereof |
| JP2008135627A (en) * | 2006-11-29 | 2008-06-12 | Nec Electronics Corp | Semiconductor device |
| CN201458083U (en) * | 2009-07-23 | 2010-05-12 | 北京时代民芯科技有限公司 | IC packing box with ceramic quad package |
| US8987878B2 (en) * | 2010-10-29 | 2015-03-24 | Alpha And Omega Semiconductor Incorporated | Substrateless power device packages |
| JP6031059B2 (en) * | 2014-03-31 | 2016-11-24 | 信越化学工業株式会社 | Semiconductor device, stacked semiconductor device, post-sealing stacked semiconductor device, and manufacturing method thereof |
| CN106997851A (en) * | 2016-01-23 | 2017-08-01 | 重庆三峡学院 | A kind of wafer scale（Or panel level）The preparation method of sensor chip encapsulation |
| CN108878297A (en) * | 2018-07-20 | 2018-11-23 | 合肥矽迈微电子科技有限公司 | Chip-packaging structure and preparation method thereof |
| CN110473795B (en) * | 2019-09-02 | 2024-02-23 | 合肥矽迈微电子科技有限公司 | Layered isolation packaging structure and process for large-size chip |
| CN112825310A (en) * | 2019-11-21 | 2021-05-21 | 浙江荷清柔性电子技术有限公司 | Packaging structure and flexible integrated packaging method of ultrathin chip |
| CN110828431A (en) * | 2019-12-06 | 2020-02-21 | 上海先方半导体有限公司 | Plastic package structure for three-dimensional fan-out type packaging |
| CN112928028A (en) * | 2021-01-22 | 2021-06-08 | 广东佛智芯微电子技术研究有限公司 | Board-level chip packaging method with embedded circuit and packaging structure thereof |
| CN115547852B (en) * | 2022-12-01 | 2023-03-07 | 合肥矽迈微电子科技有限公司 | Semi-finished product structure of high-power chip, device and packaging process of device |
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