CN108878297A - Chip-packaging structure and preparation method thereof - Google Patents
Chip-packaging structure and preparation method thereof Download PDFInfo
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- CN108878297A CN108878297A CN201810805579.7A CN201810805579A CN108878297A CN 108878297 A CN108878297 A CN 108878297A CN 201810805579 A CN201810805579 A CN 201810805579A CN 108878297 A CN108878297 A CN 108878297A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 60
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000011068 loading method Methods 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 91
- 239000012790 adhesive layer Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 14
- 238000000034 method Methods 0.000 description 10
- 239000005022 packaging material Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001868 water Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention provides a kind of chip-packaging structure and preparation method thereof, and chip-packaging structure includes：One lead frame, the lead frame have an at least Ji Dao and an at least pin；An at least chip is arranged on the Ji Dao, and the back side of each chip is connect with the loading end of the Ji Dao, and multiple conductive bumps connecting with the weld pad of chip are provided on the active face of each chip；An at least conductive column is arranged in the pin upper surface；At least one reroutes layer, connect respectively with the conductive bump and the conductive column, the weld pad of the chip is connected to the pin.The advantage of the invention is that, chip-packaging structure of the present invention is radiated by Ji Dao, the chip passes through conductive bump, rewiring layer and conductive column connection and pin, with high thermal conductivity and good electric conductivity, adapt to the chip package and modularized encapsulation of the highly conductive demand of high-power and high thermal conductivity, the electrical and thermal conductivity performance of chip package can greatly be optimized, effectively promote the service performance of chip.
Description
Technical field
The present invention relates to field of semiconductor package more particularly to a kind of chip-packaging structure and preparation method thereof.
Background technique
In IC package industry, Wire Bonding Technology (Wire Bonding, abbreviation WB) using metal wire realize chip with
Exposed pin connection conducting, its shortcoming is that, packaging body is limited to the diameter and length of metal wire itself, core in terms of electrical property
The electric conductivity of piece is poor.
Flip-chip welding technology (Flip Chip Bonding Technology, abbreviation FC) is a kind of to be connected to chip
Multiple chip mats are configured on the active surface of chip by the encapsulation technology of carrier mainly in the way of the array of face,
And convex block is formed on chip mat, then by chip turn-over and then via these convex blocks, these chip mats of chip are distinguished
Contact on electricity and structural connectivity to carrier.Since flip-chip welding technology is applicable to the chip package knot of high pin count
Structure, and there is many advantages, such as reducing chip package area and shortening signal transmission path simultaneously, so that flip-chip welding technology
The chip package field of high-order is had been widely used at present.Its shortcoming is that since chip is by convex block or weight cloth
The modes such as line layer are connect with exposed pin, and there are the filling and isolation of plastic packaging layer in centre, so that the heating conduction of chip is poor.
Therefore, develop a kind of encapsulating structure with excellent conductive performance and heating conduction to be of great significance.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of chip-packaging structures and preparation method thereof, can have
There are high thermal conductivity and good electric conductivity, adapts to the chip package and modularization envelope of the highly conductive demand of high-power and high thermal conductivity
Dress, can greatly optimize the electrical and thermal conductivity performance of chip package, effectively promote the service performance of chip.
To solve the above-mentioned problems, the present invention provides a kind of chip-packaging structures, including：One lead frame, it is described to draw
Wire frame has an at least Ji Dao and an at least pin；An at least chip, be arranged on the Ji Dao, the back side of each chip with
The loading end of the Ji Dao connects, and is provided with multiple conductive bumps connecting with the weld pad of chip on the active face of each chip；
An at least conductive column is arranged in the pin upper surface；At least one reroute layer, respectively with the conductive bump and the conduction
Column connection, is connected to the pin for the weld pad of the chip.
In one embodiment, the chip is connect with the loading end of the Ji Dao by conductive and heat-conductive adhesive layer.
In one embodiment, the Ji Dao is conductive base island.
In one embodiment, the back side Ji Dao opposite with loading end is provided with external pin.
In one embodiment, it is connected between adjacent rewiring layer by conducting block.
The present invention also provides a kind of preparation methods of chip-packaging structure, include the following steps：One lead frame, institute are provided
Lead frame is stated with an at least Ji Dao and an at least pin；An at least chip is provided, is formed on the active face of each chip
Conductive bump, the conductive bump are connect with the weld pad of each chip；A conductive column is formed, the conductive column setting is drawn described
Foot upper surface；The chip is welded on the loading end of the Ji Dao, the active of the chip faces upward, with the active face
The opposite back side is connect with the loading end of the Ji Dao；Plastic-sealed body is formed, and exposes upper surface and the conductive column of conductive bump
Upper surface；Or before forming conductive column step, chip is welded on the loading end of the Ji Dao；Plastic packaging step is carried out again
Suddenly, plastic-sealed body is formed, and exposes the upper surface of pin upper surface and conductive bump；After plastic packaging step, in the upper table of pin
Face forms conductive column, and the upper surface of the conductive column is exposed to plastic-sealed body；It forms at least one and reroutes layer and plastic packaging, the heavy cloth
Line layer is connect with the conductive bump and the conductive column respectively, and the weld pad of the chip is connected to the pin, is formed
Chip-packaging structure.
In one embodiment, the back side Ji Dao opposite with loading end is provided with external pin.
In one embodiment, in the case where plastic packaging is carried out after on the loading end that chip is welded on the Ji Dao, described
The surface of plastic-sealed body forms through-hole, and the upper surface of pin, conductive material is filled in through-hole, is led with being formed at the through-hole exposure
The upper surface of electric column, the conductive column is exposed to plastic-sealed body.
In one embodiment, forming the step of multilayer reroutes layer includes：Form one first rewiring layer, first weight
Wiring layer is connect with the conductive bump and partially electronically conductive column；First reroutes layer described in plastic packaging, and exposes the first weight of part
Wiring layer；One second is formed on plastic-sealed body and reroutes layer, and described second, which reroutes layer, passes through an at least conducting block and described the
At the exposure of one rewiring layer and partially electronically conductive column connects；And so on, multiple rewiring layers are formed, so that each conductive bump
It is connect with a pin.
In one embodiment, the lead frame further includes a supporting layer, and the supporting layer is arranged in the lead frame
The back side, plastic packaging reroute layer step after, further include the steps that the removal supporting layer.
It is an advantage of the current invention that chip-packaging structure of the present invention by Ji Dao radiate, the chip by conductive bump,
Layer and conductive column connection and pin are rerouted, there is high thermal conductivity and good electric conductivity, adapt to high-power and high thermal conductivity
The chip package and modularized encapsulation of highly conductive demand can greatly optimize the electrical and thermal conductivity performance of chip package, effectively be promoted
The service performance of chip.
Detailed description of the invention
Fig. 1 is the schematic diagram of the first embodiment of chip-packaging structure of the present invention；
Fig. 2 is the schematic diagram of the second embodiment of chip-packaging structure of the present invention；
Fig. 3 A~Fig. 3 H is the process flow chart of an embodiment of preparation method of the present invention；
Fig. 4 is a flow chart of another embodiment of preparation method of the present invention；
Fig. 5 A~Fig. 5 C is a flow chart of another embodiment of preparation method of the present invention；
Fig. 6 A~Fig. 6 C is a flow chart of another embodiment of preparation method of the present invention.
Specific embodiment
The specific embodiment of chip-packaging structure provided by the invention and preparation method thereof is done in detail with reference to the accompanying drawing
It describes in detail bright.
The present invention provides a kind of chip-packaging structure.Fig. 1 is the signal of the first embodiment of chip-packaging structure of the present invention
Figure.Referring to Fig. 1, the chip-packaging structure includes：One lead frame 1, at least a chip 2, at least a conductive column 3 and at least
One reroutes layer 4.
The lead frame 1 has an at least base island 10 and an at least pin 11.In the present embodiment, it is schematically painted
The island Chu Yigeji 10 and two pins 11, described two pins 11 are located at the two sides on base island 10.
Wherein, in the present embodiment, at the back side on the base island 10, i.e., opposite with the loading end on the base island 10 one
Face is provided with an external pin 12, is also equipped with external pin 12 in the lower surface of the pin 11, the external pin 12 be used for it is outer
The electrical connection of portion's structure.Certainly, in other embodiments, can also the island Jin Ji 10 the back side be arranged external pin 12.
Further, the base island 10 is conductive base island, such as copper-based island, and the pin 11 is conductive pin, such as copper draws
Foot.
The chip 2 is arranged on the base island 10.The present invention to the quantity of the chip 2 without limiting, can basis
Actual use is selected.In the present embodiment, the quantity of the chip 2 is one.
The back side of each chip 2 is connect with the loading end on the base island 10, and the back side of the chip 2 can pass through conductive and heat-conductive
Adhesive layer 20 is connect with the loading end on the base island 10.The material of the conductive and heat-conductive adhesive layer includes but is not limited to glue
Water, metal or metal mixture, such as silver paste etc..The back side of the chip 2 is connect with the loading end on the base island 10, is increased
The heat dissipation area of the chip 2 improves the heat dissipation performance of the chip 2.
Multiple conductive studs connecting with the weld pad (not being painted in attached drawing) of chip 2 are provided on the active face of each chip 2
Block 21.The conductive bump 21 can be used metal material and be made, for example, copper product.It is described to lead compared with traditional metal lead wire
Electric convex block 21 increases the area that the weld pad is connect with the external world, improves the electric conductivity of chip.
The conductive column 3 is arranged in 11 upper surface of pin.The conductive column 3 includes but is not limited to metallic conduction post.
The conductive column 3 is conducted with the pin 11.
The rewiring layer 4 is connect with the conductive bump 21 and the conductive column 3 respectively, by the weldering of the chip 2
Pad is connected to the pin 11.In the present embodiment, the chip-packaging structure includes one layer of rewiring layer, which reroutes layer
For patterned conductive layer, each conductive bump 21 is connect with a conductive column 3, so that each conductive bump 21 draws with one
Foot 11 connects.The chip 2 is electrically connected by conductive bump 21, rewiring layer 4, conductive column 3 with the pin 11 realization, energy
Existing metal lead wire is enough avoided to connect the bad disadvantage of brought electric conductivity.
Further, the chip-packaging structure further includes a plastic-sealed body 5, lead frame 1 described in 5 plastic packaging of plastic-sealed body,
Chip 2, conductive column 3 and rewiring layer 4.The plastic-sealed body 5 is made of the material of this field routine.
The present invention also provides a kind of second embodiments of chip-packaging structure.Fig. 2 is chip-packaging structure second of the present invention
The schematic diagram of embodiment.Referring to Fig. 2, the difference of the present embodiment and first embodiment is, the chip-packaging structure includes
Two layers of rewiring layer 4, i.e., first reroutes layer 40 and the second rewiring layer 41.Described first reroutes layer 40 and conductive bump 21
And partially electronically conductive column 3 connects, the second rewiring layer 41 is connect with the first rewiring layer 40 and partially electronically conductive column 3, Jin Ershi
Existing each conductive bump 21 is connect with the electrical connection of pin 11.Described first reroutes layer 40 and the second rewiring layer
41 is graphical, to realize connection.Wherein, it is connected between adjacent rewiring layer by conducting block 42, for example, first weight
It is connected between wiring layer 40 and the second rewiring layer 41 by conducting block 42.The conducting block 42 includes but is not limited to metal
Block.In other embodiments of the present invention, the rewiring layer 4 can be set as needed multiple, can shape using identical method
Layer is rerouted at multilayer.
Wherein, in this second embodiment, the back side on the base island 10 and the back side of the pin 11 and not set outer tube
The back side of foot, the back side of the Ji Dao and the pin is used directly as external pin.
The present invention also provides a kind of preparation methods of chip-packaging structure.The preparation method includes the following steps：
Fig. 3 A is please referred to, a lead frame 1 is provided, the lead frame 1 has at least a base island 10 and at least a pin
11.In the present embodiment, an island Ge Ji 10 and two pins 11 are schematically shown, described two pins 11 are located at base
The two sides on island 10.Wherein, in the present embodiment, the lead frame 1 further includes a supporting layer 13, and the setting of supporting layer 13 exists
The back side of the lead frame 1 is used to support the lead frame 1.In another embodiment, as shown in figure 4, the base island 10
The back side opposite with loading end is provided with external pin 12, and the back side of the pin 11 is also equipped with external pin 12, the supporting layer
13 are arranged except the external pin 12.Wherein, the forming method of the lead frame 1 can be to be formed on supporting layer 13
Metal layer, the graphical metal layer form lead frame, wherein multi-layer graphical figure layer can be formed, so as to formed by
The lead frame that more metal layers are formed, wherein one layer can be used as Ji Dao and pin, wherein another layer can be used as outer limb.
Fig. 3 B is please referred to, an at least chip 2 is provided.Conductive bump 21 is formed on the active face of each chip 2, it is described to lead
The weld pad (not being painted in attached drawing) of each chip 2 of electric convex block 21 connects.In the present embodiment, the quantity of the chip 2 is one.
The conductive bump 21 can be used metal material and be made, for example, copper product.
Fig. 3 C is please referred to, a conductive column 3 is formed, the conductive column 3 is arranged in 11 upper surface of pin.In the present embodiment
In, conductive column 3 is formed on the surface of the pin 11, wherein the side of patterned metal layer can be used in the formation of the conductive column 3
Method is formed, and is the prior art, is repeated no more.The conductive column 2 includes but is not limited to metallic conduction post.The conductive column 3 with
The pin 11 conducts.
Fig. 3 D is please referred to, the chip 2 is welded on the loading end on the base island 10.The chip 2 it is active towards
On, the back side opposite with the active face is connect with the loading end on the base island 10, i.e., the described chip 2 is provided with conductive bump 21
One face upward.The chip 2 is connect by conductive and heat-conductive adhesive layer 20 with the loading end on the base island 10.The conduction is led
The material of hot adhesion oxidant layer includes but is not limited to glue, metal or metal mixture, such as silver paste etc..The back side of the chip 2
It is connect with the loading end on the base island 10, increases the heat dissipation area of the chip 2, improve the heat dissipation performance of the chip 2.
Fig. 3 E is please referred to, forms plastic-sealed body 50, and expose the upper surface of conductive bump 21 and the upper surface of conductive column 3.
Wherein, in plastic packaging, plastic packaging material can cover the upper surface of the conductive bump 21 and the upper surface of conductive column 3, complete in plastic packaging
Afterwards, the method that grinding or etching can be used removes the plastic packaging material of the upper surface of the conductive bump 21 and the upper surface of conductive column 3,
So that the upper surface of conductive bump 21 and the upper surface of conductive column 3 are exposed to the plastic-sealed body 50.Alternatively, in plastic packaging,
The plastic packaging material does not cover the upper surface of the conductive bump 21 and the upper surface of conductive column 3 directly, thus be omitted grinding or
The step of etching.
In another embodiment of preparation method of the present invention, after the step of providing a chip shown in Fig. 3 B, it please join
Fig. 5 A is read, the chip 2 is welded on the loading end on the base island 10；Fig. 5 B is please referred to, plastic packaging is carried out, forms plastic-sealed body
50, and expose the upper surface of 11 upper surface of pin and conductive bump 21；Fig. 5 C is please referred to, is formed and is led in the upper surface of pin 11
Electric column 3, the upper surface of the conductive column 3 are exposed to the plastic-sealed body 50.Wherein, formed Fig. 5 C shown in structure, can be used as
Lower method：Through-hole is formed on the surface of the plastic-sealed body, the through-hole exposes the upper surface of pin, fills in through-hole conductive
Material, to form conductive column, the upper surface of the conductive column is exposed to plastic-sealed body.
Please continue to refer to Fig. 3 F, forms at least one and reroute layer.In the present embodiment, one layer of rewiring layer 4 is formed.It is described
It is graphical to reroute layer 4, is connect respectively with conductive bump 21 and conductive column 3, so that the weld pad of chip and pin 11 are electrically connected
It connects.The forming method for rerouting layer 4 includes but is not limited to the method for using patterned metal layer.
Please refer to Fig. 3 G, plastic packaging.In this step, 4 plastic packaging of rewiring layer is formed by the core using plastic packaging material 51
Chip package.The plastic package method is the conventional method of this field.
In other embodiments, multilayer can be formed and reroute layer.The step of then forming multiple wiring layer include：It please refers to
Fig. 6 A forms one first and reroutes layer 40, described first reroutes layer 40 and the conductive bump after forming plastic-sealed body 50
21 and partially electronically conductive column 3 connect, formed it is described first reroute layer 40 the step of with above-mentioned formation rewiring layer the step of it is identical,
It has been described above, details are not described herein again；Fig. 6 B, plastic packaging are please referred to, and forms one second on plastic-sealed body 60 and reroutes layer
41, the second rewiring layer 41 is connect by an at least conducting block 42 with the first rewiring layer 40 and partially electronically conductive column 3,
And then it connect each conductive bump 42 with pin 11；Fig. 6 C is please referred to, is rerouted using described in 70 plastic packaging of plastic packaging material second
Layer 41 forms chip-packaging structure of the present invention.In other embodiments, and so on, multiple rewiring layers are formed, so that each
Conductive bump 21 is connect with a pin 11.
Fig. 3 H is please referred to, after plastic packaging step, further includes the steps that the removal supporting layer 13, so far, forms this
Invention chip-packaging structure.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of chip-packaging structure, which is characterized in that including：
One lead frame, the lead frame have an at least Ji Dao and an at least pin；
An at least chip is arranged on the Ji Dao, and the back side of each chip is connect with the loading end of the Ji Dao, each chip
Active face on be provided with multiple conductive bumps connecting with the weld pad of chip；
An at least conductive column is arranged in the pin upper surface；
At least one reroutes layer, connect respectively with the conductive bump and the conductive column, and the weld pad of the chip is connected
To the pin.
2. chip-packaging structure according to claim 1, which is characterized in that the loading end of the chip and the Ji Dao are logical
Cross the connection of conductive and heat-conductive adhesive layer.
3. chip-packaging structure according to claim 1, which is characterized in that the Ji Dao is conductive base island.
4. chip-packaging structure according to claim 1, which is characterized in that the back side Ji Dao opposite with loading end is set
It is equipped with external pin.
5. chip-packaging structure according to claim 1, which is characterized in that pass through conducting block between adjacent rewiring layer
Connection.
6. a kind of preparation method of chip-packaging structure, which is characterized in that include the following steps：
A lead frame is provided, the lead frame has an at least Ji Dao and an at least pin；
An at least chip is provided, forms conductive bump, the conductive bump and each chip on the active face of each chip
Weld pad connection；
A conductive column is formed, the conductive column is arranged in the pin upper surface；
The chip is welded on the loading end of the Ji Dao, the active of the chip faces upward, opposite with the active face
The back side connect with the loading end of the Ji Dao；
Plastic-sealed body is formed, and exposes the upper surface of conductive bump and the upper surface of conductive column；Or
Before forming conductive column step, chip is welded on the loading end of the Ji Dao；Plastic packaging step is carried out again, forms modeling
Feng Ti, and expose the upper surface of pin upper surface and conductive bump；After plastic packaging step, conduction is formed in the upper surface of pin
The upper surface of column, the conductive column is exposed to plastic-sealed body；
It forming at least one and reroutes layer and plastic packaging, the rewiring layer is connect with the conductive bump and the conductive column respectively,
The weld pad of the chip is connected to the pin, chip-packaging structure is formed.
7. the preparation method of chip-packaging structure according to claim 6, which is characterized in that the Ji Dao and loading end phase
Pair the back side be provided with external pin.
8. the preparation method of chip-packaging structure according to claim 6, which is characterized in that be welded on the base in chip
In the case where carrying out plastic packaging after on the loading end on island, through-hole, pin at the through-hole exposure are formed on the surface of the plastic-sealed body
Upper surface, conductive material is filled in through-hole, to form conductive column, the upper surface of the conductive column is exposed to plastic-sealed body.
9. the preparation method of chip-packaging structure according to claim 6, which is characterized in that form multilayer and reroute layer
Step includes：
One first rewiring layer is formed, the first rewiring layer is connect with the conductive bump and partially electronically conductive column；
First reroutes layer described in plastic packaging, and exposes part first and reroute layer；
One second is formed on plastic-sealed body and reroutes layer, and described second, which reroutes layer, passes through an at least conducting block and first weight
At the exposure of wiring layer and partially electronically conductive column connects；
And so on, multiple rewiring layers are formed, so that each conductive bump is connect with a pin.
10. the preparation method of chip-packaging structure according to claim 6, which is characterized in that the lead frame also wraps
A supporting layer is included, the back side of the lead frame is arranged in the supporting layer, further includes one after plastic packaging reroutes layer step
The step of removing the supporting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810805579.7A CN108878297A (en) | 2018-07-20 | 2018-07-20 | Chip-packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810805579.7A CN108878297A (en) | 2018-07-20 | 2018-07-20 | Chip-packaging structure and preparation method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN108878297A true CN108878297A (en) | 2018-11-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810805579.7A Pending CN108878297A (en) | 2018-07-20 | 2018-07-20 | Chip-packaging structure and preparation method thereof |
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| CN (1) | CN108878297A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110581079A (en) * | 2019-09-23 | 2019-12-17 | 合肥矽迈微电子科技有限公司 | Fan-out type chip packaging method and fan-out type chip packaging body |
| CN110993579A (en) * | 2019-11-25 | 2020-04-10 | 南京矽力杰半导体技术有限公司 | Packaging structure of power module |
| CN111211096A (en) * | 2020-01-10 | 2020-05-29 | 珠海格力电器股份有限公司 | Chip module packaging structure and packaging method |
| CN111755340A (en) * | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN112309998A (en) * | 2019-07-30 | 2021-02-02 | 华为技术有限公司 | Packaging device, manufacturing method thereof and electronic equipment |
| CN112992835A (en) * | 2019-12-17 | 2021-06-18 | 珠海格力电器股份有限公司 | Semiconductor device and method for manufacturing the same |
| US11189555B2 (en) | 2019-01-30 | 2021-11-30 | Delta Electronics, Inc. | Chip packaging with multilayer conductive circuit |
| WO2022021800A1 (en) * | 2020-07-31 | 2022-02-03 | 矽磐微电子(重庆)有限公司 | Semiconductor encapsulating method and semiconductor encapsulating structure |
| CN115547852A (en) * | 2022-12-01 | 2022-12-30 | 合肥矽迈微电子科技有限公司 | Semi-finished product structure of high-power chip, device and packaging process of device |
| CN115841995A (en) * | 2023-02-13 | 2023-03-24 | 徐州致能半导体有限公司 | Packaging structure and packaging method |
| CN115985783A (en) * | 2023-03-20 | 2023-04-18 | 合肥矽迈微电子科技有限公司 | Packaging structure and process of MOSFET chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779220A (en) * | 2015-03-27 | 2015-07-15 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure and manufacture method thereof |
| US20160163629A1 (en) * | 2014-12-03 | 2016-06-09 | Phoenix Pioneer Technology Co., Ltd | Semiconductor package and method of fabricating the same |
| CN208608186U (en) * | 2018-07-20 | 2019-03-15 | 合肥矽迈微电子科技有限公司 | Chip-packaging structure |
-
2018
- 2018-07-20 CN CN201810805579.7A patent/CN108878297A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160163629A1 (en) * | 2014-12-03 | 2016-06-09 | Phoenix Pioneer Technology Co., Ltd | Semiconductor package and method of fabricating the same |
| CN104779220A (en) * | 2015-03-27 | 2015-07-15 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging structure and manufacture method thereof |
| CN208608186U (en) * | 2018-07-20 | 2019-03-15 | 合肥矽迈微电子科技有限公司 | Chip-packaging structure |
Cited By (16)
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|---|---|---|---|---|
| US11189555B2 (en) | 2019-01-30 | 2021-11-30 | Delta Electronics, Inc. | Chip packaging with multilayer conductive circuit |
| CN112309998A (en) * | 2019-07-30 | 2021-02-02 | 华为技术有限公司 | Packaging device, manufacturing method thereof and electronic equipment |
| CN110581079B (en) * | 2019-09-23 | 2021-09-03 | 合肥矽迈微电子科技有限公司 | Fan-out type chip packaging method and fan-out type chip packaging body |
| CN110581079A (en) * | 2019-09-23 | 2019-12-17 | 合肥矽迈微电子科技有限公司 | Fan-out type chip packaging method and fan-out type chip packaging body |
| US11887942B2 (en) | 2019-11-25 | 2024-01-30 | Hefei Silergy Semiconductor Technology Co., Ltd. | Package structure for power supply module |
| CN110993579A (en) * | 2019-11-25 | 2020-04-10 | 南京矽力杰半导体技术有限公司 | Packaging structure of power module |
| CN112992835A (en) * | 2019-12-17 | 2021-06-18 | 珠海格力电器股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN112992835B (en) * | 2019-12-17 | 2022-08-30 | 珠海格力电器股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN111211096A (en) * | 2020-01-10 | 2020-05-29 | 珠海格力电器股份有限公司 | Chip module packaging structure and packaging method |
| CN111755340A (en) * | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| WO2022021800A1 (en) * | 2020-07-31 | 2022-02-03 | 矽磐微电子(重庆)有限公司 | Semiconductor encapsulating method and semiconductor encapsulating structure |
| CN115547852B (en) * | 2022-12-01 | 2023-03-07 | 合肥矽迈微电子科技有限公司 | Semi-finished product structure of high-power chip, device and packaging process of device |
| CN115547852A (en) * | 2022-12-01 | 2022-12-30 | 合肥矽迈微电子科技有限公司 | Semi-finished product structure of high-power chip, device and packaging process of device |
| CN115841995A (en) * | 2023-02-13 | 2023-03-24 | 徐州致能半导体有限公司 | Packaging structure and packaging method |
| CN115841995B (en) * | 2023-02-13 | 2023-07-14 | 徐州致能半导体有限公司 | Packaging structure and packaging method |
| CN115985783A (en) * | 2023-03-20 | 2023-04-18 | 合肥矽迈微电子科技有限公司 | Packaging structure and process of MOSFET chip |
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