KR20020065739A - Chip scale package and method for fabricating the same - Google Patents
Chip scale package and method for fabricating the same Download PDFInfo
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- KR20020065739A KR20020065739A KR1020010005912A KR20010005912A KR20020065739A KR 20020065739 A KR20020065739 A KR 20020065739A KR 1020010005912 A KR1020010005912 A KR 1020010005912A KR 20010005912 A KR20010005912 A KR 20010005912A KR 20020065739 A KR20020065739 A KR 20020065739A
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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- H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
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Abstract
Description
본 발명은 칩스케일 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 경박단소화되며 열방출 성능이 향상된 새로운 구조의 칩스케일 반도체 패키지를 제공하기 위한 것이다.The present invention relates to a chip scale package and a method of manufacturing the same, and more particularly, to provide a chip scale semiconductor package having a novel structure, which is light in weight and short, and has improved heat dissipation performance.
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다.In general, the packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. I'm making it.
한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 패키징 공정을 거치게 된다.On the other hand, in general, semiconductor devices are separated into individual chips in a wafer in which integrated circuits are formed, and then mounted in a plastic package or a ceramic package, and then subjected to a packaging process for assembling the substrate to facilitate mounting on the substrate.
이와 같이 행해지는 반도체소자에 대한 패키징 공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다.The main purpose of the packaging step for the semiconductor element thus performed is to secure the shape and protect the function for mounting on the substrate or the socket.
또한, 최근에는 집적회로의 고집적화에 따라 다핀화, 미세조립기술, 또 실장형태의 다양화에 따른 패키지의 다종류화 등, 조립공정과 관련된 기술도 각각 세분된 분야에 따라 크게 변화하고 있다.In addition, in recent years, technologies related to the assembly process, such as multi-pinning, micro-assembly technology, and package variety due to the diversification of the mounting type according to the high integration of integrated circuits, are also greatly changed according to the subdivided fields.
반도체 조립공정의 개요에 대해 현재 가장 많이 사용되고 있는 플라스틱 타입의 반도체소자를 예로 들어 설명하면 다음과 같다.An overview of the semiconductor assembly process will be described below with an example of a plastic type semiconductor device which is most used.
먼저, 전기적 회로가 형성된 웨이퍼를 각각의 단일 칩으로 분리하는데, 이때 Si(실리콘)는 모스경도 7로서 딱딱하고 깨지기 쉬운 성질을 갖고 있으므로 웨이퍼의 제조시 미리 분리할 라인에 절단하기 위한 물질을 넣어두고 이 분리라인을 따라 브레이크 응력을 가해 파괴, 분리시키는 방법을 취하는 경우가 많다.First, the wafer on which the electrical circuit is formed is separated into each single chip, and Si (silicon) has a Mohs hardness of 7 and is hard and brittle, so that a material for cutting is placed in a line to be separated in advance in manufacturing the wafer. In many cases, a break stress is applied along this separation line to break and separate.
또한, 분리된 각각의 반도체 칩은 리드프레임의 다이패드에 본딩되고, 이때의 접합방법은 Au-Si 공정(共晶)법, 납땜법, 수지접착법 등이 있으며 용도에 따라 알맞은 방법이 선택되어 사용된다.In addition, each separated semiconductor chip is bonded to the die pad of the lead frame, and the bonding method is Au-Si process, soldering method, resin bonding method, etc. Used.
한편, 전술한 바와 같이 반도체 칩을 리드프레임의 다이패드에 접착하는 목적은 조립이 완료된 후 기판에 실장시키기 위해서 뿐만 아니라, 전기적 입출력단자나 어스(earth)를 겸하는 일도 있으며 소자의 동작시 발생하는 열의 방열통로로서도 필요로 하는 경우가 있기 때문이다.On the other hand, as described above, the purpose of bonding the semiconductor chip to the die pad of the lead frame is not only to be mounted on the substrate after assembly is completed, but also to serve as an electrical input / output terminal or earth, This is because the heat dissipation path may be required.
상기와 같이 반도체 칩을 본딩한 후에는 반도체칩의 칩패드와 리드프레임의 인너리드를 와이어로 본딩하므로써 연결하게 되며, 와이어 본딩의 방법으로 플라스틱 봉함 패키지에서는 일반적으로 골드 와이어를 사용한 열압착법 또는 열압착법과 초음파법을 혼용한 방법이 주로 이용되고 있다.After bonding the semiconductor chip as described above, the chip pad of the semiconductor chip and the inner lead of the lead frame are connected by wire bonding. In the plastic sealing package, the wire bonding method or the thermal bonding method using gold wire is generally performed. The method which mixed the compression method and the ultrasonic method is mainly used.
또한, 와이어 본딩에 의해 반도체 칩과 인너리드가 전기적으로 연결된 후에는 칩을 고순도의 에폭시 수지를 사용하여 성형 봉합하므로써 몰드바디를 형성시키는 몰딩공정이 수행되는데, 이때 사용되는 에폭시 수지는 집적회로의 신뢰성을 좌우하는 중요한 요소이며, 수지의 고순도화와 몰딩시 집적회로에 주어지는 응력을 저감시키기 위한 저응력화 등의 개선이 추진되고 있다.In addition, after the semiconductor chip and the inner lead are electrically connected by wire bonding, a molding process of forming a mold body by forming and sealing the chip using a high purity epoxy resin is performed. In addition, the improvement of the high purity of the resin and the reduction of the stress for reducing the stress applied to the integrated circuit during molding are being promoted.
그리고, 상기한 공정이 완료된 후에는 IC 패키지를 소켓이나 기판에 실장하기 위해 아웃터리드(outer lead)를 소정의 형상으로 절단하고 성형하는 공정이 행해지며, 아웃터리드에는 실장접합성(납땜성)을 향상시키기 위해 도금이나 납딥(dip)이 처리된다.After the above process is completed, a process of cutting and molding an outer lead into a predetermined shape is carried out to mount the IC package on a socket or a substrate, and the mount is improved in solderability. Plating or dip dips are applied to make them.
한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 패키지의 대표적인 예로서는 전술한 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package), BGA 패키지( Ball Grid Array package), BLP(Bottom Leaded Package) 등이 있으며, 계속 다핀(多-pin)화 또는 경박단소(輕薄短小)화 되고 있다.On the other hand, semiconductor packages are divided into various types according to the mounting type and the lead type. As a representative example of the package, in addition to the above-described dual inline package (DIP), QFP (Quad Flat Package), TSOP (Thin Small Outline Package), and BGA package (Ball) Grid Array package (BLP), Bottom Leaded Package (BLP), and the like, continue to be multi-pin or light and thin.
상기한 패키지 타입중, BGA 패키지(Ball Grid Array package)는 반도체 칩이 부착된 기판의 이면에 구형의 솔더볼을 소정의 상태로 배열(Array)하여 아웃터리드(outer lead) 대신으로 사용하게 되며, 상기 BGA 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 할 수 있으며, QFP와는 달리 리드의 변형이 없는 장점이 있다.Among the above package types, the BGA package (Ball Grid Array package) is used to replace the outer lead by arranging a spherical solder ball in a predetermined state on the back side of the substrate on which the semiconductor chip is attached. The BGA package can make the package body area smaller than the QFP (Quad Flat Package) type, and unlike QFP, there is an advantage that there is no deformation of the lead.
그러나, 상기 BGA 패키지는 기존의 리드프레임에 비해 값이 비싼 회로기판을 사용하므로 제조원가가 높아지고, 반도체 칩 및 골드 와이어의 보호를 위해 봉지공정 수행시 상형 및 하형에 의해 회로기판이 눌러져 솔더마스크에 크랙이 발생할 우려가 높아지는 등의 단점이 있다.However, since the BGA package uses a circuit board that is more expensive than a conventional lead frame, the manufacturing cost increases, and when the encapsulation process is performed to protect the semiconductor chip and the gold wire, the circuit board is pressed by the upper and lower molds and cracks in the solder mask. There are disadvantages such as a high possibility of occurrence.
그리고, 상기BLP(Bottom Leaded Package)는 패키지 몸체의 바텀면을 통해 노출된 리드를 이용하여 기판에 실장하므로, 패키지 몸체의 두께를 아웃터리드를 갖는 DIP나 QFP 타입에 비해 작게 할 수 있다.In addition, since the bottom leaded package (BLP) is mounted on the substrate using leads exposed through the bottom surface of the package body, the thickness of the package body may be smaller than that of a DIP or QFP type having an outwardly shaped product.
아울러, 최근에는 마이크로 BGA 패키지등 여러 가지 타입의 칩스케일 패키지가 다양하게 개발되고 있는 실정이다.In addition, various types of chip scale packages, such as micro BGA packages, have been developed in recent years.
한편, 상기한 반도체 패키지들은 실장면적, 입출력 단자수, 전기적 신뢰성, 제조공정의 유연성, 제조비용등에 있어 제각기 장점 및 단점을 갖고 있다.Meanwhile, the semiconductor packages have advantages and disadvantages in terms of mounting area, number of input / output terminals, electrical reliability, manufacturing process flexibility, manufacturing cost, and the like.
따라서, 상기한 각 패키지들의 장점을 살리면서 단점을 해소한 새로운 타입의 반도체 패키지가 지속적으로 연구 개발되고 있는 실정이다.Therefore, a new type of semiconductor package that solves the disadvantages while making use of the advantages of the above-mentioned packages is constantly being researched and developed.
본 발명은 상기한 바와 같이 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 칩스케일 반도체 패키지를 제공하기 위한 것으로서, 구조적 측면에서 경박단소하며 방열성능이 뛰어난 신뢰성 높은 반도체 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention is to provide a new type of chip-scale semiconductor package to solve the disadvantages while maximizing the advantages of the existing semiconductor package as described above, and in terms of structure, the semiconductor package with high reliability and excellent heat dissipation performance and Its purpose is to provide its manufacturing method.
도 1은 본 발명의 제1실시예에 따른 칩스케일 패키지를 나타낸 종단면도1 is a longitudinal sectional view showing a chip scale package according to a first embodiment of the present invention;
도 2는 도 1의 서키트 테이프를 나타낸 평면도2 is a plan view showing the circuit tape of FIG.
도 3은 도 2의 저면도3 is a bottom view of FIG. 2
도 4a 내지 도 4d는 제1실시예에 따른 칩스케일 패키지 제조과정을 설명하기 위한 종단면도4A to 4D are longitudinal cross-sectional views illustrating a process of manufacturing a chip scale package according to a first embodiment;
도 5는 본 발명의 제2실시예에 따른 칩스케일 패키지를 나타낸 종단면도5 is a longitudinal sectional view showing a chip scale package according to a second embodiment of the present invention;
도 6은 도 5의 서키트 테이프를 나타낸 평면도6 is a plan view showing the circuit tape of FIG.
도 7은 도 6의 저면도FIG. 7 is a bottom view of FIG. 6
도 8a 내지 도 8d는 제2실시예에 따른 칩스케일 패키지 제조과정을 설명하기 위한 종단면도8A to 8D are longitudinal cross-sectional views illustrating a process of manufacturing a chip scale package according to a second embodiment;
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:반도체칩2:서키트 테이프1: Semiconductor chip 2: Circuit tape
3:와이어본딩패드4:회로배선3: wire bonding pad 4: circuit wiring
5:솔더랜드6:어드헤시브5: Solderland 6: Advanced
7:와이어8:몰드바디7: Wire 8: Molded Body
9:윈도우10:히트싱크9: Windows 10: Heatsink
상기한 목적을 달성하기 위한 본 발명의 제1형태에 따르면, 상면에 와이어본딩패드가 형성되며 저면에는 상기 와이어본딩패드와 연결되는 회로배선 및 솔더랜드가 형성된 서키트 테이프와, 상기 서키트 테이프 상면에 부착되는 반도체칩과, 상기 반도체칩의 칩패드와 서키트 테이프의 와이어본딩패드를 연결하는 와이어와,상기 반도체칩과 와이어가 봉지되도록 서키트 테이프 상부 영역에 형성되는 몰드바디를 포함하여 구성됨을 특징으로 하는 칩스케일 패키지가 제공된다.According to a first aspect of the present invention for achieving the above object, a wire bonding pad is formed on an upper surface, a circuit tape and a solder land formed on the bottom surface are connected to the wire bonding pad, and attached to an upper surface of the circuit tape. A semiconductor chip, a wire connecting the chip pad of the semiconductor chip and a wire bonding pad of the circuit tape, and a mold body formed in an upper region of the circuit tape so that the wire is encapsulated. A scale package is provided.
상기한 목적을 달성하기 위한 본 발명의 제2형태에 따르면, 상면에 와이어본딩패드가 형성되고 저면에는 상기 와이어본딩패드와 연결되는 회로배선 및 솔더랜드가 형성되며 중앙부에 윈도우가 형성된 서키트 테이프와, 상기 서키트 테이프의 윈도우 상에 부착되는 히트싱크와, 상기 히트싱크 상면에 부착되는 반도체칩과, 상기 반도체칩의 칩패드와 서키트 테이프의 와이어본딩패드를 연결하는 와이어와, 상기 반도체칩과 와이어가 봉지되도록 서키트 테이프 상부 영역에 형성되는 몰드바디를 포함하여 구성됨을 특징으로 하는 칩스케일 패키지가 제공된다.According to a second aspect of the present invention for achieving the above object, a circuit bonding pad is formed on the upper surface and a circuit wiring and solder land connected to the wire bonding pad is formed on the bottom surface and the window tape is formed in the center, A heat sink attached to the window of the circuit tape, a semiconductor chip attached to an upper surface of the heat sink, a wire connecting the chip pad of the semiconductor chip and the wire bonding pad of the circuit tape, and the semiconductor chip and the wire are encapsulated. A chip scale package is provided which comprises a mold body formed in the upper portion of the circuit tape.
한편, 상기한 목적을 달성하기 위한 본 발명의 제3형태에 따르면, 상면에 와이어본딩패드가 형성되며 저면에는 상기 와이어본딩패드와 연결되는 회로배선 및 솔더랜드가 형성된 서키트 테이프 상면에 반도체칩을 부착하는 단계와, 상기 반도체칩의 칩패드와 서키트 테이프의 와이어본딩패드를 와이어로 연결하는 단계와, 상기 반도체칩과 와이어가 봉지되도록 서키트 테이프 상부 영역을 봉지하여 몰드바디를 형성하는 단계를 포함하여서 됨을 특징으로 하는 칩스케일 패키지 제조방법이 제공된다.Meanwhile, according to a third aspect of the present invention for achieving the above object, a wire bonding pad is formed on an upper surface, and a semiconductor chip is attached to an upper surface of a circuit tape on which a circuit wiring and solder lands are connected to the wire bonding pad. And connecting the chip pad of the semiconductor chip and the wire bonding pad of the circuit tape with a wire, and encapsulating the upper area of the circuit tape so that the semiconductor chip and the wire are encapsulated to form a mold body. A chip scale package manufacturing method is provided.
한편, 상기한 목적을 달성하기 위한 본 발명의 제4형태에 따르면, 상면에 와이어본딩패드가 형성되고 저면에는 상기 와이어본딩패드와 연결되는 회로배선 및 솔더랜드가 형성되며 중앙부에 윈도우가 형성된 서키트 테이프의 윈도우 상에 히트싱크를 부착되는 단계와, 상기 히트싱크 상면에 반도체칩을 부착하는 단계와, 상기반도체칩의 칩패드와 서키트 테이프의 와이어본딩패드를 와이어로 연결하는 단계와, 상기 반도체칩과 와이어가 봉지되도록 히트싱크 및 서키트 테이프 상부 영역을 봉지하여 몰드바디를 형성하는 단계를 포함하여서 됨을 특징으로 하는 칩스케일 패키지 제조방법이 제공된다.On the other hand, according to the fourth aspect of the present invention for achieving the above object, a circuit bonding pad is formed on the upper surface and the circuit wiring and solder land connected to the wire bonding pad is formed on the bottom surface, the circuit tape formed with a window in the center Attaching a heat sink on a window of the semiconductor substrate; attaching a semiconductor chip to an upper surface of the heat sink; connecting a chip pad of the semiconductor chip and a wire bonding pad of a circuit tape with a wire; A method of manufacturing a chip scale package is provided, which comprises forming a mold body by encapsulating a heat sink and a circuit tape upper region such that a wire is encapsulated.
먼저, 본 발명의 제1실시예를 첨부도면 도 1 내지 도 4d를 참조하여 설명하면 다음과 같다.First, the first embodiment of the present invention will be described with reference to the accompanying drawings, FIGS. 1 to 4D.
도 1은 본 발명의 제1실시예에 따른 칩스케일 패키지를 나타낸 종단면도이고, 도 2는 도 1의 서키트 테이프를 나타낸 평면도이며, 도 3은 도 2의 저면도로서, 본 발명은 상면에 와이어본딩패드(3)가 형성되며 저면에는 상기 와이어본딩패드(3)와 연결되는 회로배선(4) 및 솔더랜드(5)가 형성된 서키트 테이프(2)와, 상기 서키트 테이프(2) 상면에 부착되는 반도체칩(1)과, 상기 반도체칩(1)의 칩패드와 서키트 테이프(2)의 와이어본딩패드(3)를 연결하는 와이어(7)와, 상기 반도체칩(1)과 와이어(7)가 봉지되도록 서키트 테이프(2) 상부 영역에 형성되는 몰드바디(8)를 포함하여 구성된다.1 is a longitudinal cross-sectional view illustrating a chip scale package according to a first embodiment of the present invention, FIG. 2 is a plan view illustrating the circuit tape of FIG. 1, and FIG. 3 is a bottom view of FIG. 2. A bonding pad 3 is formed and a circuit tape 4 and a solder land 5 connected to the wire bonding pad 3 are formed on a bottom surface of the circuit board 2, and a top surface of the circuit tape 2 is attached to the circuit pad 4. The semiconductor chip 1, the wire 7 connecting the chip pad of the semiconductor chip 1 and the wire bonding pad 3 of the circuit tape 2, and the semiconductor chip 1 and the wire 7 It comprises a mold body (8) formed in the upper region of the circuit tape 2 to be sealed.
이 때, 상기 반도체칩(1)과 서키트 테이프(2) 사이에는 어드헤시브(6)가 개재되며, 상기 솔더랜드(5)에는 솔더볼(도시는 생략함)이 부착가능하다.At this time, an additive 6 is interposed between the semiconductor chip 1 and the circuit tape 2, and solder balls (not shown) may be attached to the solder land 5.
이와 같이 구성된 본 발명의 제1실시예에 따른 칩스케일 패키지 제조 과정을 도 4a 내지 도 4d를 참조하여 설명하면 다음과 같다.The chip scale package manufacturing process according to the first embodiment of the present invention configured as described above will be described with reference to FIGS. 4A to 4D.
먼저, 상면에 와이어본딩패드(3)가 형성되며 저면에는 상기 와이어본딩패드(3)와 연결되는 회로배선(4) 및 솔더랜드(5)가 형성된 서키트 테이프(2)를 준비한 후, 상기 서키트 테이프(2) 상면에 반도체칩(1)을 부착한다.First, a wire bonding pad 3 is formed on an upper surface thereof, and a circuit tape 4 and a solder tape 5 having solder lands 5 connected to the wire bonding pad 3 are prepared on the bottom surface thereof, and then the circuit tape (2) The semiconductor chip 1 is attached to the upper surface.
그 후, 상기 반도체칩(1)의 칩패드와 서키트 테이프(2)의 와이어본딩패드(3)를 와이어(7)로 연결한다.Thereafter, the chip pad of the semiconductor chip 1 and the wire bonding pad 3 of the circuit tape 2 are connected with the wire 7.
이 때, 기존의 일반적인 방식의 와이어(7) 본딩순서와는 달리 와이어본딩패드(3) 상에 볼본딩(ball bonding)을 실시하고, 반도체칩(1)의 칩패드상에 스티치 본딩(stitch bonding)을 실시하게 된다.At this time, unlike the conventional bonding method of the wire 7, ball bonding is performed on the wire bonding pad 3, and stitch bonding is performed on the chip pad of the semiconductor chip 1. ).
이는, 열적충격이 가해질 경우 열팽창계수차에 의한 열응력(thermal stress)을 쉽게 흡수할 수 있도록 하기 위함이다.This is to facilitate absorption of thermal stress due to thermal expansion coefficient aberration when thermal shock is applied.
한편, 와이어(7) 본딩후에는 상기 반도체칩(1)과 와이어(7)가 봉지되도록 서키트 테이프(2) 상부 영역을 봉지하여 몰드바디(8)를 형성하게 된다.Meanwhile, after the wire 7 is bonded, the mold body 8 is formed by encapsulating the upper area of the circuit tape 2 so that the semiconductor chip 1 and the wire 7 are sealed.
이하, 본 발명의 제2실시예에 따른 칩스케일 패키지를 설명하고자 한다.Hereinafter, a chip scale package according to a second embodiment of the present invention will be described.
도 5는 본 발명의 제2실시예에 따른 칩스케일 패키지를 나타낸 종단면도이고, 도 6은 도 5의 서키트 테이프를 나타낸 평면도이며, 도 7은 도 6의 저면도로서, 본 발명의 제2실시예에 따른 칩스케일 패키지는 상면에 와이어본딩패드(3)가 형성되고 저면에는 상기 와이어본딩패드(3)와 연결되는 회로배선(4) 및 솔더랜드(5)가 형성되며 중앙부에 윈도우(9)가 형성된 서키트 테이프(2)와, 상기 서키트 테이프(2)의 윈도우(9) 상에 부착되는 히트싱크(10)와, 상기 히트싱크(10) 상면에 부착되는 반도체칩(1)과, 상기 반도체칩(1)의 칩패드와 서키트 테이프(2)의 와이어본딩패드(3)를 연결하는 와이어(7)와, 상기 반도체칩(1)과 와이어(7)가 봉지되도록 서키트 테이프(2) 상부 영역에 형성되는 몰드바디(8)를 포함하여 구성된다.5 is a longitudinal cross-sectional view illustrating a chip scale package according to a second embodiment of the present invention, FIG. 6 is a plan view illustrating the circuit tape of FIG. 5, and FIG. 7 is a bottom view of FIG. 6, according to a second embodiment of the present invention. In the chip scale package according to the example, a wire bonding pad 3 is formed on an upper surface thereof, a circuit wiring 4 and a solder land 5 connected to the wire bonding pad 3 are formed on a lower surface thereof, and a window 9 is formed in a central portion thereof. Is formed on the circuit tape 2, the heat sink 10 attached to the window 9 of the circuit tape 2, the semiconductor chip 1 attached to the upper surface of the heat sink 10, and the semiconductor Wire 7 connecting the chip pad of the chip 1 and the wire bonding pad 3 of the circuit tape 2 and the upper region of the circuit tape 2 so that the semiconductor chip 1 and the wire 7 are sealed. It is configured to include a mold body (8) formed in.
이 때, 상기 반도체칩(1)과 히트싱크(10) 사이에는 어드헤시브(6)가 개재되며, 상기 솔더랜드(5)에는 솔더볼(도시는 생략함)이 부착가능하다.At this time, an additive 6 is interposed between the semiconductor chip 1 and the heat sink 10, and solder balls (not shown) may be attached to the solder land 5.
이와 같이 구성된 본 발명의 제2실시예에 따른 칩스케일 패키지 제조 과정을 도 8a 내지 도 8d을 참조하여 설명하면 다음과 같다.The chip scale package manufacturing process according to the second embodiment of the present invention configured as described above will be described with reference to FIGS. 8A to 8D.
먼저, 상면에 와이어본딩패드(3)가 형성되고 저면에는 상기 와이어본딩패드(3)와 연결되는 회로배선(4) 및 솔더랜드(5)가 형성되며 중앙부에 윈도우(9)가 형성된 서키트 테이프(2)를 준비한 상태에서, 상기 서키트 테이프(2)의 윈도우(9) 상에 히트싱크(10)를 부착한다.First, a wire bonding pad 3 is formed on an upper surface, a circuit wiring 4 and a solder land 5 connected to the wire bonding pad 3 are formed on a bottom surface, and a circuit tape having a window 9 formed in a central portion thereof. In a state where 2) is prepared, the heat sink 10 is attached onto the window 9 of the circuit tape 2.
이어, 상기 히트싱크(10) 상면에는 반도체칩(1)을 부착한다.Subsequently, a semiconductor chip 1 is attached to an upper surface of the heat sink 10.
그 다음, 상기 반도체칩(1)의 칩패드와 서키트 테이프(2)의 와이어본딩패드(3)를 와이어(7)로 연결하게 된다.Then, the chip pad of the semiconductor chip 1 and the wire bonding pad 3 of the circuit tape 2 are connected with the wire 7.
이 때, 기존의 일반적인 방식의 와이어 본딩 순서와는 달리, 열응력의 흡수를 돕기 위해 와이어본딩패드(3) 상에 볼본딩을 실시하고, 반도체칩(1)의 칩패드상에 스티치 본딩을 실시하게 됨은 전술한 바와 같다.At this time, unlike the conventional wire bonding procedure, ball bonding is performed on the wire bonding pad 3 to aid in the absorption of thermal stress, and stitch bonding is performed on the chip pad of the semiconductor chip 1. This is as described above.
그리고, 상기 히트싱크(10)는 반도체칩(1)의 그라운드 단자를 접지시키기 위한 그라운드(ground)로서도 역할하게 된다.The heat sink 10 also serves as a ground for grounding the ground terminal of the semiconductor chip 1.
한편, 와이어(7) 본딩 완료후에는, 상기 반도체칩(1)과 와이어(7)가 봉지되도록 히트싱크(10) 및 서키트 테이프(2) 상부 영역을 봉지하여 몰드바디(8)를 형성하게 된다.On the other hand, after the bonding of the wire 7 is completed, the mold body 8 is formed by encapsulating the heat sink 10 and the upper region of the circuit tape 2 so that the semiconductor chip 1 and the wire 7 are sealed. .
상기, 제2실시예에 따른 칩스케일 패키지는 서키트 테이프(2)의 윈도우(9)상에 히트싱크(10)가 부착되어 있어, 도 8a에 나타낸 바와 같이 반도체칩(1)이 히트싱크(10) 상면에 부착되는 점과, 히트싱크(10)가 그라운드 본딩에 사용되는 점에 있어서, 제1실시예에서의 칩스케일 패키지와는 다른 특징이 있다.In the chip scale package according to the second embodiment, the heat sink 10 is attached to the window 9 of the circuit tape 2, and as shown in FIG. ) Is different from the chip scale package in the first embodiment in that it is attached to the upper surface and the heat sink 10 is used for ground bonding.
이상에서와 같이, 본 발명은 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 칩스케일 패키지를 제공하기 위한 것으로서, 값싸고 신뢰성 높은 부자재(附資材)를 이용하여 구조적 측면에서 경박단소하며 방열성능이 뛰어난 신뢰성 높은 칩스케일 패키지를 제공할 수 있게 된다.As described above, the present invention is to provide a new type of chip-scale package that maximizes the advantages of the existing semiconductor package while eliminating its disadvantages, and in terms of structure using inexpensive and reliable subsidiary materials. It is possible to provide a reliable chip scale package that is light in weight and thin and has excellent heat dissipation performance.
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