CN114910690B - Multiplexing trimming structure and method for current high-precision sampling system in charging control chip - Google Patents

Multiplexing trimming structure and method for current high-precision sampling system in charging control chip Download PDF

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CN114910690B
CN114910690B CN202210845254.8A CN202210845254A CN114910690B CN 114910690 B CN114910690 B CN 114910690B CN 202210845254 A CN202210845254 A CN 202210845254A CN 114910690 B CN114910690 B CN 114910690B
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tube
trimming
resistor
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CN114910690A (en
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陈浩
张航鲜
周江云
吴刚
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Chengdu Yichong Wireless Power Technology Co ltd
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Chengdu Yichong Wireless Power Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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    • Y02E60/10—Energy storage using batteries

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Abstract

The invention provides a multiplexing trimming structure and a method for a current high-precision sampling system in a charging control chip, wherein the trimming structure comprises a register, system voltage, a Main power tube Main FET, a sampling tube Sense FET1, a sampling tube Sense FET2, a current sampling circuit and a constant current management circuit; the current sampling circuit comprises a current sampling operational amplifier CSA, a sampling resistor Rsns1, a sampling resistor Rsns2, an NMOS tube Mn1, an NMOS tube Mn2, a PMOS tube Mp1, a PMOS tube Mp2 and a sampling selection circuit; the constant current management circuit comprises an error amplifier EA and a driver; trimming circuits are arranged inside the error amplifier EA and at one end of the sampling resistor Rsns; the trimming circuit is controlled by the trimming code output by the register. The invention can realize high precision in a wider output current range.

Description

Multiplexing trimming structure and method for current high-precision sampling system in charging control chip
Technical Field
The invention relates to the technical field of charging control chips, in particular to a multiplexing trimming structure and a multiplexing trimming method for a current high-precision sampling system in a charging control chip.
Background
Lithium ion batteries are widely applied to various portable devices, and charge control chips related to the lithium ion batteries have great market potential, so the design heat of the charge control chips is higher and higher, wherein the design of high-precision current is one of the difficulties.
The charging current has great influence on the service life of the battery, the charging time can be reduced by the large current, the charging efficiency is ensured, but the problem of reduction of the service life of the battery is also caused, and therefore, the high-precision charging current is the key of the design of the charging control chip. In addition, with the huge market space of consumer electronics, it is important that the charging control chip is compatible with different application scenarios, and the charging control chip needs to output different currents. Based on the above two points, high precision current design with wide output range becomes an urgent demand of the market.
Disclosure of Invention
The invention aims to provide a multiplexing trimming structure and a multiplexing trimming method for a current high-precision sampling system in a charging control chip, so as to realize high precision in a wider output current range.
The invention provides a multiplexing trimming structure of a Current high-precision sampling system in a charging control chip, which comprises a register, a system voltage Vsys, a Main power tube Main FET, a sampling tube Sense FET1, a sampling tube Sense FET2, a Current sampling circuit Current Sense and a constant Current management circuit CCRegulation; the Current sampling circuit Current Sense includes: the current sampling operational amplifier CSA, the sampling resistor Rsns1, the sampling resistor Rsns2, the NMOS tube Mn1, the NMOS tube Mn2, the PMOS tube Mp1, the PMOS tube Mp2 and the sampling selection circuit CSA _ output _ sel; the constant current management circuit CCRegulation comprises an error amplifier EA and a driver; trimming circuits are arranged inside the error amplifier EA and at one end of the sampling resistor Rsns; the trimming circuit is controlled by a trimming code output by the register;
the source electrode of the Main power tube Main FET is connected with a system voltage Vsys; the grid electrode of the Main power tube Main FET is connected with the output end of the driver; the drain electrode of the Main power tube Main FET is grounded through the rechargeable battery, a connection point vbat between the drain electrode and the rechargeable battery is also connected with a first negative input end inn1 of the current sampling operational amplifier CSA, and one end of a sampling resistor Rsns1 and one end of a sampling resistor Rsns2 is connected with the connection point vbat; the other end of the sampling resistor Rsns2 is connected with a second negative input terminal inn2 of the current sampling operational amplifier CSA on one hand, and is connected with the source electrode of the NMOS transistor Mn2 on the other hand; the source electrode of the sampling tube Sense FET1 is connected with the system voltage Vsys; the grid electrode of the sampling tube Sense FET1 is connected with the output end of the driver; the drain electrode of the sampling tube Sense FET1 is connected with the first positive input end inp1 of the current sampling operational amplifier CSA on one hand, and is connected with the drain electrode of the NMOS tube Mn1 on the other hand; the source of the sampling tube Sense FET2 is connected to the system voltage Vsys; the grid electrode of the sampling tube Sense FET2 is connected with the output end of the driver; the drain electrode of the sampling tube Sense FET2 is connected with the other end of the sampling resistor Rsns1 on one hand, and is connected with a second positive input end inp2 of the current sampling operational amplifier CSA on the other hand; the gate of the NMOS transistor Mn1 is connected to the first output end outH of the current sampling operational amplifier CSA, and the source of the NMOS transistor Mn1 is connected to the first active end of the sampling selection circuit CSA _ output _ sel; the grid electrode of the NMOS tube Mn2 is connected with the second output end outL of the current sampling operational amplifier CSA, and the drain electrode of the NMOS tube Mn2 is respectively connected with the grid electrode and the drain electrode of the PMOS tube Mp1 and the grid electrode of the PMOS tube Mp 2; the source electrode of the PMOS tube Mp1 and the source electrode of the PMOS tube Mp2 are connected with a power supply Vcc; the drain electrode of the PMOS pipe Mp2 is connected with the second active end of the sampling selection circuit CSA _ output _ sel; the fixed end of the sampling selection circuit CSA _ output _ sel is grounded through a trimming circuit and a sampling resistor Rsns on one hand, and is connected with the positive input end of an error amplifier EA on the other hand; the negative input end of the error amplifier EA is connected with a reference voltage vref _ dac; the output of the error amplifier EA is connected to the input of the driver.
Further, the error amplifier EA comprises a PMOS transistor M1, a PMOS transistor M2, a resistor R1, a resistor R2 and a comparator U1;
the source electrode of the PMOS tube M1 and the source electrode of the PMOS tube M2 are connected with a power supply; the grid electrode of the PMOS pipe M1 is connected with a reference voltage vref _ dac; the grid electrode of the PMOS pipe M2 is connected with the fixed end of the sampling selection circuit CSA _ output _ sel; the drain of the PMOS tube M1 is grounded through a resistor R1 and a trimming circuit in sequence on one hand, and is connected with the positive input end of a comparator U1 on the other hand; the drain electrode of the PMOS tube M2 is grounded through a resistor R2 and a trimming circuit on the one hand, and is connected with the negative input end of a comparator U1 on the other hand; the resistance of the resistor R1 is equal to the resistance of the resistor R2.
Further, the trimming circuit comprises a switch sw1, a switch sw2 and a switch sw3 which are connected in series, and a first resistor, a second resistor and a third resistor which are connected in series; the first resistance value is R, the second resistance value is 2R, and the third resistance value is 4R; a connection point between the switch sw1 and the switch sw2 is connected with a connection point between the first resistor and the second resistor; the connection point between the switch sw2 and the switch sw3 is connected to the connection point between the second resistor and the third resistor.
The invention also provides a multiplexing trimming method for the current high-precision sampling system in the charging control chip, which is realized by adopting the multiplexing trimming circuit for the current high-precision sampling system in the charging control chip;
the trimming method comprises the following steps:
when vbat is greater than the threshold voltage, connecting a fixed end of the sampling selection circuit CSA _ output _ sel with a first movable end; the Current sampling circuit Current Sense clamps the drain voltage of a sampling tube Sense FET1 to the drain voltage of a Main power tube Main FET, namely the voltage of a first positive input end inp1 of the Current sampling operational amplifier CSA is equal to the voltage of a first negative input end inn1 of the Current sampling operational amplifier CSA; then the current isns1 of the sampling tube Sense FET1 flows to a sampling resistor Rsns through an NMOS tube Mn1 to generate a voltage CSA _ OUT, the voltage CSA _ OUT is input into an error amplifier EA, the ratio of the current isns1 of the sampling tube Sense FET1 to the current ibat of a Main power tube Main FET is 1: K, and current sampling is completed; next, an error amplifier EA in the constant current management circuit CCRegulation samples the voltage CSA _ OUT and the reference voltage vref _ dac, and then adjusts the gate voltages of the sampling tube Sense FET1 and the Main power tube Main FET through a driver until the CSA _ OUT = vref _ dac and the current ibat of the Main power tube Main FET reaches the set sampling precision requirement; in the process, the register outputs a trimming code to control the trimming circuit to eliminate the current precision influence factor;
connecting a fixed terminal of sampling selection circuit CSA _ output _ sel to a second active terminal when vbat is less than a threshold voltage; the Current sampling circuit Current Sense clamps the voltage of the sampling resistor Rsns1 to the voltage of the sampling resistor Rsns2, namely the voltage of the second positive input terminal inp2 of the Current sampling operational amplifier CSA is equal to the voltage of the second negative input terminal inn2 of the Current sampling operational amplifier CSA; setting the resistance values of a sampling resistor Rsns1 and a sampling resistor Rsns2 to be equal, so that the current isns2 of a sampling tube Sense FET2 is equal to the current flowing through a PMOS tube Mp1 and an NMOS tube Mn2, then the current of the PMOS tube Mp2 mirror PMOS tube Mp1 flows through the sampling resistor Rsns to generate a voltage CSA _ OUT, the voltage CSA _ OUT is input into an error amplifier EA, the ratio of the current isns2 of the sampling tube Sense FET2 to the current ibat 86of a Main power tube Main FET is 1: K, and the current sampling is completed; next, an error amplifier EA in the constant current management circuit CCRegulation samples the voltage CSA _ OUT and the reference voltage vref _ dac, and then adjusts the gate voltages of the sampling tube Sense FET2 and the Main power tube Main FET through a driver until the CSA _ OUT = vref _ dac and the current ibat of the Main power tube Main FET reaches the set sampling precision requirement; in the process, the register outputs the trimming code to control the trimming circuit to eliminate the current precision influence factor.
Further, the method for eliminating the current precision influence factor by the register outputting the trimming code to control the trimming circuit comprises the following steps:
the use of 0 in the register indicates the turn-off of the switch sw1, the switch sw2 and the switch sw3 in the trimming circuit, and the use of 1 indicates the turn-on of the switch sw1, the switch sw2 and the switch sw3 in the trimming circuit;
the register outputs trimming codes with the range of 000- >111 to a trimming circuit connected with the sampling resistor Rsns, so that the resistance change of the sampling resistor Rsns within the range of 0-7R is realized, and the resistance error delta R introduced in the manufacturing of the charging control chip is eliminated;
the register realizes the resistance change of the resistor R1 and the resistor R2 in the range of 0-7R by outputting trimming codes with the range of 000- >111 to two trimming circuits in the error amplifier EA, so that a fixed differential pressure is generated between the reference voltage vref _ dac and the voltage CSA _ OUT to eliminate the voltage mismatches vos1 and vos 2; wherein vos1 represents the voltage mismatch vos1a between the sampling tube Sense FET1 and the Main power tube Main FET or the voltage mismatch vos1b between the sampling tube Sense FET2 and the Main power tube Main FET; vos2 denotes the input voltage mismatch of the error amplifier EA; the voltage mismatch refers to a difference in threshold voltage between devices.
Further, the trimming code in the register is set according to the working area of the current ibat.
Further, the threshold voltage is 2V.
Further, the operating region of the current ibat is as follows:
when vbat is greater than the threshold voltage, the operation of the current ibat is divided into:
the first working area is 1 mA-8 mA
The second working area is 8 mA-64 mA;
when vbat is less than the threshold voltage, the operation of the current ibat is divided into:
the first working area is 1 mA-8 mA
The second working area is 8 mA-64 mA;
the third working area is 64 mA-500 mA.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. according to the invention, the influence of the voltage mismatch Vos1, the voltage mismatch Vos2 and the resistance error delta R on the accuracy of the current ibat is eliminated through the trimming circuit and the corresponding trimming code, and high accuracy can be realized in a wider output current range.
2. The invention multiplexes the sampling resistor Rsns and the error amplifier EA, and can greatly reduce the area of the chip.
3. The invention has wide application range.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a structural diagram of a multiplexing trimming structure of a current high-precision sampling system in a charging control chip in an embodiment of the present invention.
Fig. 2 is a graph showing the variation of the output current ibat with the reference voltage vref _ dac according to the embodiment of the present invention.
FIG. 3 is a schematic diagram of the register outputting the trim code according to the embodiment of the present invention.
Fig. 4 is a structural diagram of a trimming circuit according to an embodiment of the invention.
Fig. 5 is a block diagram of an error amplifier in an embodiment of the invention.
FIG. 6 is a comparison chart of current precision before and after trimming according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
As shown in fig. 1, the present embodiment provides a multiplexing trimming structure of a Current high-precision sampling system in a charging control chip, which includes a register, a system voltage Vsys, a Main power transistor Main FET, a sampling tube Sense FET1, a sampling tube Sense FET2, a Current sampling circuit Current Sense, and a constant Current management circuit CCRegulation; the Current sampling circuit Current Sense includes: the current sampling operational amplifier CSA, the sampling resistor Rsns1, the sampling resistor Rsns2, the NMOS tube Mn1, the NMOS tube Mn2, the PMOS tube Mp1, the PMOS tube Mp2 and the sampling selection circuit CSA _ output _ sel; the constant current management circuit CCRegulation comprises an error amplifier EA and a driver; trimming circuits are arranged inside the error amplifier EA and at one end of the sampling resistor Rsns; the trimming circuit is controlled by the trimming code output by the register;
the source electrode of the Main power tube Main FET is connected with a system voltage Vsys; the grid electrode of the Main power tube Main FET is connected with the output end of the driver; the drain electrode of the Main power tube Main FET is grounded through the rechargeable battery, a connection point vbat between the drain electrode and the rechargeable battery is also connected with a first negative input end inn1 of the current sampling operational amplifier CSA, and one end of a sampling resistor Rsns1 and one end of a sampling resistor Rsns2 is connected with the connection point vbat; the other end of the sampling resistor Rsns2 is connected with a second negative input terminal inn2 of the current sampling operational amplifier CSA on one hand, and is connected with the source electrode of the NMOS transistor Mn2 on the other hand; the source electrode of the sampling tube Sense FET1 is connected with the system voltage Vsys; the grid electrode of the sampling tube Sense FET1 is connected with the output end of the driver; the drain electrode of the sampling tube Sense FET1 is connected with the first positive input end inp1 of the current sampling operational amplifier CSA on one hand, and is connected with the drain electrode of the NMOS tube Mn1 on the other hand; the source of the sampling tube Sense FET2 is connected to the system voltage Vsys; the grid electrode of the sampling tube Sense FET2 is connected with the output end of the driver; the drain electrode of the sampling tube Sense FET2 is connected with the other end of the sampling resistor Rsns1 on one hand, and is connected with a second positive input end inp2 of the current sampling operational amplifier CSA on the other hand; the gate of the NMOS transistor Mn1 is connected to the first output end outH of the current sampling operational amplifier CSA, and the source of the NMOS transistor Mn1 is connected to the first active end of the sampling selection circuit CSA _ output _ sel; the grid electrode of the NMOS tube Mn2 is connected with the second output end outL of the current sampling operational amplifier CSA, and the drain electrode of the NMOS tube Mn2 is respectively connected with the grid electrode and the drain electrode of the PMOS tube Mp1 and the grid electrode of the PMOS tube Mp 2; the source electrode of the PMOS tube Mp1 and the source electrode of the PMOS tube Mp2 are connected with a power supply Vcc; the drain electrode of the PMOS pipe Mp2 is connected with the second active end of the sampling selection circuit CSA _ output _ sel; the fixed end of the sampling selection circuit CSA _ output _ sel is grounded through a trimming circuit and a sampling resistor Rsns on one hand, and is connected with the positive input end of an error amplifier EA on the other hand; the negative input end of the error amplifier EA is connected with a reference voltage vref _ dac; the output of the error amplifier EA is connected to the input of the driver.
Wherein:
when the fixed ends of the sampling tube Sense FET1, the current sampling operational amplifier CSA, the NMOS tube Mn1 and the sampling selection circuit CSA _ output _ sel are connected with the first movable end, a sampling circuit when vbat is high is formed;
when the fixed ends of the sampling tube Sense FET2, the sampling resistor Rsns1, the sampling resistor Rsns2, the current sampling operational amplifier CSA, the NMOS tube Mn2, the PMOS tube Mp1, the PMOS tube Mp2 and the sampling selection circuit CSA _ output _ sel are connected with the second movable end, a sampling circuit when vbat is low is formed.
Errors in the overall system include:
(1) the resistance error Δ R introduced in the manufacturing of the charge control chip, that is, the sampling resistance Rsns has a resistance value change of Δ R.
(2) The voltage adaptation between the sampling tube and the Main power tube Vos1 (i.e., the voltage mismatch between the sampling tube Sense FET1 and the Main power tube Main FET Vos1a or the voltage mismatch between the sampling tube Sense FET2 and the Main power tube Main FET Vos1 b). Because of the uncertainty of each process in the integrated circuit fabrication process, there is a finite mismatch (i.e., voltage mismatch) for nominally identical devices, and thus the voltage mismatch in the present invention refers to the difference in threshold voltage between devices to indicate such mismatch.
(3) The input voltage mismatch Vos2 of the error amplifier EA.
Thus, the current ibat is represented as:
ibat=K*(1+2Vos1/(Vgs-Vth))(vref_dac+Vos2)*/(Rsns+ΔR）
k represents a sampling ratio, and K =16,128 or 1024 may be set for the working region of the current ibat, which corresponds to three working regions of the current ibat, respectively; vgs is the gate-source voltage of the main power transistor MainFET, and Vth is the threshold voltage of the main power transistor MainFET.
The influence of resistance error Δ R, voltage mismatch Vos1 and voltage mismatch Vos2 on current accuracy is analyzed by taking a group of fixed sampling mirror proportions as an example. Fig. 2 shows the variation curve of the output current ibat with the reference voltage vref _ dac, which shows the four conditions of the voltage mismatch Vos1, the voltage mismatch Vos2, and the resistance error Δ R acting alone and in an ideal case. Wherein ideal condition ideal is a primary curve passing through the origin, and the output current precision corresponding to all reference voltages vref _ dac reaches 100%; the resistance error Δ R affects only the gain of the sampling accuracy, and its effect on the accuracy of the output current corresponding to the reference voltage vref _ dac is consistent and does not change with the change of the reference voltage vref _ dac; the voltage mismatch Vos2 is a fixed offset, the voltage mismatch Vos2 significantly affects the current accuracy when the reference voltage vref _ dac is small, and the effect of the voltage mismatch Vos2 decreases as the reference voltage vref _ dac increases. The voltage mismatch Vos1 current mirror offset is different from the resistance error Δ R and the voltage mismatch Vos2, which is neither a gain affecting the sampling accuracy nor a fixed offset, but similar to the voltage mismatch Vos2, the current accuracy is poor when the reference voltage vref _ dac is small and the current accuracy is good when the reference voltage vref _ dac is large.
Therefore, as shown in fig. 3, in the present invention, a trimming circuit is provided at one end of the sampling resistor Rsns in the error amplifier EA, and the register outputs a corresponding trimming code to eliminate the influence of the resistance error Δ R, the voltage mismatch Vos1, and the voltage mismatch Vos2 on the current accuracy. Therefore, the trimming method based on the multiplexing trimming structure of the current high-precision sampling system in the charging control chip comprises the following steps:
when vbat is greater than the threshold voltage (the threshold voltage is set to 2V in this embodiment), the fixed terminal of the sampling selection circuit CSA _ output _ sel is connected to the first active terminal; the Current sampling circuit Current Sense clamps the drain voltage of a sampling tube Sense FET1 to the drain voltage of a Main power tube Main FET, namely the voltage of a first positive input end inp1 of the Current sampling operational amplifier CSA is equal to the voltage of a first negative input end inn1 of the Current sampling operational amplifier CSA; then the current isns1 of the sampling tube Sense FET1 flows to a sampling resistor Rsns through an NMOS tube Mn1 to generate a voltage CSA _ OUT, the voltage CSA _ OUT is input into an error amplifier EA, the ratio of the current isns1 of the sampling tube Sense FET1 to the current ibat of a Main power tube Main FET is 1: K, and current sampling is completed; next, an error amplifier EA in the constant current management circuit CCRegulation samples the voltage CSA _ OUT and the reference voltage vref _ dac, and then adjusts the gate voltages of the sampling tube Sense FET1 and the Main power tube Main FET through a driver until the CSA _ OUT = vref _ dac and the current ibat of the Main power tube Main FET reaches the set sampling precision requirement; in the process, the register outputs a trimming code to control the trimming circuit to eliminate the current precision influence factor;
when vbat is less than the threshold voltage (the threshold voltage is set to 2V in this embodiment), the fixed terminal of the sampling selection circuit CSA _ output _ sel is connected to the second active terminal; the Current sampling circuit Current Sense clamps the voltage of the sampling resistor Rsns1 to the voltage of the sampling resistor Rsns2, namely the voltage of the second positive input terminal inp2 of the Current sampling operational amplifier CSA is equal to the voltage of the second negative input terminal inn2 of the Current sampling operational amplifier CSA; setting the resistance values of a sampling resistor Rsns1 and a sampling resistor Rsns2 to be equal, so that the current isns2 of a sampling tube Sense FET2 is equal to the current flowing through a PMOS tube Mp1 and an NMOS tube Mn2, then the current of the PMOS tube Mp2 mirror PMOS tube Mp1 flows through the sampling resistor Rsns to generate a voltage CSA _ OUT, the voltage CSA _ OUT is input into an error amplifier EA, the ratio of the current isns2 of the sampling tube Sense FET2 to the current ibat 86of a Main power tube Main FET is 1: K, and the current sampling is completed; next, an error amplifier EA in the constant current management circuit CCRegulation samples the voltage CSA _ OUT and the reference voltage vref _ dac, and then adjusts the gate voltages of the sampling tube Sense FET2 and the Main power tube Main FET through a driver until the CSA _ OUT = vref _ dac and the current ibat of the Main power tube Main FET reaches the set sampling precision requirement; in the process, the register outputs the trimming code to control the trimming circuit to eliminate the current precision influence factor.
Further, as shown in fig. 4, the trimming circuit includes a switch sw1, a switch sw2 and a switch sw3 connected in series, and a first resistor, a second resistor and a third resistor connected in series; the first resistance value is R, the second resistance value is 2R, and the third resistance value is 4R; a connection point between the switch sw1 and the switch sw2 is connected with a connection point between the first resistor and the second resistor; the connection point between the switch sw2 and the switch sw3 is connected to the connection point between the second resistor and the third resistor.
Further, as shown in fig. 5, the error amplifier EA includes a PMOS transistor M1, a PMOS transistor M2, a resistor R1, a resistor R2, and a comparator U1;
the source electrode of the PMOS tube M1 and the source electrode of the PMOS tube M2 are connected with a power supply; the grid electrode of the PMOS pipe M1 is connected with a reference voltage vref _ dac; the grid electrode of the PMOS pipe M2 is connected with the fixed end of the sampling selection circuit CSA _ output _ sel; the drain of the PMOS tube M1 is grounded through a resistor R1 and a trimming circuit in sequence on one hand, and is connected with the positive input end of a comparator U1 on the other hand; the drain electrode of the PMOS tube M2 is grounded through a resistor R2 and a trimming circuit on the one hand, and is connected with the negative input end of a comparator U1 on the other hand; the resistance of the resistor R1 is equal to the resistance of the resistor R2.
As shown in fig. 6, the method for eliminating the current precision influence factor by the register outputting the trimming code to control the trimming circuit includes:
the first step is as follows: in register:
0 is used for indicating the turn-off of the switch sw1, the switch sw2 and the switch sw3 in the trimming circuit;
the opening of the switches sw1, sw2 and sw3 in the trimming circuit is denoted by 1;
the second step is that: the register outputs trimming codes with the range of 000- >111 to a trimming circuit connected with the sampling resistor Rsns, so that the resistance change of the sampling resistor Rsns within the range of 0-7R is realized, and the resistance error delta R introduced in the manufacturing of the charging control chip is eliminated;
the third step: the register outputs trimming codes with the range of 000- >111 to two trimming circuits in the error amplifier EA, so that resistance change of the resistor R1 and the resistor R2 within the range of 0-7R is realized, and a fixed differential pressure is generated between the reference voltage vref _ dac and the voltage CSA _ OUT to eliminate voltage mismatches vos1 and vos 2; wherein vos1 represents the voltage mismatch vos1a between the sampling tube Sense FET1 and the Main power tube Main FET or the voltage mismatch vos1b between the sampling tube Sense FET2 and the Main power tube Main FET; vos2 denotes the input voltage mismatch of the error amplifier EA.
Generally, the current ibat has a plurality of working areas, and the trimming code in the register may be set according to the working area of the current ibat, thereby realizing that different trimming codes are selected according to different currents ibat. The working area of the current ibat is as follows:
when vbat is greater than the threshold voltage, the operation of the current ibat is divided into:
the first working area is 1 mA-8 mA
The second working area is 8 mA-64 mA;
when vbat is less than the threshold voltage, the operation of the current ibat is divided into:
the first working area is 1 mA-8 mA
The second working area is 8 mA-64 mA;
the third working area is 64 mA-500 mA.
From the above, the current ibat has 5 working areas, and the voltage mismatch Vos1, the voltage mismatch Vos2 and the resistance error Δ R in each working area have different effects on the accuracy of the current ibat. Based on this, the register of this embodiment stores the trimming codes corresponding to these five working areas, and selects the corresponding trimming codes to output to the trimming circuit under different working areas, so as to ensure the current ibat precision under any charging stage and different charging settings, and the sampling resistor Rsns and the error amplifier EA are multiplexed in this way, thereby greatly reducing the area of the chip. The scheme can be popularized to a charging system with a larger current range ibat, only more working areas are required to be allocated by the system, and corresponding trimming codes are added and stored in the register for calling.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A multiplexing trimming structure of a Current high-precision sampling system in a charging control chip is characterized by comprising a register, a system voltage Vsys, a Main power tube Main FET, a sampling tube Sense FET1, a sampling tube Sense FET2, a Current sampling circuit Current Sense and a constant Current management circuit CCRegulation; the Current sampling circuit Current Sense includes: the current sampling operational amplifier CSA, the sampling resistor Rsns1, the sampling resistor Rsns2, the NMOS tube Mn1, the NMOS tube Mn2, the PMOS tube Mp1, the PMOS tube Mp2 and the sampling selection circuit CSA _ output _ sel; the constant current management circuit CCRegulation comprises an error amplifier EA and a driver; trimming circuits are arranged inside the error amplifier EA and at one end of the sampling resistor Rsns; the trimming circuit is controlled by the trimming code output by the register;
the source electrode of the Main power tube Main FET is connected with a system voltage Vsys; the grid electrode of the Main power tube Main FET is connected with the output end of the driver; the drain electrode of the Main power tube Main FET is grounded through the rechargeable battery, a connection point vbat between the drain electrode and the rechargeable battery is also connected with a first negative input end inn1 of the current sampling operational amplifier CSA, and one end of a sampling resistor Rsns1 and one end of a sampling resistor Rsns2 is connected with the connection point vbat; the other end of the sampling resistor Rsns2 is connected with a second negative input terminal inn2 of the current sampling operational amplifier CSA on one hand, and is connected with the source electrode of the NMOS transistor Mn2 on the other hand; the source electrode of the sampling tube Sense FET1 is connected with the system voltage Vsys; the grid electrode of the sampling tube Sense FET1 is connected with the output end of the driver; the drain electrode of the sampling tube Sense FET1 is connected with the first positive input end inp1 of the current sampling operational amplifier CSA on one hand, and is connected with the drain electrode of the NMOS tube Mn1 on the other hand; the source of the sampling tube Sense FET2 is connected to the system voltage Vsys; the grid electrode of the sampling tube Sense FET2 is connected with the output end of the driver; the drain electrode of the sampling tube Sense FET2 is connected with the other end of the sampling resistor Rsns1 on one hand, and is connected with a second positive input end inp2 of the current sampling operational amplifier CSA on the other hand; the gate of the NMOS transistor Mn1 is connected to the first output end outH of the current sampling operational amplifier CSA, and the source of the NMOS transistor Mn1 is connected to the first active end of the sampling selection circuit CSA _ output _ sel; the grid electrode of the NMOS tube Mn2 is connected with the second output end outL of the current sampling operational amplifier CSA, and the drain electrode of the NMOS tube Mn2 is respectively connected with the grid electrode and the drain electrode of the PMOS tube Mp1 and the grid electrode of the PMOS tube Mp 2; the source electrode of the PMOS tube Mp1 and the source electrode of the PMOS tube Mp2 are connected with a power supply Vcc; the drain electrode of the PMOS pipe Mp2 is connected with the second active end of the sampling selection circuit CSA _ output _ sel; the fixed end of the sampling selection circuit CSA _ output _ sel is grounded through a trimming circuit and a sampling resistor Rsns on one hand, and is connected with the positive input end of an error amplifier EA on the other hand; the negative input end of the error amplifier EA is connected with a reference voltage vref _ dac; the output of the error amplifier EA is connected to the input of the driver.
2. The multiplexing trimming structure of the current high-precision sampling system in the charging control chip of claim 1, wherein the error amplifier EA comprises a PMOS transistor M1, a PMOS transistor M2, a resistor R1, a resistor R2 and a comparator U1;
the source electrode of the PMOS tube M1 and the source electrode of the PMOS tube M2 are connected with a power supply; the grid electrode of the PMOS pipe M1 is connected with a reference voltage vref _ dac; the grid electrode of the PMOS pipe M2 is connected with the fixed end of the sampling selection circuit CSA _ output _ sel; the drain electrode of the PMOS tube M1 is grounded through a resistor R1 and a trimming circuit in sequence on one hand, and is connected with the positive input end of a comparator U1 on the other hand; the drain electrode of the PMOS tube M2 is sequentially grounded through a resistor R2 and a trimming circuit on the one hand, and is connected with the negative input end of a comparator U1 on the other hand; the resistance of the resistor R1 is equal to the resistance of the resistor R2.
3. The multiplexing trimming structure of the current high-precision sampling system in the charge control chip according to claim 2, wherein the trimming circuit comprises a switch sw1, a switch sw2 and a switch sw3 which are connected in series, and a first resistor, a second resistor and a third resistor which are connected in series; the first resistance value is R, the second resistance value is 2R, and the third resistance value is 4R; a connection point between the switch sw1 and the switch sw2 is connected with a connection point between the first resistor and the second resistor; the connection point between the switch sw2 and the switch sw3 is connected to the connection point between the second resistor and the third resistor.
4. A multiplexing trimming method for a current high-precision sampling system in a charging control chip is characterized in that the trimming method is realized by adopting the multiplexing trimming structure for the current high-precision sampling system in the charging control chip according to any one of claims 1 to 3;
the trimming method comprises the following steps:
connecting a fixed terminal of sampling selection circuit CSA _ output _ sel to a first active terminal when vbat is greater than a threshold voltage; the Current sampling circuit Current Sense clamps the drain voltage of a sampling tube Sense FET1 to the drain voltage of a Main power tube Main FET, namely the voltage of a first positive input end inp1 of the Current sampling operational amplifier CSA is equal to the voltage of a first negative input end inn1 of the Current sampling operational amplifier CSA; then the current isns1 of the sampling tube Sense FET1 flows to a sampling resistor Rsns through an NMOS tube Mn1 to generate a voltage CSA _ OUT, the voltage CSA _ OUT is input into an error amplifier EA, at the moment, the ratio of the current isns1 of the sampling tube Sense FET1 to the current ibat of a Main power tube Main FET is 1: K, K represents the sampling proportion, and the current sampling is completed; next, an error amplifier EA in the constant current management circuit CCRegulation samples the voltage CSA _ OUT and the reference voltage vref _ dac, and then adjusts the gate voltages of the sampling tube Sense FET1 and the Main power tube Main FET through a driver until the CSA _ OUT = vref _ dac and the current ibat of the Main power tube Main FET reaches the set sampling precision requirement; in the process, the register outputs the trimming code to control the trimming circuit to eliminate the current precision influence factor;
connecting a fixed terminal of sampling selection circuit CSA _ output _ sel to a second active terminal when vbat is less than a threshold voltage; the Current sampling circuit Current Sense clamps the voltage of the sampling resistor Rsns1 to the voltage of the sampling resistor Rsns2, namely the voltage of the second positive input terminal inp2 of the Current sampling operational amplifier CSA is equal to the voltage of the second negative input terminal inn2 of the Current sampling operational amplifier CSA; setting the resistance values of a sampling resistor Rsns1 and a sampling resistor Rsns2 to be equal, so that the current isns2 of a sampling tube Sense FET2 is equal to the current flowing through a PMOS tube Mp1 and an NMOS tube Mn2, then the current of the PMOS tube Mp2 mirror PMOS tube Mp1 flows through the sampling resistor Rsns to generate a voltage CSA _ OUT, the voltage CSA _ OUT is input into an error amplifier EA, the ratio of the current isns2 of the sampling tube Sense FET2 to the current ibat 86of a Main power tube Main FET is 1: K, and the current sampling is completed; next, an error amplifier EA in the constant current management circuit CCRegulation samples the voltage CSA _ OUT and the reference voltage vref _ dac, and then adjusts the gate voltages of the sampling tube Sense FET2 and the Main power tube Main FET through a driver until the CSA _ OUT = vref _ dac and the current ibat of the Main power tube Main FET reaches the set sampling precision requirement; in the process, the register outputs the trimming code to control the trimming circuit to eliminate the current precision influence factor.
5. The multiplexing trimming method for the current high-precision sampling system in the charging control chip according to claim 4, wherein the method for the register to output the trimming code to control the trimming circuit to eliminate the current precision influencing factors comprises the following steps:
the use of 0 in the register indicates the turn-off of the switch sw1, the switch sw2 and the switch sw3 in the trimming circuit, and the use of 1 indicates the turn-on of the switch sw1, the switch sw2 and the switch sw3 in the trimming circuit;
the register outputs trimming codes with the range of 000- >111 to a trimming circuit connected with the sampling resistor Rsns, so that the resistance change of the sampling resistor Rsns within the range of 0-7R is realized, and the resistance error delta R introduced in the manufacturing of the charging control chip is eliminated;
the register realizes the resistance change of the resistor R1 and the resistor R2 in the range of 0-7R by outputting trimming codes with the range of 000- >111 to two trimming circuits in the error amplifier EA, so that a fixed differential pressure is generated between the reference voltage vref _ dac and the voltage CSA _ OUT to eliminate the voltage mismatches vos1 and vos 2; wherein vos1 represents the voltage mismatch vos1a between the sampling tube Sense FET1 and the Main power tube Main FET or the voltage mismatch vos1b between the sampling tube Sense FET2 and the Main power tube Main FET; vos2 denotes the input voltage mismatch of the error amplifier EA; the voltage mismatch refers to a difference in threshold voltage between devices.
6. The multiplexing trimming method for the current high-precision sampling system in the charging control chip according to claim 5, wherein the trimming code in the register is set according to the working area of the current ibat.
7. The method for multiplexing and trimming current in a charging control chip with high precision sampling system according to claim 6, wherein the threshold voltage is 2V.
8. The multiplexing method for trimming current high-precision sampling system in the charging control chip according to claim 7, wherein the working area of the current ibat is as follows:
when vbat is greater than the threshold voltage, the operation of the current ibat is divided into:
the first working area is 1 mA-8 mA
The second working area is 8 mA-64 mA;
when vbat is less than the threshold voltage, the operating region for current ibat is:
the first working area is 1 mA-8 mA
The second working area is 8 mA-64 mA;
the third working area is 64 mA-500 mA.
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