CN111398656A - High-precision battery voltage sampling circuit - Google Patents

High-precision battery voltage sampling circuit Download PDF

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Publication number
CN111398656A
CN111398656A CN202010181836.1A CN202010181836A CN111398656A CN 111398656 A CN111398656 A CN 111398656A CN 202010181836 A CN202010181836 A CN 202010181836A CN 111398656 A CN111398656 A CN 111398656A
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China
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tube
pmos tube
pmos
drain
circuit
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郭仲杰
李青
陈浩
何帅
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Xian University of Technology
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Xian University of Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/382—Arrangements for monitoring battery or accumulator variables, e.g. SoC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control

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  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a high-precision battery voltage sampling circuit, which comprises a voltage conversion circuit, wherein the voltage conversion circuit is composed of two amplifiers with the same structure, namely an operational amplifier OP1 and an operational amplifier OP2, the input end of the operational amplifier OP2 is Vn +, a dynamic clamping circuit B provides a power ground of the operational amplifier OP2, the input end of the operational amplifier OP1 is Vn-, a dynamic clamping circuit A provides a power ground of the operational amplifier OP1, and the dynamic clamping circuit A and the dynamic clamping circuit B have the same structure; the voltage conversion circuit is further connected with the negative feedback control circuit, the negative feedback control circuit is further connected with the bootstrap circuit, the precision and the stability of the voltage conversion circuit are improved through the negative feedback circuit, the voltage higher than a power supply is provided through the bootstrap circuit, and higher sampling precision and system stability are achieved. The invention solves the problem of low sampling precision of the battery voltage sampling circuit in the prior art.

Description

High-precision battery voltage sampling circuit
Technical Field
The invention belongs to the technical field of sampling circuits, and particularly relates to a high-precision battery voltage sampling circuit.
Background
The sampling accuracy of the battery voltage reflects the sampling error for the actual battery voltage. The voltage of a plurality of series battery packs can reach dozens of volts, and direct sampling is difficult, so that high voltage needs to be converted into low voltage relative to the ground, and errors are generated in the conversion process from the high voltage to the low voltage, so that the sampling precision is reduced. And the smaller the error generated in the sampling process, the higher the sampling precision.
The traditional battery voltage sampling circuit adopts a resistance voltage division network to realize the conversion from high voltage to low voltage, however, in the voltage sampling process, a switch tube of a gating battery has an on-resistance to generate certain voltage drop, so that the acquisition precision is influenced. In addition, the battery voltage is a dynamic analog quantity, and the sampling precision is also related to the response speed of the circuit. The existing technology often adopts the following two ways to improve the sampling precision:
in the method 1, the battery voltage is connected to the unit gain buffer and then transmitted to the resistance voltage division network, so that the voltage drop generated by direct transmission of the switching tube is reduced. However, the input voltage of the operational amplifier in the buffer structure varies with the voltage of the battery, and if a distributed structure is adopted, that is, each battery has a corresponding operational amplifier, the area of the chip is too large for a plurality of series-connected battery packs, and the operational amplifier needs a high-voltage tube for processing high voltage, and the comprehensive performance of the high-voltage tube is inferior to that of a common low-voltage tube, so that the performance of the chip is reduced.
In the method 2, by adding negative feedback control, the output voltage of the voltage conversion circuit or the battery voltage with a certain proportionality coefficient is used as the input of a negative feedback control structure, and the negative feedback control structure is as follows: the unit gain buffer composed of the operational amplifier and the common source amplifier generates current through a resistor, and the current is fed back to the voltage conversion circuit through the current mirror, so that a negative feedback mechanism is formed. However, when the highest voltage in the circuit is VCC1 and is provided by the highest voltage of the series battery pack, when the highest battery is selected for sampling, the source and drain voltages of the current mirror in the negative feedback structure are both VCC1, and the current mirror cannot normally operate, so that when the highest battery is read, the negative feedback control structure cannot normally operate, and the sampling precision is obviously reduced compared with the other batteries.
Disclosure of Invention
The invention aims to provide a high-precision battery voltage sampling circuit, which solves the problem of low sampling precision of a battery voltage sampling circuit in the prior art.
The technical scheme adopted by the invention is that the high-precision battery voltage sampling circuit comprises a voltage conversion circuit, wherein the voltage conversion circuit is composed of two amplifiers with the same structure, namely an operational amplifier OP1 and an operational amplifier OP2, the input end of the operational amplifier OP2 is Vn +, a dynamic clamping circuit B provides a power ground for the operational amplifier OP2, and the dynamic clamping circuit B reduces the voltage of Vn + by 2VGSAs the ground of the operational amplifier OP2, the voltage is raised by 5V through the PMOS connected by 5 series diodesGSAs the power supply of the operational amplifier OP2, the power supply ground voltage difference of the operational amplifier OP2 is always 5VGSAnd the power ground voltage changes along with the input voltage, the input end of the operational amplifier OP1 is Vn-, the dynamic clamp circuit A provides the power ground of the operational amplifier OP1, and the dynamic clamp circuit A and the dynamic clamp circuit B have the same structure;
the voltage conversion circuit is further connected with the negative feedback control circuit, the negative feedback control circuit is further connected with the bootstrap circuit, the precision and the stability of the voltage conversion circuit are improved through the closed-loop negative feedback circuit, the voltage higher than a power supply is provided through the bootstrap circuit, the working range of the negative feedback circuit is widened, and the higher sampling precision and the system stability are achieved.
The present invention is also characterized in that,
the voltage conversion circuit has the specific structure that: the operational amplifier OP1 and OP2 with the same structure are included, a PMOS tube M1 and a PMOS tube M2 are used as input differential pair transistors in the operational amplifier OP2, the grid electrode of the PMOS tube M2 is connected to an input end Vn +, concretely, the source electrode of the PMOS tube M1 is connected to the source electrode of the PMOS tube M2 and also connected to the drain electrode of the PMOS tube M6, the source electrode of the PMOS tube M6 is connected to the dynamic clamp circuit B, the drain electrode of the PMOS tube M1 is connected to the drain electrode of the NMOS tube M3, the source electrode of the NMOS tube M3 is connected to the dynamic clamp circuit B, the grid electrode of the NMOS tube M3 is connected to the grid electrode of the NMOS tube M4, meanwhile, the grid electrode of the NMOS tube M3 is also connected to the drain electrode of the NMOS tube M3, the source electrode of the NMOS tube M4 is connected to the dynamic clamp circuit B, the drain electrode of the NMOS tube M4 is connected to the drain electrode of the PMOS tube M2, the drain electrode of the PMOS tube M2 is connected to the drain electrode of the PMOS tube M1, and then connected to the dynamic clamp circuit 7, the drain electrode of the PMOS tube M7 is also connected with the drain electrode of an NMOS tube M5, the source electrode of the NMOS tube M5 is connected with the dynamic clamping circuit B, and the grid electrode of the NMOS tube M5 is connected with the drain electrode of the PMOS tube M2;
in the operational amplifier OP1, a PMOS transistor M9 and a PMOS transistor M10 are used as input differential pair transistors, a gate of a PMOS transistor M10 is connected to an input terminal Vn +, specifically, a source of a PMOS transistor M9 is connected to a source of a PMOS transistor M10 and simultaneously connected to a drain of a PMOS transistor M15, a source of a PMOS transistor M15 is connected to the dynamic clamp circuit a, a drain of a PMOS transistor M9 is connected to a drain of an NMOS transistor M11, a source of an NMOS transistor M11 is connected to the dynamic clamp circuit a, a gate of an NMOS transistor M11 is connected to a gate of an NMOS transistor M12, a gate of an NMOS transistor M11 is also connected to a drain of an NMOS transistor M11, a source of an NMOS transistor M12 is connected to the dynamic clamp circuit a, a drain of an NMOS transistor M12 is connected to a drain of a PMOS transistor M10, a drain of a PMOS transistor M10 is also connected to a drain of a resistor Rm2 and a drain of a capacitor M2 in turn, a source of a PMOS transistor M14 is connected to a drain of an NMOS transistor M14 and a drain of an NMOS transistor M14, the source electrode of the NMOS tube M13 is connected with the dynamic clamping circuit A, and the grid electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M10;
the drain of the NMOS tube M13 is also connected with the gate of the PMOS tube M16, the drain of the PMOS tube M16 is connected to the ground through a resistor R2, the source of the PMOS tube M16 is connected with the source of the NMOS tube M8 through a resistor R1, the source of the NMOS tube M8 is also connected with the gate of the PMOS tube M1, the gate of the NMOS tube M8 is connected with the drain of the NMOS tube M5, and the drain of the NMOS tube M8 is connected with the negative feedback control circuit.
The specific structure of the dynamic clamping circuit B is as follows: the dynamic clamp circuit comprises PMOS tubes M29-M34 which are sequentially connected in series, wherein the source electrode of each last PMOS tube is connected with the drain electrode of the next PMOS tube, meanwhile, the grid electrodes and the source electrodes of the PMOS tubes M30-M33 are also connected, the grid electrode of the PMOS tube M34 is connected with the dynamic clamp circuit A, the source electrode of the PMOS tube M34 is simultaneously connected with the dynamic clamp circuit A and the bootstrap circuit, the drain electrode of the PMOS tube M29 is connected with the source electrode of the PMOS tube M28, the drain electrode of the PMOS tube M28 is grounded, the grid electrode of the PMOS tube M28 is connected with the drain electrode of the PMOS tube M27, the source electrode of the PMOS tube M27 is connected with the drain electrode of the PMOS tube M26, meanwhile, the grid electrode of the PMOS tube M27 is also connected with the source electrode, the source electrode of the PMOS tube M26 is connected with the source electrode of the NMOS tube M25, and simultaneously, the grid electrode of the PMOS tube M26 is also connected with the source electrode of the NMOS tube M25, the gate electrode is connected; the source electrode of the PMOS transistor M28 is also simultaneously connected with the source electrode of the NMOS transistor M3, the source electrode of the NMOS transistor M4 and the source electrode of the NMOS transistor M5 in the operational amplifier OP 2;
the specific structure of the dynamic clamping circuit A is as follows: the dynamic clamp circuit comprises PMOS tubes M39-M44 which are sequentially connected in series, wherein the source electrode of each last PMOS tube is connected with the drain electrode of the next PMOS tube, meanwhile, the grid electrodes and the source electrodes of the PMOS tubes M40-M43 are also connected, the grid electrode of the PMOS tube M44 is connected with the dynamic clamp circuit A, the source electrode of the PMOS tube M44 is simultaneously connected with the dynamic clamp circuit A and the bootstrap circuit, the drain electrode of the PMOS tube M39 is connected with the source electrode of the PMOS tube M38, the drain electrode of the PMOS tube M38 is grounded, the grid electrode of the PMOS tube M38 is connected with the drain electrode of the PMOS tube M37, the source electrode of the PMOS tube M37 is connected with the drain electrode of the PMOS tube M36, meanwhile, the grid electrode of the PMOS tube M37 is also connected with the source electrode, the source electrode of the PMOS tube M36 is connected with the source electrode of the NMOS tube M35, meanwhile, the grid electrode of the PMOS tube M36 is also connected with the source electrode of the NMOS tube M35 is connected with the input end V; the source electrode of the PMOS transistor M38 is also simultaneously connected to the source electrode of the NMOS transistor M11, the source electrode of the NMOS transistor M12, and the source electrode of the NMOS transistor M13 in the operational amplifier OP 1.
The negative feedback control circuit has the specific structure as follows: the single gain buffer comprises unit gain buffers formed by MOS tubes M17-M20, generates current through a resistor R3, and feeds the current back to the voltage conversion circuit through a current mirror structure formed by MOS tubes M23 and M24, so that the sampling precision and the circuit stability are improved.
The negative feedback control circuit has the specific structure as follows: a PMOS tube M17 and a PMOS tube M18 are used as differential pair tubes, the gate of the PMOS tube M17 is connected with the drain of the PMOS tube M16, the source of the PMOS tube M17 is connected with the source of the PMOS tube M18, and is also connected with the drain of the PMOS tube M21, the source of the PMOS tube M21 is connected with VD33, the drain of the PMOS tube M17 is connected with the drain of the NMOS tube M17, the source of the NMOS tube M17 is connected with the source of the NMOS tube M17, and is grounded at the same time, the gate of the NMOS tube M17 is connected with the gate of the NMOS tube M17, the gate of the NMOS tube M17 is also connected with the drain, the drain of the NMOS tube M17 is also connected with the drain of the PMOS tube M17, the gate of the PMOS tube M17 is also connected with the drain of the PMOS tube M17 through a resistor R17, the source of the PMOS tube M17 is also connected with the drain of the PMOS tube M17, the gate of the PMOS tube M17 is also connected with the drain of the PMOS tube M17, the drain of the PMOS tube M17 is also connected with the gate of the PMOS tube M17, the source electrode of the PMOS tube M24 is connected with the bootstrap circuit, and the drain electrode of the PMOS tube M24 is connected with the drain electrode of the PMOS tube M18.
The bootstrap circuit has the specific structure that: the negative feedback control circuit comprises a selector MUX, wherein the output end of the selector MUX is connected with the source electrode of a PMOS tube M24 and the source electrode of a PMOS tube M23 in the negative feedback control circuit, one input end of the selector MUX is connected with one end of a switch S4 and is connected with a power supply VCC1, the other end of the switch S4 is connected with one end of a capacitor C1 and one end of a switch S2 respectively, the other end of the switch S2 is grounded, the other input end of the selector MUX is connected with one end of a switch S3, the other end of the switch S3 is connected with the other end of a capacitor C1, the other end of the switch S3 is also connected with one end of a switch S1, and the other end of the switch S1 is connected with a power.
The invention has the advantages that a high-precision battery voltage sampling circuit adopts a dynamically-responsive resistance voltage division network and a closed-loop negative feedback control structure, and a bootstrap circuit, realizes the resistance voltage division network which can dynamically sample the battery voltage without being interfered by the voltage drop of a switching tube by combining with a unity gain buffer, realizes the core device of an operational amplifier which processes the high voltage by adopting a common low-voltage tube through a clamping circuit, improves the precision and the stability of the resistance voltage division network through the closed-loop negative feedback circuit, and provides the voltage higher than a power supply through the bootstrap circuit, so that the working range of the negative feedback circuit is widened, higher sampling precision and system stability are realized, the operational amplifier is prevented from adopting a high-voltage tube, the power consumption and the area are reduced, and the overall performance of the circuit is improved.
Drawings
FIG. 1 is a high-precision battery voltage sampling specific circuit structure;
FIG. 2 is a schematic diagram of a negative feedback architecture and a bootstrap circuit.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention relates to a high-precision battery voltage sampling circuit, which comprises a voltage conversion circuit, wherein the voltage conversion circuit is composed of two amplifiers with the same structure, namely an operational amplifier OP1 and an operational amplifier OP2, the input end of the operational amplifier OP2 is Vn +, the dynamic clamping circuit B provides a power ground for the operational amplifier OP2, and the dynamic clamping circuit B reduces the voltage of Vn + by 2VGSAs the ground of the operational amplifier OP2, the voltage is raised by 5V through the PMOS connected by 5 series diodesGSAs the power supply of the operational amplifier OP2, the power supply ground voltage difference of the operational amplifier OP2 is always 5VGSAnd the power ground voltage changes along with the input voltage, the input end of the operational amplifier OP1 is Vn-, the dynamic clamp circuit A provides the power ground of the operational amplifier OP1, and the dynamic clamp circuit A and the dynamic clamp circuit B have the same structure;
the voltage conversion circuit is further connected with the negative feedback control circuit, the negative feedback control circuit is further connected with the bootstrap circuit, the precision and the stability of the voltage conversion circuit are improved through the closed-loop negative feedback circuit, the voltage higher than a power supply is provided through the bootstrap circuit, the working range of the negative feedback circuit is widened, and the higher sampling precision and the system stability are achieved.
As shown in fig. 1, the specific structure of the voltage conversion circuit is as follows: the operational amplifier OP1 and OP2 with the same structure are included, a PMOS tube M1 and a PMOS tube M2 are used as input differential pair transistors in the operational amplifier OP2, the grid electrode of the PMOS tube M2 is connected to an input end Vn +, concretely, the source electrode of the PMOS tube M1 is connected to the source electrode of the PMOS tube M2 and also connected to the drain electrode of the PMOS tube M6, the source electrode of the PMOS tube M6 is connected to the dynamic clamp circuit B, the drain electrode of the PMOS tube M1 is connected to the drain electrode of the NMOS tube M3, the source electrode of the NMOS tube M3 is connected to the dynamic clamp circuit B, the grid electrode of the NMOS tube M3 is connected to the grid electrode of the NMOS tube M4, meanwhile, the grid electrode of the NMOS tube M3 is also connected to the drain electrode of the NMOS tube M3, the source electrode of the NMOS tube M4 is connected to the dynamic clamp circuit B, the drain electrode of the NMOS tube M4 is connected to the drain electrode of the PMOS tube M2, the drain electrode of the PMOS tube M2 is connected to the drain electrode of the PMOS tube M1, and then connected to the dynamic clamp circuit 7, the drain electrode of the PMOS tube M7 is also connected with the drain electrode of an NMOS tube M5, the source electrode of the NMOS tube M5 is connected with the dynamic clamping circuit B, and the grid electrode of the NMOS tube M5 is connected with the drain electrode of the PMOS tube M2;
in the operational amplifier OP1, a PMOS transistor M9 and a PMOS transistor M10 are used as input differential pair transistors, a gate of a PMOS transistor M10 is connected to an input terminal Vn +, specifically, a source of a PMOS transistor M9 is connected to a source of a PMOS transistor M10 and simultaneously connected to a drain of a PMOS transistor M15, a source of a PMOS transistor M15 is connected to the dynamic clamp circuit a, a drain of a PMOS transistor M9 is connected to a drain of an NMOS transistor M11, a source of an NMOS transistor M11 is connected to the dynamic clamp circuit a, a gate of an NMOS transistor M11 is connected to a gate of an NMOS transistor M12, a gate of an NMOS transistor M11 is also connected to a drain of an NMOS transistor M11, a source of an NMOS transistor M12 is connected to the dynamic clamp circuit a, a drain of an NMOS transistor M12 is connected to a drain of a PMOS transistor M10, a drain of a PMOS transistor M10 is also connected to a drain of a resistor Rm2 and a drain of a capacitor M2 in turn, a source of a PMOS transistor M14 is connected to a drain of an NMOS transistor M14 and a drain of an NMOS transistor M14, the source electrode of the NMOS tube M13 is connected with the dynamic clamping circuit A, and the grid electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M10;
the drain of the NMOS tube M13 is also connected with the gate of the PMOS tube M16, the drain of the PMOS tube M16 is connected to the ground through a resistor R2, the source of the PMOS tube M16 is connected with the source of the NMOS tube M8 through a resistor R1, the source of the NMOS tube M8 is also connected with the gate of the PMOS tube M1, the gate of the NMOS tube M8 is connected with the drain of the NMOS tube M5, and the drain of the NMOS tube M8 is connected with the negative feedback control circuit.
The specific structure of the dynamic clamping circuit B is as follows: the dynamic clamp circuit comprises PMOS tubes M29-M34 which are sequentially connected in series, wherein the source electrode of each last PMOS tube is connected with the drain electrode of the next PMOS tube, meanwhile, the grid electrodes and the source electrodes of the PMOS tubes M30-M33 are also connected, the grid electrode of the PMOS tube M34 is connected with the dynamic clamp circuit A, the source electrode of the PMOS tube M34 is simultaneously connected with the dynamic clamp circuit A and the bootstrap circuit, the drain electrode of the PMOS tube M29 is connected with the source electrode of the PMOS tube M28, the drain electrode of the PMOS tube M28 is grounded, the grid electrode of the PMOS tube M28 is connected with the drain electrode of the PMOS tube M27, the source electrode of the PMOS tube M27 is connected with the drain electrode of the PMOS tube M26, meanwhile, the grid electrode of the PMOS tube M27 is also connected with the source electrode, the source electrode of the PMOS tube M26 is connected with the source electrode of the NMOS tube M25, and simultaneously, the grid electrode of the PMOS tube M26 is also connected with the source electrode of the NMOS tube M25, the gate electrode is connected; the source electrode of the PMOS transistor M28 is also simultaneously connected with the source electrode of the NMOS transistor M3, the source electrode of the NMOS transistor M4 and the source electrode of the NMOS transistor M5 in the operational amplifier OP 2;
the specific structure of the dynamic clamping circuit A is as follows: the dynamic clamp circuit comprises PMOS tubes M39-M44 which are sequentially connected in series, wherein the source electrode of each last PMOS tube is connected with the drain electrode of the next PMOS tube, meanwhile, the grid electrodes and the source electrodes of the PMOS tubes M40-M43 are also connected, the grid electrode of the PMOS tube M44 is connected with the dynamic clamp circuit A, the source electrode of the PMOS tube M44 is simultaneously connected with the dynamic clamp circuit A and the bootstrap circuit, the drain electrode of the PMOS tube M39 is connected with the source electrode of the PMOS tube M38, the drain electrode of the PMOS tube M38 is grounded, the grid electrode of the PMOS tube M38 is connected with the drain electrode of the PMOS tube M37, the source electrode of the PMOS tube M37 is connected with the drain electrode of the PMOS tube M36, meanwhile, the grid electrode of the PMOS tube M37 is also connected with the source electrode, the source electrode of the PMOS tube M36 is connected with the source electrode of the NMOS tube M35, meanwhile, the grid electrode of the PMOS tube M36 is also connected with the source electrode of the NMOS tube M35 is connected with the input end V; the source electrode of the PMOS transistor M38 is also simultaneously connected to the source electrode of the NMOS transistor M11, the source electrode of the NMOS transistor M12, and the source electrode of the NMOS transistor M13 in the operational amplifier OP 1.
The negative feedback control circuit has the specific structure as follows: the single gain buffer comprises unit gain buffers formed by MOS tubes M17-M20, generates current through a resistor R3, and feeds the current back to the voltage conversion circuit through a current mirror structure formed by MOS tubes M23 and M24, so that the sampling precision and the circuit stability are improved.
The negative feedback control circuit has the specific structure as follows: a PMOS tube M17 and a PMOS tube M18 are used as differential pair tubes, the gate of the PMOS tube M17 is connected with the drain of the PMOS tube M16, the source of the PMOS tube M17 is connected with the source of the PMOS tube M18, and is also connected with the drain of the PMOS tube M21, the source of the PMOS tube M21 is connected with VD33, the drain of the PMOS tube M17 is connected with the drain of the NMOS tube M17, the source of the NMOS tube M17 is connected with the source of the NMOS tube M17, and is grounded at the same time, the gate of the NMOS tube M17 is connected with the gate of the NMOS tube M17, the gate of the NMOS tube M17 is also connected with the drain, the drain of the NMOS tube M17 is also connected with the drain of the PMOS tube M17, the gate of the PMOS tube M17 is also connected with the drain of the PMOS tube M17 through a resistor R17, the source of the PMOS tube M17 is also connected with the drain of the PMOS tube M17, the gate of the PMOS tube M17 is also connected with the drain of the PMOS tube M17, the drain of the PMOS tube M17 is also connected with the gate of the PMOS tube M17, the source electrode of the PMOS tube M24 is connected with the bootstrap circuit, and the drain electrode of the PMOS tube M24 is connected with the drain electrode of the PMOS tube M18.
The bootstrap circuit has the specific structure that: the negative feedback control circuit comprises a selector MUX, wherein the output end of the selector MUX is connected with the source electrode of a PMOS tube M24 and the source electrode of a PMOS tube M23 in the negative feedback control circuit, one input end of the selector MUX is connected with one end of a switch S4 and is connected with a power supply VCC1, the other end of the switch S4 is connected with one end of a capacitor C1 and one end of a switch S2 respectively, the other end of the switch S2 is grounded, the other input end of the selector MUX is connected with one end of a switch S3, the other end of the switch S3 is connected with the other end of a capacitor C1, the other end of the switch S3 is also connected with one end of a switch S1, and the other end of the switch S1 is connected with a power.
FIG. 1 shows a specific circuit structure for sampling high-precision battery voltage, where Vn + and Vn-respectively represent positive and negative voltages of a selected battery, and in the voltage conversion circuit structure, an operational amplifier for transmitting Vn + is composed of MOS transistors M1-M7, MOS transistors M1-M7 use common low-voltage transistors, MOS transistors M1 and M2 use input differential pair transistors, and input terminals are Vn + and Vn + in a wide range, so that the operational amplifier can normally operate using low-voltage devices, and a dynamic clamp circuit provides a power ground for the operational amplifier. The dynamic clamping circuit is composed of MOS transistors M25-M34 and reduces the voltage of Vn + by 2VGSAs a ground for the operational amplifier, and then 5PMOS connected by series diode is increased by 5VGSAs the power supply of the operational amplifier, the voltage difference of the power supply and the ground of the operational amplifier is always 5VGSAnd the power supply ground voltage changes following the input voltage. The operational amplifier and the clamp circuit for transmitting Vn-have the same principle. Thus, the voltage drop across the resistor R1 is always the battery voltage, and the error is relatively small.
The MOS tubes M17-M24 are negative feedback control circuits, the MOS tubes M17-M22 form a unit gain buffer, current is generated through a resistor R3, and the current is fed back to the voltage conversion circuit through the MOS tubes M23 and M24 of a current mirror structure, so that the sampling precision and the circuit stability are improved.
The bootstrap circuit is composed of switches S1-S4, capacitor C1 and selector MUX, and provides the power supply of the whole circuit. When the battery is selected to be not the highest, the power supply of the whole circuit is the voltage VCC1 of the series battery pack; when the highest battery is selected, the VCC2 is the power supply of the whole circuit, so that the operational amplifier for transmitting the positive voltage of the battery and the whole negative feedback system can work normally, and the function and performance of the circuit are ensured.
Fig. 2 is a schematic diagram of a negative feedback control structure and a bootstrap circuit, the negative feedback control structure is composed of a unit gain buffer OP3, a MOS transistor M3, a current mirror MOS transistor M4 and a MOS transistor M5, the input of the unit gain buffer OP3 is a sampling voltage, the sampling voltage is converted into a current through the unit gain buffer and a resistor R3, and the current is fed back to the voltage conversion circuit through the current mirror MOS transistors M4 and M5, so as to realize negative feedback control. The highest voltage of the series battery pack is VCC1, the highest voltage of the whole circuit is provided by VCC1, but when the highest battery is read, the power supply and the input voltage of the operational amplifier OP1 with Vn + as the input are equal, and the battery pack cannot work normally; even if the anode voltage of the highest battery is directly connected to the resistance voltage division network, the source and drain voltages of the MOS transistor M5 are both VCC1, the MOS transistor can not enter a saturation region, and negative feedback control can not work normally, so that the sampling precision of the highest battery is reduced.
A bootstrap circuit is added in the invention, when the highest battery is read, the highest voltage of the circuit is raised, so that an MOS tube M5 enters a saturation region, and negative feedback control is normally operated, the bootstrap circuit consists of a capacitor C1 and four switches S1-S4, wherein in the whole chip starting stage, the switch S1 and the switch S2 are opened to charge the capacitor C1, after the chip is started, the voltage difference between two polar plates of the capacitor C1 is VD33 (which can be provided by a power circuit in the chip such as L DO), only when the highest battery voltage is read, the switch S1 and the switch S2 are opened, the switch S3 and the switch S4 are closed, the switch S4 is connected with the highest voltage VCC1 of the battery pack, by utilizing the principle that the voltage between two polar plates of the capacitor does not suddenly change, the voltage at the switch S1 is VCC1, the VCC1 is VCC1+ VD33, the highest voltage conversion is realized by an alternative MUX circuit, when the SE 72 is 1 (high voltage), the highest voltage is read, the VCC1 is read, the highest voltage is a drain of the MOS tube, the MOS tube M is read, the MOS tube M1, the highest voltage is read, the MOS tube M is taken as a saturation region, the MOS tube M1, the MOS tube M, the MOS tube is taken as a sampling amplifier, and the MOS tube M is taken as a high voltage, and the MOS tube, the MOS tube M is taken as a high voltage, the MOS tube M1.
According to the high-voltage and low-voltage characteristics of different batteries, the high-precision battery voltage sampling circuit can directly sample a first battery (connected to the ground), and other batteries can realize the conversion from high voltage to low voltage through the voltage conversion circuit. According to different application ranges of the circuit, the output voltage range is limited, the proportion of resistors in the resistor voltage dividing network can be adjusted, and the voltage dividing resistor suitable for the voltage of the first battery is matched with the proportion of resistors suitable for other batteries.
The positive and negative voltages of the battery are respectively transmitted to the resistance voltage dividing network through the unit gain buffer, so that the battery voltage can be dynamically input to the resistance voltage dividing network, and the influence of voltage drop generated by the on-resistance on sampling voltage during direct transmission of the switching tube can be avoided.
A dynamic clamping circuit which changes along with input voltage is adopted to provide a power ground of the operational amplifier, so that a core device of the operational amplifier adopts a common low-voltage tube, the power consumption and the area of a chip are reduced, and the performance is improved.
The output voltage of the resistance voltage division network is subjected to V-I conversion and is superposed on the resistance voltage division network through a closed-loop negative feedback control structure, so that the precision and the stability of the resistance voltage division network are improved.
The negative feedback control structure adopts a unit gain buffer and a resistor to realize V-I conversion, the unit gain buffer adopts an operational amplifier and a common source amplifier circuit, and the introduced current generates a fixed proportion current through a current mirror and is input into a resistor voltage division network, so that the influence of voltage drop in the battery voltage sampling process can be well inhibited, and the voltage sampling precision and the circuit stability are improved.
When the highest battery in the series battery pack is selected, the input of an operational amplifier for transmitting the positive voltage of the battery is equal to the power supply and cannot work normally, a current mirror of the negative feedback system cannot work normally due to the fact that the source voltage and the drain voltage are equal, a bootstrap circuit is formed by the capacitors controlled by the switches in a combined mode, voltage higher than the power supply is provided, the working point of the operational amplifier is met, the working condition of the current mirror is met, negative feedback control can work normally within all sampling voltage ranges, and the precision and the stability of the system are improved.
The invention adopts a resistance voltage division network with dynamic response, a closed-loop negative feedback control structure and a bootstrap circuit suitable for the closed-loop negative feedback control structure, realizes the resistance voltage division network capable of dynamically sampling the battery voltage without being interfered by the voltage drop of a switch tube by combining a unit gain buffer, realizes the core device of an operational amplifier for processing high voltage by adopting a common low-voltage tube through a clamping circuit, improves the precision and the stability of the resistance voltage division network through the closed-loop negative feedback circuit, provides the voltage higher than a power supply through the bootstrap circuit, widens the working range of a negative feedback circuit, realizes higher sampling precision and system stability, avoids the operational amplifier adopting a high-voltage tube, reduces the power consumption and the area, and improves the overall performance of the circuit.

Claims (6)

1. A high-precision battery voltage sampling circuit is characterized by comprising a voltage conversion circuit, wherein the voltage conversion circuit is composed of two amplifiers with the same structure, namely an operational amplifier OP1 and an operational amplifier OP2, the input end of the operational amplifier OP2 is Vn +, and a dynamic clamping circuit B provides operation for the operational amplifierPower ground of amplifier OP2, dynamic clamp B lowers Vn + voltage by 2VGSAs the ground of the operational amplifier OP2, the voltage is raised by 5V through the PMOS connected by 5 series diodesGSAs the power supply of the operational amplifier OP2, the power supply ground voltage difference of the operational amplifier OP2 is always 5VGSAnd the power ground voltage changes along with the input voltage, the input end of the operational amplifier OP1 is Vn-, the dynamic clamp circuit A provides the power ground of the operational amplifier OP1, and the dynamic clamp circuit A and the dynamic clamp circuit B have the same structure;
the voltage conversion circuit is further connected with the negative feedback control circuit, the negative feedback control circuit is further connected with the bootstrap circuit, the precision and the stability of the voltage conversion circuit are improved through the closed-loop negative feedback circuit, the voltage higher than a power supply is provided through the bootstrap circuit, the working range of the negative feedback circuit is widened, and the higher sampling precision and the system stability are achieved.
2. The high-precision battery voltage sampling circuit according to claim 1, wherein the voltage conversion circuit has a specific structure: the operational amplifier OP1 and OP2 with the same structure are included, a PMOS tube M1 and a PMOS tube M2 are used as input differential pair transistors in the operational amplifier OP2, the grid electrode of the PMOS tube M2 is connected to an input end Vn +, concretely, the source electrode of the PMOS tube M1 is connected to the source electrode of the PMOS tube M2 and also connected to the drain electrode of the PMOS tube M6, the source electrode of the PMOS tube M6 is connected to the dynamic clamp circuit B, the drain electrode of the PMOS tube M1 is connected to the drain electrode of the NMOS tube M3, the source electrode of the NMOS tube M3 is connected to the dynamic clamp circuit B, the grid electrode of the NMOS tube M3 is connected to the grid electrode of the NMOS tube M4, meanwhile, the grid electrode of the NMOS tube M3 is also connected to the drain electrode of the NMOS tube M3, the source electrode of the NMOS tube M4 is connected to the dynamic clamp circuit B, the drain electrode of the NMOS tube M4 is connected to the drain electrode of the PMOS tube M2, the drain electrode of the PMOS tube M2 is connected to the drain electrode of the PMOS tube M1, and then connected to the dynamic clamp circuit 7, the drain electrode of the PMOS tube M7 is also connected with the drain electrode of an NMOS tube M5, the source electrode of the NMOS tube M5 is connected with the dynamic clamping circuit B, and the grid electrode of the NMOS tube M5 is connected with the drain electrode of the PMOS tube M2;
in the operational amplifier OP1, a PMOS transistor M9 and a PMOS transistor M10 are used as input differential pair transistors, a gate of a PMOS transistor M10 is connected to an input terminal Vn +, specifically, a source of a PMOS transistor M9 is connected to a source of a PMOS transistor M10 and simultaneously connected to a drain of a PMOS transistor M15, a source of a PMOS transistor M15 is connected to the dynamic clamp circuit a, a drain of a PMOS transistor M9 is connected to a drain of an NMOS transistor M11, a source of an NMOS transistor M11 is connected to the dynamic clamp circuit a, a gate of an NMOS transistor M11 is connected to a gate of an NMOS transistor M12, a gate of an NMOS transistor M11 is also connected to a drain of an NMOS transistor M11, a source of an NMOS transistor M12 is connected to the dynamic clamp circuit a, a drain of an NMOS transistor M12 is connected to a drain of a PMOS transistor M10, a drain of a PMOS transistor M10 is also connected to a drain of a resistor Rm2 and a drain of a capacitor M2 in turn, a source of a PMOS transistor M14 is connected to a drain of an NMOS transistor M14 and a drain of an NMOS transistor M14, the source electrode of the NMOS tube M13 is connected with the dynamic clamping circuit A, and the grid electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M10;
the drain of the NMOS tube M13 is also connected with the gate of the PMOS tube M16, the drain of the PMOS tube M16 is connected to the ground through a resistor R2, the source of the PMOS tube M16 is connected with the source of the NMOS tube M8 through a resistor R1, the source of the NMOS tube M8 is also connected with the gate of the PMOS tube M1, the gate of the NMOS tube M8 is connected with the drain of the NMOS tube M5, and the drain of the NMOS tube M8 is connected with the negative feedback control circuit.
3. The high-precision battery voltage sampling circuit according to claim 2, wherein the dynamic clamping circuit B has a specific structure: the dynamic clamp circuit comprises PMOS tubes M29-M34 which are sequentially connected in series, wherein the source electrode of each last PMOS tube is connected with the drain electrode of the next PMOS tube, meanwhile, the grid electrodes and the source electrodes of the PMOS tubes M30-M33 are also connected, the grid electrode of the PMOS tube M34 is connected with the dynamic clamp circuit A, the source electrode of the PMOS tube M34 is simultaneously connected with the dynamic clamp circuit A and the bootstrap circuit, the drain electrode of the PMOS tube M29 is connected with the source electrode of the PMOS tube M28, the drain electrode of the PMOS tube M28 is grounded, the grid electrode of the PMOS tube M28 is connected with the drain electrode of the PMOS tube M27, the source electrode of the PMOS tube M27 is connected with the drain electrode of the PMOS tube M26, meanwhile, the grid electrode of the PMOS tube M27 is also connected with the source electrode, the source electrode of the PMOS tube M26 is connected with the source electrode of the NMOS tube M25, and simultaneously, the grid electrode of the PMOS tube M26 is also connected with the source electrode of the NMOS tube M25, the gate electrode is connected; the source electrode of the PMOS transistor M28 is also simultaneously connected with the source electrode of the NMOS transistor M3, the source electrode of the NMOS transistor M4 and the source electrode of the NMOS transistor M5 in the operational amplifier OP 2;
the specific structure of the dynamic clamping circuit A is as follows: the dynamic clamp circuit comprises PMOS tubes M39-M44 which are sequentially connected in series, wherein the source electrode of each last PMOS tube is connected with the drain electrode of the next PMOS tube, meanwhile, the grid electrodes and the source electrodes of the PMOS tubes M40-M43 are also connected, the grid electrode of the PMOS tube M44 is connected with the dynamic clamp circuit A, the source electrode of the PMOS tube M44 is simultaneously connected with the dynamic clamp circuit A and the bootstrap circuit, the drain electrode of the PMOS tube M39 is connected with the source electrode of the PMOS tube M38, the drain electrode of the PMOS tube M38 is grounded, the grid electrode of the PMOS tube M38 is connected with the drain electrode of the PMOS tube M37, the source electrode of the PMOS tube M37 is connected with the drain electrode of the PMOS tube M36, meanwhile, the grid electrode of the PMOS tube M37 is also connected with the source electrode, the source electrode of the PMOS tube M36 is connected with the source electrode of the NMOS tube M35, meanwhile, the grid electrode of the PMOS tube M36 is also connected with the source electrode of the NMOS tube M35 is connected with the input end V; the source electrode of the PMOS transistor M38 is also simultaneously connected to the source electrode of the NMOS transistor M11, the source electrode of the NMOS transistor M12, and the source electrode of the NMOS transistor M13 in the operational amplifier OP 1.
4. The high-precision battery voltage sampling circuit according to claim 3, wherein the negative feedback control circuit has a specific structure: the single gain buffer comprises unit gain buffers formed by MOS tubes M17-M20, generates current through a resistor R3, and feeds the current back to the voltage conversion circuit through a current mirror structure formed by MOS tubes M23 and M24, so that the sampling precision and the circuit stability are improved.
5. The high-precision battery voltage sampling circuit according to claim 3, wherein the negative feedback control circuit has a specific structure: a PMOS tube M17 and a PMOS tube M18 are used as differential pair tubes, the gate of the PMOS tube M17 is connected with the drain of the PMOS tube M16, the source of the PMOS tube M17 is connected with the source of the PMOS tube M18, and is also connected with the drain of the PMOS tube M21, the source of the PMOS tube M21 is connected with VD33, the drain of the PMOS tube M17 is connected with the drain of the NMOS tube M17, the source of the NMOS tube M17 is connected with the source of the NMOS tube M17, and is grounded at the same time, the gate of the NMOS tube M17 is connected with the gate of the NMOS tube M17, the gate of the NMOS tube M17 is also connected with the drain, the drain of the NMOS tube M17 is also connected with the drain of the PMOS tube M17, the gate of the PMOS tube M17 is also connected with the drain of the PMOS tube M17 through a resistor R17, the source of the PMOS tube M17 is also connected with the drain of the PMOS tube M17, the gate of the PMOS tube M17 is also connected with the drain of the PMOS tube M17, the drain of the PMOS tube M17 is also connected with the gate of the PMOS tube M17, the source electrode of the PMOS tube M24 is connected with the bootstrap circuit, and the drain electrode of the PMOS tube M24 is connected with the drain electrode of the PMOS tube M18.
6. The high-precision battery voltage sampling circuit according to claim 5, wherein the bootstrap circuit has a specific structure: the negative feedback control circuit comprises a selector MUX, wherein the output end of the selector MUX is connected with the source electrode of a PMOS tube M24 and the source electrode of a PMOS tube M23 in the negative feedback control circuit, one input end of the selector MUX is connected with one end of a switch S4 and is connected with a power supply VCC1, the other end of the switch S4 is connected with one end of a capacitor C1 and one end of a switch S2 respectively, the other end of the switch S2 is grounded, the other input end of the selector MUX is connected with one end of a switch S3, the other end of the switch S3 is connected with the other end of a capacitor C1, the other end of the switch S3 is also connected with one end of a switch S1, and the other end of the switch S1 is connected with a power.
CN202010181836.1A 2020-03-16 2020-03-16 High-precision battery voltage sampling circuit Pending CN111398656A (en)

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Application publication date: 20200710