CN107727925A - A kind of high precision wide range peak point current sample circuit - Google Patents
A kind of high precision wide range peak point current sample circuit Download PDFInfo
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- CN107727925A CN107727925A CN201711101616.8A CN201711101616A CN107727925A CN 107727925 A CN107727925 A CN 107727925A CN 201711101616 A CN201711101616 A CN 201711101616A CN 107727925 A CN107727925 A CN 107727925A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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Abstract
A kind of high precision wide range peak point current sample circuit, applied to double N pipes synchronous commutation type Buck converters, belong to electric and electronic technical field.Its source current potential Vx is clamped to power switch node SW points by clamping operational amplifier OP and adjustment pipe M1 including SenseFET sampling pipes MNs, pre- reduction voltage circuit, clamp operational amplifier OP, NMOS adjustment pipe M1 and sampling resistor R1, SenseFET sampling pipe MNs；Pre- reduction voltage circuit realizes pre- buck functionality, and make its decompression size adjustable by extra feedback control, so that its output is stable in clamp amplifier input range, ensure realize normal current sample in the power power-supply of wide variation, sample rate current is converted into sampled voltage by sampling resistor R1.The achievable wide scope of the present invention, the sampling of high-precision peak point current, meanwhile, grid input amplifier structure improves peak point current sampling lower limit, has expanded its sample rate current scope, ensure that has high current sample precision under wide input voltage range.
Description
Technical field
The invention belongs to electric and electronic technical field, is related to a kind of height for being used for double N pipe synchronous commutation type Buck converters
Precision wide scope peak point current sample circuit.
Background technology
In Peak Current Mode Buck converters, peak point current sampling precision is high, can reach more preferable loop control effect,
And as the sampling of numerous new technologies is for example floated grid voltage, floating grid width, transient state lift technique etc., it is to inductive current information
Sampling precision require more and more higher.
High-precision SenseFET current samples key is the voltage clamp precision of SenseFET sampling pipe sources, clamp
Precision is higher, then it is more accurate with the mirroring ratios of power tube, and obtained sample rate current is also closer identical with its dimension scale
Inductive current size.
The input range of general double N pipe Buck converters is very wide, and how in wide input range to realize that SenseFET is adopted
Sample pipe source is clamping into for one of limited samples scope, the subject matter of precision.The input range of grid input clamp amplifier
It is general narrower, it can not meet to require corresponding to the Buck converters input range of wide scope.In general common gate amplifying circuit is such as
Shown in Fig. 1, its sampling pipe MNs sources clamp is completed by common gate clamp amplifier, but common gate clamp amplifier can take out from input
Obtaining current, namely extra Ib electric currents supply common gate clamp amplifier can be extracted from Isense as its bias current, so
Result in actually to flow through on sampling resistor electric current and compare and to reduce Ib with Isense so as to reduce its sampling precision, and
Low inductive current down-sampling electric current can not even provide bias current needed for common grid amplifying stage so as to cause to clamp amplifier failure.
The content of the invention
The problem to be solved in the present invention：When under wide input range, the clamp effect of traditional SenseFET sampling pipes source
It is deteriorated, sampling precision declines；Second, during light load, traditional common gate input stage clamp amplifier failure, so as to limit it
Underloading sample effect.In view of the above-mentioned problems, the present invention proposes a kind of high precision wide range peak point current sample circuit, applied to double
N pipe Buck converters, sample circuit is enabled to be applied to width using SenseFET sampling pipes, pre- reduction voltage circuit and clamp amplifier
Input voltage range, input amplifier structure using grid and improve current sample scope and precision, it is achieved thereby that wide-range high-accuracy
Peak point current sampling.
The technical scheme is that：
A kind of high precision wide range peak point current sample circuit, applied to double N pipes synchronous commutation type Buck converters, including
SenseFET sampling pipes MNs, pre- reduction voltage circuit, clamp operational amplifier OP, NMOS adjustment pipe M1 and sampling resistor R1,
SenseFET sampling pipes MNs grid connects the power upper tube of double N pipes synchronous commutation type Buck converters
Grid, its connection power power-supply PVDD that drains, its source electrode connect the leakage of the positive input terminal and NMOS adjustment pipes M1 of pre- reduction voltage circuit
Pole；
The negative input end of pre- reduction voltage circuit connects the switching node SW of double N pipes synchronous commutation type Buck converters, its
Positive-negative output end connects clamp operational amplifier OP positive-negative input end respectively；
Pipe M1 grid connection clamp bit arithmetic amplifier OP output end is adjusted, its source electrode is defeated as the sample circuit
Go out end and by being grounded after sampling resistor R1；
The pre- reduction voltage circuit includes pre- decompression and clamps operational amplifier OP_P, the first input NMOS tube M2, the second input
NMOS tube M3, the first current mirror NMOS tube M4 and the second current mirror NMOS tube M5,
Negative input end of the first input NMOS tube M2 grid as the pre- reduction voltage circuit, its connection power power-supply that drains
PVDD, the drain electrode of the pre- decompression clamp operational amplifier OP_P of its source electrode connection positive input terminal and the first current mirror NMOS tube M4 is simultaneously
Negative output terminal as the pre- reduction voltage circuit；
Positive input terminal of the second input NMOS tube M3 grid as the pre- reduction voltage circuit, its connection power power-supply that drains
PVDD, its source electrode connect the second current mirror NMOS tube M5 drain electrode and as the positive output ends of the pre- reduction voltage circuit；
Pre- decompression clamp operational amplifier OP_P negative input end is connected current potential, and its output end connects the first current mirror
NMOS tube M4 and the second current mirror NMOS tube M5 grid, the first current mirror NMOS tube M4 and the second current mirror NMOS tube M5 source
Pole is grounded.
Specifically, the clamp operational amplifier OP and the clamp that pre- decompression clamper operational amplifier OP_P is same structure
Amplifier, including the first PMOS M6, the second PMOS M7, the 3rd PMOS M10, the first NMOS tube M8, the second NMOS tube M9,
Three NMOS tube M11, the 4th NMOS tube M12, the 5th NMOS tube M13, electric capacity C1 and current source,
Negative input end of the first NMOS tube M8 grid as the clamp amplifier, it drains the first PMOS M6's of connection
Grid and drain electrode and the second PMOS M7 grid, its source electrode connect the second NMOS tube M9 source electrode and the 4th NMOS tube M12
Drain electrode；
Positive input terminal of the second NMOS tube M9 grid as the clamp amplifier, it drains the second PMOS M7's of connection
Drain electrode and the 3rd PMOS M10 grid；
The negative pole connection supply voltage of current source, its positive pole connect the 3rd NMOS tube M11 grid and drain electrode, the 4th NMOS
The grid of pipe M12 grid and the 5th NMOS tube M13；
3rd PMOS M10 drain electrode connection the 5th NMOS tube M13 drain electrode and as it is described clamp amplifier output end,
Electric capacity C1 is connected between the 3rd PMOS M10 grid and drain electrode；
First PMOS M6, the second PMOS M7 and the 3rd PMOS M10 source electrode connect supply voltage, the 3rd NMOS tube
M11, the 4th NMOS tube M12 and the 5th NMOS tube M13 source ground.
Beneficial effects of the present invention are：Peak point current sample circuit proposed by the present invention is by by SenseFET sampling pipes source
End carries out voltage clamp with power switch node SW points, so as to obtain and flow through the sample rate current of upper tube current in proportion, expands
Current sampling circuit input voltage range, load current range, while ensure that current sample precision.
Brief description of the drawings
Fig. 1 is that traditional common gate clamps SenseFET current sample structural representations.
Fig. 2 is a kind of overall structure diagram of high precision wide range peak point current sample circuit provided by the invention.
Fig. 3 is pre- reduction voltage circuit P_LD and clamp amplifier OP structural representation in the present invention.
Fig. 4 is that one kind that operational amplifier is clamped in embodiment realizes circuit diagram.
Embodiment
The present invention is further described with reference to the accompanying drawings and detailed description.
It is a kind of high-precision wide for being applied to double N pipe synchronous commutation type Buck converters proposed by the present invention as shown in Figure 2
Scope peak point current sample circuit, including SenseFET sampling pipes MNs, pre- reduction voltage circuit P_LD, clamp operational amplifier OP with
And NMOS adjustment pipes M1, sampling resistor R1, sampling pipe MNs are by clamping amplifier OP and adjustment pipe M1 by its source current potential Vx pincers
Power switch node SW points are arrived in position, and so as to which MNs working condition is identical with power upper tube, and then it flows through size of current
It is equal to the scalar multiple that upper tube flows through electric current, its ratio is MNs and the breadth length ratio of power upper tube.Sampling pipe MNs grid with
Buck translation circuit power upper tubes grid end connects, its drain terminal connection power power-supply PVDD, source Vx points and pre- reduction voltage circuit P_LD
Positive input terminal and adjustment pipe M1 drain terminal connection；Pre- reduction voltage circuit P_LD negative input end and Buck converter switches nodes
SW points are connected, and its positive-negative output end is connected with the clamp positive negative inputs of amplifier OP respectively, so as to amplify the error of Vx points and SW points, pincers
Position amplifier OP output ends Vy is connected with adjusting pipe M1 grid end, and sample rate current size is adjusted by the grid end for adjusting adjustment pipe M1,
Adjustment sample rate current specific practice be：Input Vy is constituted to output Vcs by sampling pipe MNs, adjustment pipe M1, sampling resistor R1
Source follower structure, so as to which Vy change can change Vcs voltages, and sample rate current Isense sizes are Vcs/R1, from
And change the size of sample rate current；Adjustment pipe M1 sources are connected with sampling resistor R1, so as to which sample rate current is electric by sampling
Resistance R1 is converted into sampled voltage Vcs.
It is pre- reduction voltage circuit P_LD and clamp amplifier OP structural representation in the present invention as shown in Figure 3, pre- reduction voltage circuit
P_LD inputs are depressured by the first input NMOS tube M2 and the second input NMOS tube M3 common drain follower, and this is mainly
Because power power-supply voltage range is very wide, but high-precision clamper amplifier OP input range is certain, so needing to defeated
Enter and first handled.Here drain electrode follower is different from general follower, and the pressure drop mainly due to general follower is
Fixed, large-scale input voltage can not be adapted to.Here the processing done is by being depressured clamp operational amplifier OP_P in advance
The bias current of follower is adjusted, so as to which dynamic changes its voltage drop, and due to the electricity of the first current mirror NMOS tube M4 and second
Mirror NMOS tube M5 symmetry is flowed, so the first input NMOS tube M2 and the second input NMOS tube M3 push in identical bias current
Drop identical, and then only need to carry out high-precision clamp to Vd, Ve.
SenseFET sampling pipe source Vx and SW points are dropped by the follower that drains in pre- reduction voltage circuit P_LD
While pressure, ensure that the gain close to 1 times, it is pre- be depressured size by the bias current for the follower that drains is adjusted from
And it is set to be fixed in high accuracy clamp operational amplifier OP input range.
Pre- reduction voltage circuit P_LD includes forming first input NMOS tube M2 and second input NMOS tube of the input NMOS to pipe
M3, the first current mirror NMOS tube M4 and the second current mirror NMOS tube M5 that form bias current mirror and pre- decompression clamp computing
Amplifier OP_P.Wherein, the negative input end that the first input NMOS tube M2 grid end is pre- reduction voltage circuit P_LD, the first input NMOS
Pipe M2 drain terminal connection power power-supply PVDD, its source clamp operational amplifier OP_P positive input terminal and first with pre- decompression
The connected negative output terminal Vd points as pre- reduction voltage circuit P_LD of current mirror NMOS tube M4 drain terminal；Pre- decompression clamp amplifier OP_P's
Negative input end is connected with fixed potential, its output end and the first current mirror NMOS tube M4 grid end and the second current mirror NMOS tube M5
Grid end be connected, so as to realize to Vd points clamp, as long as wherein fixed potential clamp operational amplifier configuration common mode input
In the range of, specific size is determined by the clamp amplifier structure and technique actually used；Second input NMOS tube M3 grid end
For pre- buck current P_LD positive input terminal, its drain terminal is connected with power power-supply PVDD, source and the second current mirror NMOS tube M5
The connected positive output end Ve points as pre- reduction voltage circuit P_LD of drain terminal.Because the second current mirror NMOS tube M5 is the first current mirror
NMOS tube M4 mirror image, so after Vd points are clamped to Vb, the pressure difference between Ve and Vx is identical with the pressure difference between SW and Vd, from
And realize pre- buck functionality.The pre- reduction voltage circuit proposed may operate under different power input PVDD so that clamping
Amplifier OP be operated in galvanic current it is flat under, ensure its performance.
It is that one kind that operational amplifier is clamped in the present embodiment realizes circuit diagram as shown in Figure 4, what deserves to be explained is clamp
The specific implementation that operational amplifier OP and pre- decompression clamp operational amplifier OP_P have it is a variety of, clamp operational amplifier OP and
Pre- decompression clamp operational amplifier OP_P can be the clamper amplifier of different structure or same form, and Fig. 4 is one kind
Way of realization, but pre- decompression clamp amplifier OP_P and clamp operational amplifier OP and how to design and should all belong to the present invention's
In protection domain.
Pincers of the clamp operational amplifier OP with pre- decompression clamper operational amplifier OP_P for same structure in the present embodiment
Position amplifier, including the first PMOS M6, the second PMOS M7, the 3rd PMOS M10, the first NMOS tube M8, the second NMOS tube M9,
3rd NMOS tube M11, the 4th NMOS tube M12, the 5th NMOS tube M13, electric capacity C1 and current source, the first NMOS tube M8 grid are made
For the negative input end of the clamp amplifier, its first PMOS M6 of connection that drains grid and drain electrode and the second PMOS M7
Grid, its source electrode connect the drain electrode of the second NMOS tube M9 source electrode and the 4th NMOS tube M12；Second NMOS tube M9 grid conduct
The positive input terminal of the clamp amplifier, its second PMOS M7 of connection that drains drain electrode and the 3rd PMOS M10 grid；Electric current
The negative pole connection supply voltage in source, its positive pole connect the 3rd NMOS tube M11 grid and drain electrode, the 4th NMOS tube M12 grid
With the 5th NMOS tube M13 grid；3rd PMOS M10 the 5th NMOS tube M13 of drain electrode connection drain electrode is simultaneously used as the pincers
The output end of position amplifier, electric capacity C1 are connected between the 3rd PMOS M10 grid and drain electrode；First PMOS M6, the 2nd PMOS
Pipe M7 and the 3rd PMOS M10 source electrode connect supply voltage, the 3rd NMOS tube M11, the 4th NMOS tube M12 and the 5th NMOS tube
M13 source ground.
Pre- decompression clamp amplifier OP_P working method is to pass through the Vd points to its positive input terminal and one of negative input end
Fixed voltage Vb is compared and enlarged to change the first current mirror NMOS tube M4 and the second current mirror NMOS tube M5 grid voltage
So as to change bias current Ids2, Ids3, and then complete the clamp of Vd points.So when sampling progress, SW potential changes but Vd
Point keeps constant, and the difference of Vd and Ve voltages is amplified by clamping operational amplifier OP and is adjusted pipe M1 again and adjusts Vx points
Voltage, so that it is equal with SW points and then complete current sample.
By foregoing invention content, the high precision peak current sample demand in wide input range can be met, due to
The design of pre- reduction voltage circuit make it that no matter power input voltage PVDD sizes can normally complete voltage clamp function and then reality
Existing current sample, additionally, due to using grid input amplifier clamp, sample rate current lower limit is expanded, while ensure that sampling precision.
One of ordinary skill in the art can make various do not depart from originally according to these technical inspirations disclosed by the invention
The other various specific deformations and combination, these deformations and combination of invention essence are still within the scope of the present invention.
Claims (2)
1. a kind of high precision wide range peak point current sample circuit, it is characterised in that become applied to double N pipes synchronous commutation type Buck
Parallel operation, including SenseFET sampling pipes (MNs), pre- reduction voltage circuit, clamp operational amplifier (OP), NMOS adjust pipe (M1) and adopted
Sample resistance (R1),
The grid of SenseFET sampling pipes (MNs) connects the grid of the power upper tube of double N pipes synchronous commutation type Buck converters
Pole, its connection power power-supply (PVDD) that drains, its source electrode connects the positive input terminal of pre- reduction voltage circuit and NMOS adjustment is managed (M1)
Drain electrode；
The negative input end of pre- reduction voltage circuit connects the switching node (SW) of double N pipes synchronous commutation type Buck converters, and it is just
Negative output terminal connects the positive-negative input end of clamp operational amplifier (OP) respectively；
The output end of the grid connection clamp bit arithmetic amplifier (OP) of adjustment pipe (M1), its source electrode are defeated as the sample circuit
Go out to hold and be grounded afterwards by sampling resistor (R1)；
The pre- reduction voltage circuit includes pre- decompression and clamps operational amplifier (OP_P), the first input NMOS tube (M2), the second input
NMOS tube (M3), the first current mirror NMOS tube (M4) and the second current mirror NMOS tube (M5),
Negative input end of the grid of first input NMOS tube (M2) as the pre- reduction voltage circuit, its connection power power-supply that drains
(PVDD), the positive input terminal of the pre- decompression clamp operational amplifier (OP_P) of its source electrode connection and the first current mirror NMOS tube (M4)
Drain and be used as the negative output terminal of the pre- reduction voltage circuit；
Positive input terminal of the grid of second input NMOS tube (M3) as the pre- reduction voltage circuit, its connection power power-supply that drains
(PVDD), its source electrode connects the drain electrode of the second current mirror NMOS tube (M5) and as the positive output end of the pre- reduction voltage circuit；
The negative input end of pre- decompression clamp operational amplifier (OP_P) is connected current potential, and its output end connects the first current mirror
The grid of NMOS tube (M4) and the second current mirror NMOS tube (M5), the first current mirror NMOS tube (M4) and the second current mirror NMOS tube
(M5) source ground.
2. high precision wide range peak point current sample circuit according to claim 1, it is characterised in that the clamp computing
Amplifier (OP) and the clamp amplifier that pre- decompression clamper operational amplifier (OP_P) is same structure, including the first PMOS
(M6), the second PMOS (M7), the 3rd PMOS (M10), the first NMOS tube (M8), the second NMOS tube (M9), the 3rd NMOS tube
(M11), the 4th NMOS tube (M12), the 5th NMOS tube (M13), electric capacity (C1) and current source,
Negative input end of the grid of first NMOS tube (M8) as the clamp amplifier, its first PMOS of connection (M6) that drains
Grid and the grid of drain electrode and the second PMOS (M7), its source electrode connect the source electrode and the 4th NMOS tube of the second NMOS tube (M9)
(M12) drain electrode；
Positive input terminal of the grid of second NMOS tube (M9) as the clamp amplifier, its second PMOS of connection (M7) that drains
Drain electrode and the grid of the 3rd PMOS (M10)；
The negative pole connection supply voltage of current source, its positive pole connect the grid and drain electrode, the 4th NMOS tube of the 3rd NMOS tube (M11)
(M12) grid and the grid of the 5th NMOS tube (M13)；
The drain electrode of 3rd PMOS (M10) connects the drain electrode of the 5th NMOS tube (M13) and as the output end for clamping amplifier,
Electric capacity (C1) is connected between grid and the drain electrode of the 3rd PMOS (M10)；
The source electrode of first PMOS (M6), the second PMOS (M7) and the 3rd PMOS (M10) connects supply voltage, the 3rd NMOS tube
(M11), the source ground of the 4th NMOS tube (M12) and the 5th NMOS tube (M13).
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| CN201711101616.8A CN107727925B (en) | 2017-11-10 | 2017-11-10 | High-precision wide-range peak current sampling circuit |
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| CN201711101616.8A CN107727925B (en) | 2017-11-10 | 2017-11-10 | High-precision wide-range peak current sampling circuit |
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