CN114420676B - Chip-scale packaging structure capable of reducing warpage and preparation method thereof - Google Patents
Chip-scale packaging structure capable of reducing warpage and preparation method thereof Download PDFInfo
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- CN114420676B CN114420676B CN202210328945.0A CN202210328945A CN114420676B CN 114420676 B CN114420676 B CN 114420676B CN 202210328945 A CN202210328945 A CN 202210328945A CN 114420676 B CN114420676 B CN 114420676B
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- H01L23/562—Protection against mechanical damage
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a chip scale package structure for reducing warpage, which comprises: the chip packaging structure comprises a metal base layer and a chip packaging body positioned on the metal base layer; and conductive wires surrounding the chip packaging body are further arranged around the chip packaging body on the metal base layer, and an epitaxial structure extending to the upper surface of the chip packaging body is arranged on the conductive wires. The invention also discloses a preparation method of the chip scale packaging structure for reducing warpage. The packaging hoop structure formed by the metal base layer and the conductive wire with the epitaxial structure is used for packaging the chip packaging body, so that the chip packaging body can be well protected when warping occurs.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a chip-scale packaging structure capable of reducing warpage and a preparation method thereof.
Background
In the prior art, in a chip-level packaging process, a chip is subjected to a filling process of underfill, and a chip packaging unit is subjected to a molding compound packaging process, and because various packaging materials with mismatched CTEs (coefficient of Thermal Expansion) exist in a chip packaging body, a warpage phenomenon caused by CTE mismatch of the packaging materials is easily caused in a heat treatment process, a reliability test and a service process of a chip product of the chip, and the warpage causes a series of reliability problems of the chip, such as: (1) desoldering the chip I/O pin and a metal wiring layer or a packaging substrate or a bonding pad on a PCB; (2) and layering the edge of the chip plastic packaging layer and the metal wiring layer or the packaging substrate or the PCB. Therefore, the warpage problem of the chip package is a key bottleneck limiting the reliability and service life of the chip, and developers in the semiconductor industry chain also adjust the CTE of the package material through various material improvement schemes to reduce the above mismatch phenomenon, or reduce the CTE mismatch degree through local improvement of the package structure. However, the improvement effect of these solutions on warpage is not ideal, and especially in large-size chip packages, the warpage phenomenon is a key problem that limits the reliability of the chip.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a chip scale package structure for reducing warpage by forming an encapsulation hoop structure and a preparation method thereof.
A chip scale package structure for reducing warpage, comprising: the chip package comprises a metal base layer and a chip package body positioned on the metal base layer; and conductive wires surrounding the chip packaging body are further arranged around the chip packaging body on the metal base layer, and an epitaxial structure extending to the upper surface of the chip packaging body is arranged on the conductive wires.
As a preferred scheme, the chip package body comprises a chip encapsulating layer, a metal wiring layer and a conductive connecting piece which are sequentially connected; the metal wiring layer is in contact with the conductive line through a dielectric layer.
Preferably, the chip encapsulating layer comprises a chip electrically connected with the metal wiring layer, and a bottom glue filling layer is filled between the chip and the metal wiring layer.
Preferably, the chip package further includes an interconnection pillar connecting the metal base layer and the ground layer in the metal wiring layer.
Preferably, the cross-sectional structure of the conductive wire is a single structure of metal or alloy; or
The cross-sectional structure of the conductive wire is a structure that the cladding wraps the conductive column core.
Preferably, the cladding is made of tin-based alloy, and the conductive column core is made of alloy material of silver, copper, aluminum, gold or any combination thereof.
Preferably, the cladding layer is subjected to a high temperature reflow process and a flattening process for flattening the bonding tool to form the epitaxial structure.
Preferably, the epitaxial structure is formed by flattening the heated and melted bonding wires.
A preparation method of a chip scale package structure capable of reducing warpage comprises the following steps:
providing a first carrier plate with a first bonding layer, and preparing a metal wiring layer and a chip encapsulation layer on the first bonding layer;
manufacturing an annular groove on the outer side of the chip in the chip encapsulating layer;
embedding a conductive wire in the annular groove, and thinning the chip encapsulating layer and the conductive wire;
preparing a metal base layer to cover the chip encapsulating layer and the conductive wire;
preparing a second carrier plate with a second bonding layer, and laminating the second bonding layer to the metal base layer;
removing the first bonding layer and the first carrier plate;
manufacturing a conductive connecting piece on the metal wiring layer to form a chip packaging body;
Manufacturing an epitaxial structure extending to the upper surface of the chip packaging body on one side of the conductive wire close to the chip packaging layer, and forming a packaging hoop structure comprising a metal base layer-conductive wire-epitaxial structure;
and removing the second bonding layer and the second carrier plate.
Preferably, before removing the second bonding layer and the second carrier, the method further includes:
segmenting the containment cuff structure.
Preferably, the preparation of the chip encapsulation layer comprises the following steps:
manufacturing a pad structure for electrically connecting with a chip on the metal wiring layer;
bonding a chip to the pad structure;
encapsulating the chip to form a chip encapsulation layer.
Preferably, before encapsulating the chip to form a chip encapsulating layer, the method further comprises the following steps:
manufacturing an interconnection column on the metal wiring layer;
thinning the chip encapsulating layer comprises:
and thinning the chip encapsulating layer until the interconnection columns are exposed.
Compared with the prior art, the invention has the following beneficial effects:
1. the packaging hoop structure is formed by the metal base layer and the conducting wire with the epitaxial structure to package the chip packaging body, so that the chip packaging body can be well protected when warping occurs;
2. Through electrically isolating the metal wiring layer from the conductive wire, a conductive loop formed by the metal wiring layer, the conductive wire and the metal base layer is prevented, and crosstalk caused to signal transmission on the metal wiring layer is effectively prevented;
3. the grounding layer and the metal base layer on the metal wiring layer are electrically interconnected by arranging the interconnection columns, so that an effective electromagnetic shielding effect is formed on the signal transmission of the chip packaging body.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a chip scale package structure with reduced warpage according to the present invention;
FIG. 2 is a cross-sectional view A-A of FIG. 1;
FIG. 3 is a schematic flow chart illustrating a method for fabricating a chip scale package structure with reduced warpage according to the present invention;
FIGS. 4-11 are schematic structural diagrams corresponding to steps S1-S8 in the method for manufacturing a chip scale package structure with reduced warpage according to the present invention;
Fig. 12 is a schematic structural view corresponding to the leveling process of step S10 in the method for manufacturing a chip scale package structure with reduced warpage according to the present invention;
FIG. 13 is a schematic structural diagram corresponding to steps S9 and S10 in the method for manufacturing a chip scale package structure with reduced warpage according to the present invention;
FIG. 14 is a schematic flow chart illustrating a method for fabricating a chip scale package structure with reduced warpage according to another embodiment of the present invention;
fig. 15 and 16 are schematic structural views corresponding to step S11 in another embodiment of a method for manufacturing a chip scale package structure with reduced warpage according to the present invention;
fig. 17 is a schematic structural diagram corresponding to step S12 in another embodiment of the method for manufacturing a chip scale package structure with reduced warpage.
Wherein:
10a first carrier; 10b a second carrier;
11a first bonding layer; 11b a second bonding layer;
12a metal wiring layer; 12a dielectric layer;
13 pin interconnection structure; a pin 13 a; 13b solder balls; 13c a bonding pad;
14 interconnecting the columns;
15 bottom glue filling layer;
16, plastic packaging layer;
17 an annular groove;
18 a metal base layer;
20 electrically conductive lines; 20a cladding layer; 20b a conductive pillar core;
21 an epitaxial surface; 21' epitaxial hemisphere;
22 an epitaxial structure;
23 a conductive connection member;
A 24 division line;
30 leveling the horn; 31 leveling the base surface; 32 welding wires; 33 an outlet orifice;
100a first chip; 100b a second chip; 100c a third chip; 100d fourth chip;
m1 first chip packaging structure;
m2 second chip package structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A chip scale package structure with reduced warpage, as shown in fig. 1 and 17, comprising: a metal base layer 18 and a chip package on the metal base layer 18; there are also conductive traces 20 around the chip package on the metal base layer 18, the conductive traces 20 having an epitaxial structure 22 extending to the upper surface of the chip package.
In this embodiment, the metal base layer 18 and the conductive line 20 with the epitaxial structure 22 form an encapsulated collar structure. The epitaxial structure 22, the conductive lines 20 and the metal base layer 18 encapsulate the packaged chip in three-dimensional space, and protect the chip package in case of warpage. Taking the conductive wire as an example of coating the silver column core with tin-based alloy, when the chip package body is warped, the epitaxial structure 22 and the surface of the metal wiring layer 12, the metal base layer 18 and the cross section of the conductive wire 20 form an encapsulation hoop of the chip package body, and when the chip package body is warped, a longitudinal tension is formed on the chip-level package structure, and the epitaxial structure 22 can effectively resist the warped longitudinal tension of the chip package body by utilizing the mutual attractive force between tin-based alloy atoms of the epitaxial structure 22 and the mutual attractive force between the metal atom and the silver atom formed between the metal base layer 18 and the silver core layer 25 b. Therefore, the packaging hoop structure on the three-dimensional space in the technical scheme of the invention can effectively inhibit the warping of the chip packaging body caused by temperature change.
In a preferred embodiment, as shown in fig. 1, the chip package includes a chip encapsulating layer, a metal wiring layer 12 and a conductive connecting member 23 connected in sequence. The metal wiring layer 12 is in contact with the conductive line 20 through a dielectric layer 12 a. In other words, the conductive lines 20 do not make an electrical connection with the chip package.
The chip encapsulating layer comprises a chip and a plastic encapsulating layer 16 for encapsulating the chip. As shown in fig. 1, a dielectric layer 12a may be further disposed outside the metal wiring layer 12, and the metal wiring layer 12 is in contact with the conductive line 20 through the dielectric layer 12 a. Obviously, the conductive connecting element 23 is not electrically connected to the conductive wire 20.
The inventors have found in practice that, if no electrical isolation is provided between the metal wiring layer 12 and the conductive line 20, the metal wiring layer 12, the conductive line 20 and the metal base layer 18 form a conductive loop, so that a transmission signal oscillates in the loop, causing crosstalk to signal transmission on the nearby metal wiring layer 12. In this embodiment, the metal wiring layer 12 and the conductive line 20 are electrically isolated from each other.
In a preferred embodiment, as shown in fig. 1, the chip encapsulating layer includes a chip electrically connected to the metal wiring layer 12, and a underfill layer 15 is filled between the chip and the metal wiring layer 12.
There may be a plurality of chips, such as the first chip 100a, the second chip 100b, the third chip 100c, and the fourth chip 100d shown in fig. 1 and fig. 2. The material of the underfill layer 15 may be epoxy. The chip redistributes the mechanical stresses caused by the CTE mismatch between the encapsulating materials through the underfill layer 15.
In a preferred embodiment, as shown in fig. 1, the chip package further includes an interconnection stud 14 connecting the metal base layer 18 and the ground layer in the metal wiring layer 12.
The interconnection column 14 forms an electrical interconnection with the ground layer and the metal base layer 18 on the metal wiring layer 12, and can form an effective electromagnetic shielding effect on signal transmission of the chip package.
In a preferred embodiment, the cross-sectional structure of the conductive wire 20 is a single structure of metal or alloy; or
The cross-sectional structure of the conductive wire 20 is a structure in which the conductive pillar core 20b is covered with a cladding 20 a.
Wherein the cross-sectional structure of the conductive line 20 may consist of a single metal or metal alloy or a semiconductor-metal alloy; the cross-sectional structure of the conductive line 20 may also be any metal-clad single metal or metal alloy or semiconductor-metal alloy structure. For example, the cross-sectional structure of the conductive wire 20 may be a structure in which the conductive pillar core 20b is coated with a cladding layer 20 a; the cladding 20a may be made of a tin-based alloy material, and the conductive pillar core 20b may be made of an alloy material of silver, copper, aluminum, gold, or any combination thereof.
In a second aspect, an embodiment of a method for manufacturing a chip scale package structure with reduced warpage, as shown in fig. 3, includes the following steps:
S1: as shown in fig. 4, a first carrier 10a having a first bonding layer 11a is provided, and a metal wiring layer 12 is prepared on the first bonding layer 11 a.
In the preparation of the metal wiring layer 12, the dielectric layer 12a may be prepared at the same time. The dielectric layer 12a may be a part of the metal wiring layer 12.
S2: as shown in fig. 5, a chip encapsulation layer is prepared on the metal wiring layer 12.
The chip encapsulating layer comprises a chip, a pin interconnection structure 13 and a plastic encapsulating layer 16 encapsulating the chip. There may be a plurality of chips in the chip encapsulation layer, such as the first chip 100a, the second chip 100b, the third chip 100c, and the fourth chip 100d shown in fig. 1 and 2.
In this step, the preparation of the chip encapsulation layer may include the steps of:
s210: manufacturing a bonding pad structure for electrically connecting with a chip on the metal wiring layer;
s220: bonding a chip to the pad structure;
as shown in fig. 5, in the pin interconnection structure 13, the pin 13a of the chip is electrically connected to the pad 13c through the solder ball 13 b;
s230: encapsulating the chip to form a chip encapsulation layer.
The chip packaging layer can be formed by plastic packaging through materials such as epoxy resin, and the chip is packaged and protected, so that the reliability risk is reduced.
As a preferred embodiment, before the step S230, the following steps may be further included:
s221: interconnection studs 14 are fabricated on the metal wiring layer.
The interconnection column is used for communicating the metal wiring layer and the metal base layer in the subsequent steps, and can form effective electromagnetic shielding effect on signal transmission of the chip packaging body. The chip encapsulation layer also encapsulates the interconnect posts 14.
As a preferred embodiment, before the step S230, the following steps may be further included:
s222: the bottom side of the chip is filled with an underfill layer 15.
In this step, the chip encapsulation layer further includes the underfill layer 15. The chip redistributes the mechanical stresses caused by the CTE mismatch between the encapsulating materials through the underfill layer 15.
S3: as shown in fig. 6, a ring-shaped groove 17 is formed on the outer side of the chip in the chip encapsulation layer.
In this step, there may be a plurality of chips, and the annular groove encloses the chip therein. The annular groove may pass through the plastic layer 16, the dielectric layer 12a and the first bonding layer 11 a.
S4: as shown in fig. 7, a conductive line 20 is buried in the annular groove 17.
In this step, the cross-sectional structure of the conductive wire 20 may be composed of a single metal or an alloy metal; the cross-sectional structure of the conductive wire 20 may also be any metal-clad single metal or alloy metal structure. For example, the cross-sectional structure of the conductive wire may be a structure in which the conductive pillar core 20b is coated with a cladding layer 20 a; the cladding 20a may be made of a tin-based alloy material, and the conductive pillar core 20b may be made of an alloy material of silver, copper, aluminum, gold, or any combination thereof.
S5: as shown in fig. 8, the chip encapsulation layer and the conductive line 20 are thinned.
In this step, if the conductive wire is of a structure in which the conductive pillar core 20b is coated with the cladding 20a, the thinning process is controlled to expose the conductive pillar core 20 b. The thinning process may also expose the silicon substrate material of the chip 100 or leave the molding layer 16. If the interconnect posts 14 are present, the thinning process also exposes the interconnect posts 14.
S6: as shown in fig. 9, a metal base layer 18 is prepared to cover the chip encapsulation layer and the conductive line 20.
In this step, the metal base layer 18 may be prepared by magnetron sputtering a metal crystal nucleus layer and an electroplating process. If the interconnection post 14 is present, the metal base layer 18 is conductively interconnected to the interconnection post 14.
S7: as shown in fig. 10, a second carrier 10b having a second bonding layer 11b is prepared, and the second bonding layer 11b is bonded to the metal base layer 18 to obtain a first pre-package structure.
S8: as shown in fig. 11, the first pre-package structure prepared in step S7 is flipped, and the first bonding layer 11a and the first carrier 10a are removed by de-bonding.
S9: as shown in fig. 13, a conductive connection member 23 is formed on the metal wiring layer 12 to form a chip package.
In this step, the chip package includes a chip encapsulating layer, a metal wiring layer, and a conductive connecting member 23. The conductive connection 23 includes a pad and a solder ball, and the solder ball can be formed by depositing a solder bump of tin-based alloy on the pad after a high temperature reflow process.
S10: as shown in fig. 12 and 13, an epitaxial structure 22 extending to the upper surface of the chip package is formed on the conductive line 20 near the chip package, so as to form an encapsulation hoop structure.
In this step, the epitaxial structure may be fabricated by melting and leveling the conductive line near one side of the chip package by a high temperature reflow process. The encapsulation hoop structure comprises a metal base layer positioned at the bottom of the chip packaging body and a conducting wire with an epitaxial structure positioned at the side face of the chip packaging body.
Taking the structure that the conductive wire adopts the cladding 20a made of tin-based alloy material and the conductive column core 20b made of silver material as an example, the cladding 20a on one side of the chip encapsulating layer 16 forms molten metal liquid through a high-temperature reflow process, and after the molten metal liquid fully infiltrates the side wall of the annular groove 17, the molten metal liquid is fully contacted with the chip encapsulating layer 16, and partial tin-based alloy atoms enter the chip encapsulating layer 16 under the high-temperature diffusion effect, so that the molten metal liquid is tightly contacted with the chip encapsulating layer 16. The cladding 20a also forms molten tin-based alloy liquid in the high-temperature reflow process, the tin-based alloy liquid at the edge of the conductive column core 20b overflows under the action of gravity and surface tension to form an epitaxial hemisphere 21 ' of the tin-based alloy liquid, and then the leveling bonding tool 30 is used for melting and flattening the epitaxial hemisphere 21 ', so that the epitaxial hemisphere 21 ' is melted again under the high-temperature action of the leveling bonding tool 30 and is flattened by the leveling bonding tool 30 to form an epitaxial structure 22 with an epitaxial surface 21, and the epitaxial structure covers the dielectric layer 12a on the metal wiring layer 12.
Under the action of high temperature, tin-based alloy atoms diffuse and penetrate into the dielectric layer 12a to form an interfused tight bonding layer between the epitaxial structure 22 and the dielectric layer 12 a. When the chip packaging body is under the action of warping tensile force, the mutually fused tight bonding layers can offset partial or all tensile force, and warping of the chip packaging body can be effectively inhibited. The apparatus for preparing the epitaxial structure 22 is not limited to flattening the horn, and any apparatus that achieves melting and flattening of the cladding 20a can be used in the present invention. In addition, if a leveling horn is used to prepare the epitaxial structure, the cladding 20a should be made of a material (metal and/or metal alloy) having a melting point within the temperature range of the leveling horn.
In addition, as a preferred embodiment, as shown in fig. 12, the leveling bonding tool 30 may include an outlet hole 33 and a leveling base surface 31, the leveling base surface 31 has a heating function, the bonding wire 32 is drawn out from the outlet hole 33, melted by the heating of the leveling base surface 31 and flattened by the smoothing surface of the leveling base surface 31, the flattened bonding wire is covered on the tin-based alloy envelope layer 20a, and the surface metal of the bonding wire in the molten state is diffused and penetrated into the tin-based alloy envelope layer 20a to form alloy bonding therewith.
S11: as shown in fig. 1, the second bonding layer 11b and the second carrier 10b are removed by de-bonding, so as to obtain a first chip package structure M1.
Another embodiment of a method for manufacturing a chip scale package structure with reduced warpage is shown in fig. 14, wherein steps S1-S10 are the same as those in the previous embodiment, and further includes the following steps:
s11: as shown in fig. 15 and 16, the packaging cuff structure is divided along a dividing line 24;
in this step, the division may employ a laser cutting process. This can further reduce the package size of the chip scale package structure. The structure after division still keeps a part of the packaging hoop structure, plays a role of packaging hoop on a three-dimensional space of the chip packaging body and can effectively inhibit thermal warping.
S12: as shown in fig. 17, the second bonding layer 11b and the second carrier 10b are removed by de-bonding, so as to obtain a second chip package structure M2.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
Claims (12)
1. A chip scale package structure with reduced warpage, comprising: the chip packaging structure comprises a metal base layer and a chip packaging body positioned on the metal base layer; and a conductive wire surrounding the chip packaging body is further arranged around the chip packaging body on the metal base layer, and an epitaxial structure extending to the upper surface of the chip packaging body through leveling treatment is arranged on the conductive wire to form an encapsulation hoop structure comprising the metal base layer-conductive wire-epitaxial structure.
2. The chip scale package structure with reduced warpage of claim 1, wherein:
the chip packaging body comprises a chip packaging layer, a metal wiring layer and a conductive connecting piece which are sequentially connected; the metal wiring layer is in contact with the conductive line through a dielectric layer.
3. The chip scale package structure with reduced warpage according to claim 2, wherein:
the chip encapsulating layer comprises a chip electrically connected with the metal wiring layer, and a bottom glue filling layer is filled between the chip and the metal wiring layer.
4. The chip scale package structure with reduced warpage according to claim 2, wherein:
the chip packaging body further comprises an interconnection column which is connected with the metal base layer and the grounding layer in the metal wiring layer.
5. The chip scale package structure with reduced warpage as claimed in claim 1, wherein:
the cross-sectional structure of the conductive wire is a single structure of metal or alloy; or
The cross-sectional structure of the conductive wire is a structure that the cladding wraps the conductive column core.
6. The chip scale package structure with reduced warpage as claimed in claim 5, wherein:
the cladding adopts tin-based alloy, and the conductive column core adopts alloy material of silver, copper, aluminum, gold or any combination thereof.
7. The chip scale package structure with reduced warpage according to claim 5 or 6, wherein:
and the cladding layer is subjected to high-temperature reflow process treatment and leveling treatment to form the epitaxial structure.
8. The chip scale package structure with reduced warpage of claim 1, wherein:
the epitaxial structure is formed by heating and melting the bonding wire and performing the leveling treatment.
9. A preparation method of a chip scale package structure capable of reducing warpage is characterized by comprising the following steps:
providing a first carrier plate with a first bonding layer, preparing a metal wiring layer on the first bonding layer and preparing a chip encapsulating layer;
manufacturing an annular groove on the outer side of the chip in the chip encapsulating layer;
Embedding a conductive wire in the annular groove, and thinning the chip encapsulating layer and the conductive wire;
preparing a metal base layer to cover the chip encapsulating layer and the conductive wire;
preparing a second carrier plate with a second bonding layer, and laminating the second bonding layer on the metal base layer;
removing the first bonding layer and the first carrier plate;
manufacturing a conductive connecting piece on the metal wiring layer to form a chip packaging body;
manufacturing an epitaxial structure extending to the upper surface of the chip packaging body on one side of the conductive wire close to the chip packaging layer through leveling treatment, and forming a packaging hoop structure comprising a metal base layer-conductive wire-epitaxial structure;
and removing the second bonding layer and the second carrier plate.
10. The method of claim 9, wherein the step of manufacturing the chip scale package structure with reduced warpage comprises:
before removing the second bonding layer and the second carrier, further comprising:
segmenting the containment cuff structure.
11. The method for manufacturing a chip scale package structure with reduced warpage according to claim 9 or 10, wherein:
the preparation of the chip encapsulating layer comprises the following steps:
manufacturing a pad structure for electrically connecting with a chip on the metal wiring layer;
Bonding a chip to the pad structure;
encapsulating the chip to form a chip encapsulation layer.
12. The method of claim 11, wherein the step of manufacturing the chip scale package structure with reduced warpage comprises:
before the encapsulating the chip to form a chip encapsulating layer, the method further comprises the following steps:
manufacturing an interconnection column on the metal wiring layer;
thinning the chip encapsulating layer comprises:
and thinning the chip encapsulating layer until the interconnection columns are exposed.
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