CN111081564A - Laminated chip packaging structure and manufacturing method thereof - Google Patents

Laminated chip packaging structure and manufacturing method thereof Download PDF

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Publication number
CN111081564A
CN111081564A CN201911420295.7A CN201911420295A CN111081564A CN 111081564 A CN111081564 A CN 111081564A CN 201911420295 A CN201911420295 A CN 201911420295A CN 111081564 A CN111081564 A CN 111081564A
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conductive
film
electrically connected
holes
chip
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CN201911420295.7A
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Chinese (zh)
Inventor
高晓琛
李秀芳
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Shanghe tanrong new technology development center
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Zibo Vocational Institute
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Priority to CN201911420295.7A priority Critical patent/CN111081564A/en
Publication of CN111081564A publication Critical patent/CN111081564A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a laminated chip packaging structure and a manufacturing method thereof. In addition, the wires arranged in the two films are arranged in different directions, and the included angle is set to be 45-90 degrees, so that the stress difference can be resisted, and the flexible layout of the circuit can be realized.

Description

Laminated chip packaging structure and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor device packaging, belongs to the H01L23/00 classification number, and particularly relates to a laminated chip packaging structure and a manufacturing method thereof.
Background
The existing stacked semiconductor chip packages are often electrically interconnected through redistribution layers to achieve flexible layout of lines and fan-out type leading-out, in most cases, the redistribution layers are formed by depositing alternate dielectric layers and metal layers and patterning, the forming process is complex, defects among multiple layers are more, stress is larger, the whole package structure is easy to deform due to the stress or delaminate between a sealing layer and the redistribution layers, and the package is not favorable.
Disclosure of Invention
Based on the above problem, the present invention provides a method for manufacturing a stacked chip package structure, which comprises the following steps:
(1) providing a carrier plate with an adhesive layer, pressing a first film on the adhesive layer, and wrapping a plurality of first leads which are arranged in parallel along a first direction in the first film;
(2) forming a plurality of first conductive through holes and first conductive blind holes in the first film, wherein the first conductive through holes are respectively electrically connected with the first conductive wires, and the first conductive blind holes enable at least two adjacent first conductive wires to be electrically connected;
(3) welding a first chip on the first film, wherein the first chip is electrically connected with the first lead through the first conductive through hole and/or the first conductive blind hole;
(4) injection molding a sealing layer formed over the first film and sealing the first chip;
(5) forming a plurality of conductive posts in the sealing layer, the conductive posts being electrically connected with the first conductive lines through the first conductive vias and/or the first conductive blind vias;
(6) pressing a second film on the sealing layer, wherein a plurality of second leads which are arranged in parallel along a second direction are wrapped in the second film;
an included angle between the first direction and the second direction is α, wherein the included angle is equal to or more than 45 degrees and equal to or less than α degrees and equal to or less than 90 degrees.
According to the embodiment of the invention, the method further comprises the step (7) of forming a plurality of second conductive through holes and second conductive blind holes in the second film, wherein the second conductive through holes are respectively electrically connected with the second conducting wires, and the second conductive blind holes enable at least two adjacent second conducting wires to be electrically connected; the second conducting wire is electrically connected with the conducting post through the second conducting through hole.
According to the embodiment of the invention, the method further comprises a step (8) of welding a second chip on the second film, wherein the second chip is electrically connected with the second lead through the second conductive through hole and/or the second conductive blind hole.
According to the embodiment of the invention, the method further comprises the step (9) of removing the carrier plate and the bonding layer.
According to an embodiment of the present invention, the method of forming the first film specifically includes: and injection molding and wrapping the first lead by using dual-curing resin in an injection mold, and then carrying out primary curing.
According to an embodiment of the present invention, in the step (1), the method of laminating the first film specifically includes: providing a first film which is subjected to the first curing, laminating the first film on the adhesive layer, and then performing a second curing so that the first film is completely cured.
The invention also provides a laminated chip packaging structure, which is prepared by the manufacturing method of the laminated chip packaging structure and specifically comprises the following steps:
the first film is internally wrapped with a plurality of first wires which are arranged in parallel along a first direction; a plurality of first conductive through holes and first conductive blind holes are formed in the first film, wherein the first conductive through holes are respectively electrically connected with the first wires, and the first conductive blind holes enable at least two adjacent first wires to be electrically connected;
the first chip is welded on the first film and is electrically connected with the first lead through the first conductive through hole and/or the first conductive blind hole;
a sealing layer formed over the first film and sealing the first chip; a plurality of conductive posts are formed in the sealing layer, and the conductive posts are electrically connected with the first conducting wires through the first conductive through holes and/or the first conductive blind holes;
the second film is pressed on the sealing layer and is wrapped with a plurality of second leads which are arranged in parallel along a second direction;
an included angle between the first direction and the second direction is α, wherein the included angle is equal to or more than 45 degrees and equal to or less than α degrees and equal to or less than 90 degrees.
According to the embodiment of the present invention, a plurality of second conductive through holes and second conductive blind holes are formed in the second film, wherein the second conductive through holes are respectively electrically connected to the second conductive lines, and the second conductive blind holes electrically connect at least two adjacent second conductive lines; the second conducting wire is electrically connected with the conducting post through the second conducting through hole.
According to the embodiment of the invention, the second film is provided with a second conductive through hole and/or a second conductive blind hole, and the second conductive through hole and/or the second conductive blind hole are/is electrically connected with the second conductive line.
According to the embodiment of the invention, the main materials of the first film and the second film are dual-cured resin, the dual-cured resin is thermosetting resin or light-cured resin, and the coefficient of thermal expansion of the dual-cured resin is the same as that of the sealing layer.
The invention has the following advantages:
according to the invention, the prefabricated film is used as the redistribution layer, the main material of the film is selected from dual-cured resin, so that simple adhesion during packaging can be realized, the packaging is ensured not to be layered easily, the thermal expansion coefficients of the dual-cured resin and the sealing layer resin are equivalent, the stress difference between layers can be reduced, and layering and warping are further prevented. In addition, the wires arranged in the two films are arranged in different directions, and the included angle is set to be 45-90 degrees, so that the stress difference can be resisted, and the flexible layout of the circuit can be realized.
Drawings
FIG. 1 is a cross-sectional view of a stacked chip package structure according to the present invention;
FIG. 2 is a top view of a first membrane of the present invention;
FIG. 3 is a top view of a second membrane of the present invention; wherein, FIG. 1 is a cross-sectional view taken along line A1A2 in FIG. 2 or along line B1B2 in FIG. 3;
fig. 4-11 are schematic diagrams illustrating a method for manufacturing a stacked chip package structure according to the present invention.
Detailed Description
The laminated chip packaging structure of the invention utilizes the film as the redistribution layer, can be preformed and formed, is convenient for packaging, does not need to deposit a dielectric layer and a metal layer to form the redistribution layer, and adopts dual-curing resin as a main material, thereby realizing the convenience of adhesion and being beneficial to stress balance. Specifically, referring to fig. 1 to 3, the stacked chip package structure of the present invention includes a first film 12, wherein a plurality of first wires 13 arranged in parallel along a first direction are wrapped in the first film 12; a plurality of first conductive through holes 14 and first conductive blind holes 15 are formed in the first film 13, wherein the first conductive through holes 14 are respectively electrically connected with the first conductive wires 13, and the first conductive blind holes 15 enable at least two adjacent first conductive wires 13 to be electrically connected; the first conductive lines 13 may be arranged along the x direction, and the material thereof may be selected from copper, aluminum, and the like.
A first chip 16 is arranged on the first film 12, which can be soldered to the first film 12, for example, by means of solder balls, the first chip 16 being electrically connected to the first conductor line 13 via the first electrically conductive via 14 and/or the first electrically conductive blind hole 15.
A sealing layer 17 is provided on the first film 12, the sealing layer 17 being molded from a resin material and sealing the first chip 16; a plurality of conductive posts 18 are formed in the sealing layer 17, and the conductive posts 18 are electrically connected with the first conductive wires 13 through the first conductive through holes 14 and/or the first conductive blind holes 15; in addition, the conductive posts 18 are located at the peripheral region of the first chip 16.
The packaging structure further comprises a second film 19 which is pressed on the sealing layer 17, a plurality of second conducting wires 20 which are arranged in parallel along a second direction are wrapped in the second film 19, for example, the second conducting wires can be arranged along the y direction, the material of the second conducting wires is the same as that of the first conducting wires, the main materials of the first film 12 and the second film 19 are the same, the first film 12 and the second film 19 are both dual-curing resin, the dual-curing resin is thermosetting resin or light curing resin, the thermal expansion coefficient of the dual-curing resin is the same as that of the sealing layer 17, in order to balance stress of the sealing layer 17, conducting wires in the upper film and the lower film, namely the first film 12 and the second film 19, are arranged along different directions, wherein the included angle between the first direction and the second direction is α, 45 degrees and α degrees is smaller than or equal to 90 degrees, and stress balance can be achieved through the arrangement, and accordingly.
A plurality of second conductive through holes 21 and second conductive blind holes 22 are formed in the second film 19, wherein the second conductive through holes 21 are respectively electrically connected to the second conductive lines 20, and the second conductive blind holes 22 electrically connect at least two adjacent second conductive lines 20; the second conductive line 20 is electrically connected to the conductive pillar 18 through the second conductive via 21.
According to the embodiment of the present invention, the second chip 23 is soldered on the second film 19, and the second chip 23 is electrically connected to the second conductive line 20 through the second conductive via 21 and/or the second conductive blind via 22. The first chip 16 and the second chip 23 may be both bare chips or packaged chips, and functions thereof may be reasonably selected as needed, which is not described herein. A sealing layer 24 is formed on the second film 19, the sealing layer 24 is formed by the same method and material as those of the sealing layer 17, and a conductive post 25 is formed in the sealing layer 24. If desired, a third membrane (not shown) may also be provided thereon, which may be configured to conform to the second membrane.
In addition, the laminated chip packaging structure is also extremely simple, the method can save cost and increase the flexibility of wiring, and the manufacturing method of the laminated chip packaging structure comprises the following steps:
(1) providing a carrier plate with an adhesive layer, pressing a first film on the adhesive layer, and wrapping a plurality of first leads which are arranged in parallel along a first direction in the first film;
(2) forming a plurality of first conductive through holes and first conductive blind holes in the first film, wherein the first conductive through holes are respectively electrically connected with the first conductive wires, and the first conductive blind holes enable at least two adjacent first conductive wires to be electrically connected;
(3) welding a first chip on the first film, wherein the first chip is electrically connected with the first lead through the first conductive through hole and/or the first conductive blind hole;
(4) injection molding a sealing layer formed over the first film and sealing the first chip;
(5) forming a plurality of conductive posts in the sealing layer, the conductive posts being electrically connected with the first conductive lines through the first conductive vias and/or the first conductive blind vias;
(6) pressing a second film on the sealing layer, wherein a plurality of second leads which are arranged in parallel along a second direction are wrapped in the second film;
an included angle between the first direction and the second direction is α, wherein the included angle is equal to or more than 45 degrees and equal to or less than α degrees and equal to or less than 90 degrees.
According to the embodiment of the invention, the method further comprises the step (7) of forming a plurality of second conductive through holes and second conductive blind holes in the second film, wherein the second conductive through holes are respectively electrically connected with the second conducting wires, and the second conductive blind holes enable at least two adjacent second conducting wires to be electrically connected; the second conducting wire is electrically connected with the conducting post through the second conducting through hole.
According to the embodiment of the invention, the method further comprises a step (8) of welding a second chip on the second film, wherein the second chip is electrically connected with the second lead through the second conductive through hole and/or the second conductive blind hole.
According to the embodiment of the invention, the method further comprises the step (9) of removing the carrier plate and the bonding layer.
According to an embodiment of the present invention, the method of forming the first film specifically includes: and injection molding and wrapping the first lead by using dual-curing resin in an injection mold, and then carrying out primary curing.
According to an embodiment of the present invention, in the step (1), the method of laminating the first film specifically includes: providing a first film which is subjected to the first curing, laminating the first film on the adhesive layer, and then performing a second curing so that the first film is completely cured.
The method for manufacturing the stacked chip package structure provided by the present invention is described in detail below with reference to fig. 4 to 11.
First, the first film 12 and the second film 19 are prefabricated: the method comprises the steps of preventing a plurality of wires which are arranged in parallel in a forming die, filling the forming die with dual-curing resin to coat the wires, and then carrying out first heating or illumination curing to form a pre-curing film.
Referring to fig. 4, a carrier 10 and an adhesive layer 11 are provided, and the adhesive layer 11 may be a release layer. Pressing a first film 12 onto the adhesive layer 11, so that a plurality of first wires 13 wrapped in the first film 12 are arranged in parallel along a first direction; the method for pressing the first film 12 specifically includes: providing the first film 12 having completed the first curing, pressing the first film 12 on the adhesive layer 11, and then performing a second curing so that the first film 12 is completely cured.
Referring to fig. 5, a plurality of first conductive through holes 14 and first conductive blind holes 15 are opened or grooved in the first film 12 and filled with a conductive resin to form the first conductive through holes 14 and the first conductive blind holes 15, wherein the first conductive through holes 14 are electrically connected to the first conductive lines 13, respectively, and the first conductive blind holes 15 electrically connect at least two adjacent first conductive lines 13. Wherein the conductive resin is a resin material mixed with conductive particles, which has conductivity.
Referring to fig. 6, a first chip 16 is bonded on the first film 12, and the first chip 16 is electrically connected to the first conductive line 13 through the first conductive via 14 and/or the first conductive blind via 15. A sealing layer 17 is then formed using a conventional injection molding process, the sealing layer 17 being formed over the first film 12 and sealing the first chip 16.
Referring to fig. 7, a plurality of conductive posts 18 are formed by opening and filling a conductive resin in the sealing layer 17, and the conductive posts 18 are electrically connected to the first conductive lines 13 through the first conductive through holes 14 and/or the first conductive blind holes 15. Wherein the conductive pillar 18 is located around the first chip 16 and penetrates through the sealing layer 17.
Referring to fig. 8, a second film 19 is pressed on the sealing layer 17 and is cured for the second time, so that the second film 19 is completely cured, and a plurality of second conducting wires 20 arranged in parallel along a second direction are wrapped in the second film 19, wherein an included angle between the first direction and the second direction is α, and 45 degrees to α degrees is 90 degrees.
Referring to fig. 9, a plurality of second conductive through holes 21 and second conductive blind holes 22 are formed in the second film 19, wherein the second conductive through holes 21 are respectively electrically connected to the second conductive lines 20, and the second conductive blind holes 22 electrically connect at least two adjacent second conductive lines 20; the second conductive line 20 is electrically connected to the conductive pillar 18 through the second conductive via 21.
Referring to fig. 10, a second chip 23 is bonded on the second film 19, and the second chip 23 is electrically connected to the second conductive line 20 through the second conductive via 21 and/or the second conductive blind via 22. Then, a sealing layer 24 is formed on the second film 19, the sealing layer 24 seals the second chip 23, and the sealing layer 24 and the sealing layer 17 are made of the same material.
Referring to fig. 11, a conductive resin is opened and filled in the sealing layer 24 to form a conductive pillar 25, and the conductive pillar 25 is electrically connected to the second conductive line 20 through the second conductive via 21 and/or the second conductive blind via 22. Of course, subsequently, further layers may be formed as desired, such as continuing to form a third film and a third chip structure on sealing layer 24, and so on.
Finally, the carrier 10 and the adhesive layer 11 are removed, and the package structure shown in fig. 1 is obtained.
The multilayer film RF radio frequency device manufactured by the method is an all-plastic sealing and welding-free packaging structure, and has at least two film structures, wherein the at least two film structures are resin films which are molded in advance and are matched with the material of a sealing layer, so that stress balance is realized, and warping and layering are prevented; in addition, the multilayer film structure has universality in industry, can be formed in advance, simplifies the packaging structure, saves materials, and does not need any welding processes such as welding wires or welding balls.
In addition, referring to fig. 8, the multilayer film RF device of the present invention may further include a third film 19, which is substantially similar in structure to that described above, except that it is interconnected differently. In the present embodiment, the third film 19 has an electromagnetic shielding net 20 therein, the first chip 16 is located directly above the electromagnetic shielding net 20, and the first to third films have a third conductive through hole 21 and a fourth conductive through hole 22 therein, wherein the third conductive through hole 21 extends through the third film 19 and the second film 5 into the first film 3, and the third conductive through hole 21 electrically connects the plurality of wires 6 and the inductor coil 4, and the fourth conductive through hole 22 extends through the third film 19 into the second film 5 only, and electrically connects the plurality of wires 6. In the present embodiment, interference of the inductor coil with the chip 12 can be prevented due to the electromagnetic shield layer 20.
According to the invention, the prefabricated film is used as the redistribution layer, the main material of the film is selected from dual-cured resin, so that simple adhesion during packaging can be realized, the packaging is ensured not to be layered easily, the thermal expansion coefficients of the dual-cured resin and the sealing layer resin are equivalent, the stress difference between layers can be reduced, and layering and warping are further prevented. In addition, the wires arranged in the two films are arranged in different directions, and the included angle is set to be 45-90 degrees, so that the stress difference can be resisted, and the flexible layout of the circuit can be realized.
The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to the other example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.

Claims (10)

1. A manufacturing method of a laminated chip packaging structure comprises the following steps:
(1) providing a carrier plate with an adhesive layer, pressing a first film on the adhesive layer, and wrapping a plurality of first leads which are arranged in parallel along a first direction in the first film;
(2) forming a plurality of first conductive through holes and first conductive blind holes in the first film, wherein the first conductive through holes are respectively electrically connected with the first conductive wires, and the first conductive blind holes enable at least two adjacent first conductive wires to be electrically connected;
(3) welding a first chip on the first film, wherein the first chip is electrically connected with the first lead through the first conductive through hole and/or the first conductive blind hole;
(4) injection molding a sealing layer formed over the first film and sealing the first chip;
(5) forming a plurality of conductive posts in the sealing layer, the conductive posts being electrically connected with the first conductive lines through the first conductive vias and/or the first conductive blind vias;
(6) pressing a second film on the sealing layer, wherein a plurality of second leads which are arranged in parallel along a second direction are wrapped in the second film;
the angle between the first direction and the second direction is α, wherein α is more than or equal to 45 degrees and less than or equal to 90 degrees.
2. The method of manufacturing a stacked chip package structure according to claim 1, wherein: a step (7) of forming a plurality of second conductive through holes and second conductive blind holes in the second film, wherein the second conductive through holes are electrically connected to the second conductive lines, respectively, and the second conductive blind holes electrically connect at least two adjacent second conductive lines; the second conducting wire is electrically connected with the conducting post through the second conducting through hole.
3. The method of manufacturing a stacked chip package structure according to claim 2, wherein: and (8) welding a second chip on the second film, wherein the second chip is electrically connected with the second lead through the second conductive through hole and/or the second conductive blind hole.
4. The method of manufacturing a stacked chip package structure according to claim 3, wherein: the method further comprises the step (9) of removing the carrier plate and the bonding layer.
5. The method of manufacturing a stacked chip package structure according to claim 1, wherein: the method of forming the first film specifically includes: and injection molding and wrapping the first lead by using dual-curing resin in an injection mold, and then carrying out primary curing.
6. The method of manufacturing a stacked chip package structure according to claim 5, wherein: in the step (1), the method for laminating the first film specifically includes: providing a first film which is subjected to the first curing, laminating the first film on the adhesive layer, and then performing a second curing so that the first film is completely cured.
7. A stacked chip packaging structure prepared by the manufacturing method of the stacked chip packaging structure of any one of claims 1-6, specifically comprising:
the first film is internally wrapped with a plurality of first wires which are arranged in parallel along a first direction; a plurality of first conductive through holes and first conductive blind holes are formed in the first film, wherein the first conductive through holes are respectively electrically connected with the first wires, and the first conductive blind holes enable at least two adjacent first wires to be electrically connected;
the first chip is welded on the first film and is electrically connected with the first lead through the first conductive through hole and/or the first conductive blind hole;
a sealing layer formed over the first film and sealing the first chip; a plurality of conductive posts are formed in the sealing layer, and the conductive posts are electrically connected with the first conducting wires through the first conductive through holes and/or the first conductive blind holes;
the second film is pressed on the sealing layer and is wrapped with a plurality of second leads which are arranged in parallel along a second direction;
the angle between the first direction and the second direction is α, wherein α is more than or equal to 45 degrees and less than or equal to 90 degrees.
8. The stacked chip package structure of claim 7, wherein: a plurality of second conductive through holes and second conductive blind holes are formed in the second film, wherein the second conductive through holes are respectively electrically connected with the second wires, and the second conductive blind holes enable at least two adjacent second wires to be electrically connected; the second conducting wire is electrically connected with the conducting post through the second conducting through hole.
9. The stacked chip package structure of claim 7, wherein: the second chip is welded on the second membrane and is electrically connected with the second lead through the second conductive through hole and/or the second conductive blind hole.
10. The stacked chip package structure of claim 7, wherein: the main materials of the first film and the second film are dual-cured resin, the dual-cured resin is thermosetting resin or light-cured resin, and the thermal expansion coefficient of the dual-cured resin is the same as that of the sealing layer.
CN201911420295.7A 2019-12-31 2019-12-31 Laminated chip packaging structure and manufacturing method thereof Withdrawn CN111081564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911420295.7A CN111081564A (en) 2019-12-31 2019-12-31 Laminated chip packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911420295.7A CN111081564A (en) 2019-12-31 2019-12-31 Laminated chip packaging structure and manufacturing method thereof

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Publication Number Publication Date
CN111081564A true CN111081564A (en) 2020-04-28

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111490019A (en) * 2020-04-24 2020-08-04 济南南知信息科技有限公司 Integrated circuit structure and manufacturing method thereof
CN114420676A (en) * 2022-03-31 2022-04-29 长电集成电路(绍兴)有限公司 Chip-scale packaging structure capable of reducing warpage and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111490019A (en) * 2020-04-24 2020-08-04 济南南知信息科技有限公司 Integrated circuit structure and manufacturing method thereof
CN111490019B (en) * 2020-04-24 2022-01-07 天津恒立远大仪表股份有限公司 Integrated circuit structure and manufacturing method thereof
CN114420676A (en) * 2022-03-31 2022-04-29 长电集成电路(绍兴)有限公司 Chip-scale packaging structure capable of reducing warpage and preparation method thereof
CN114420676B (en) * 2022-03-31 2022-06-14 长电集成电路(绍兴)有限公司 Chip-scale packaging structure capable of reducing warpage and preparation method thereof

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