CN114336875B - Current demodulation circuit for wireless charging - Google Patents
Current demodulation circuit for wireless charging Download PDFInfo
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- CN114336875B CN114336875B CN202210003039.3A CN202210003039A CN114336875B CN 114336875 B CN114336875 B CN 114336875B CN 202210003039 A CN202210003039 A CN 202210003039A CN 114336875 B CN114336875 B CN 114336875B
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- 238000005070 sampling Methods 0.000 claims description 36
- 230000005540 biological transmission Effects 0.000 claims description 14
- 238000001914 filtration Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
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- 230000001105 regulatory effect Effects 0.000 claims description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
The invention belongs to the technical field of wireless charging, and particularly relates to a current demodulation circuit for wireless charging. The invention aims to reduce the capacitance value and thus the area of a chip, mainly adjusts the time constant of a filter circuit through a pulse signal generator, and increases the time constant to the value by setting the output duty ratio D of the pulse signal generatorThe double of the capacitor is realized, so that the purpose of reducing the capacitance is realized, and the area of the chip is further reduced.
Description
Technical Field
The invention belongs to the technical field of wireless charging, and particularly relates to a current demodulation circuit for wireless charging.
Background
Most of the wireless charging of mobile phones in the market currently adopts the scheme shown in fig. 1 for charging. I.e., the wireless charging base Transimitter (Tx) charges the cellular phone Receiver (Rx) through the coupling coil. Then Tx knows how much power is transferred to Rx, that is, how much charge current is supplied to Rx. Rx must send information to Tx to let Tx transmit the proper power. The path of the Rx transmission information is as follows: when Rx requires more energy, then the Controller in the mobile phone opens the modulation tubes M25 and M26 in the Rx at the same time, so that the modulation capacitors Cm1 and Cm2 are inserted into the Ls and Cs resonant circuits in the Rx, after the insertion of Cm1 and Cm2, the impedance characteristics of the Ls and Cs resonant circuits in the Rx are changed, so as to cause the change of the Ls Current, then the inductance Current of Lp in the Tx is changed through the coupling effect, the Current Snse circuit in the Tx samples the Current of the coupling inductance Lp through the rectifying tubes M13 and M14, and the sampled signal is sent to the Demodulation module in the Tx, and then the Demodulation module sends the demodulated signal to the Controller (tx_control) in the Tx, and then the tx_control adjusts the frequency and the duty ratio of the PWM1 and the PWM2 in the Tx to adjust the transmission power. Typically the frequency of the M25 and M26 adjustments inside Rx is a 2KHz square wave. The frequencies of the PWM1 and PWM2 signals in Tx are typically between 100kHz and 200kHz.
As shown in fig. 2 and 3, are typical peak current and valley current demodulation circuits, respectively. From fig. 1, it is known that the signal to be demodulated is a 2kHz frequency, and in order to be able to demodulate normally, R1 and C1 form a filter network that needs to filter out the 100kHz signal, and R2 and C2 need to filter out the 2kHz frequency. Usually, for better filtering effect, the cut-off frequency of a filtering network formed by R1 and C1 is set at 5kHz; the cut-off frequency of the filter network formed by R2 and C2 will be around 100 Hz. Since the system has limitation on the current demodulation depth, namely the minimum current variable quantity which can be demodulated is about 20mA, and the corresponding filter network has only a few mV variable quantity, in order to reduce the influence of voltage drop generated by electric leakage on the resistor on demodulation, the R1 and R2 resistors can not exceed 10Mohm, and therefore, the calculation can be realized: the capacitance of C1 is about 10pF, and the capacitance of C2 may be about 200pF, so that there is a problem that the capacitance of C2 is too large and the occupied area is too large.
Disclosure of Invention
The present invention is directed to the above-described problems, and proposes a current demodulation circuit for wireless charging that can reduce the capacitance of C2 and the area of a chip.
The technical scheme of the invention is as follows:
the current demodulation circuit for wireless charging comprises a sampling circuit, a source electrode follower, a first-stage filter circuit, a second-stage filter circuit and a comparator, wherein the sampling circuit is used for sampling the coupling inductance current of a transmitting end in a wireless charging system, the output of the sampling circuit passes through the source electrode follower and then passes through the first-stage filter circuit to be connected to the positive input end of the comparator, the output of the sampling circuit also passes through the first-stage filter circuit and the second-stage filter circuit to be connected to the negative input end of the comparator, and the comparator outputs a demodulated signal; the circuit is characterized by further comprising an adjusting circuit between the first-stage filter circuit and the second-stage filter circuit, wherein the adjusting circuit comprises a transmission gate, an inverter and a pulse signal generator, the input end of the transmission gate is connected with the output end of the first-stage filter circuit, the output end of the transmission gate is connected with the input end of the second-stage filter circuit, the first control end of the transmission gate is connected with the output end of the pulse signal generator, and the second control end of the transmission gate is connected with the output end of the inverter; the input end of the inverter is connected with the output end of the pulse signal generator, and the other end of the pulse signal generator is grounded; defining the output duty cycle of the pulse signal transmitter as D, the regulating circuit is used for increasing the time constant of the second-stage filter circuit to beMultiple times.
Further, the sampling circuit is a peak value sampling circuit.
Further, the sampling circuit comprises an NMOS tube, a first current source and a capacitor; the grid electrode of the NMOS tube is connected with a current sampling signal, the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a first current source and one end of a capacitor, and the output end of the first current source and the other end of the capacitor are grounded; the connection point of the NMOS tube source electrode, the first current source and the capacitor is the output end of the sampling circuit.
Further, the source follower comprises a PMOS tube and a second current source; the input end of the second current source is connected with the power supply, the output end of the second current source is connected with the source electrode of the PMOS tube, the grid electrode of the PMOS tube is connected with the output end of the sampling circuit, the drain electrode of the PMOS tube is grounded, and the connection point of the source electrode of the PMOS tube and the second current source is the output end of the source follower.
Further, the sampling circuit is a valley sampling circuit.
Further, the sampling circuit comprises a PMOS tube, a first current source and a capacitor; the grid electrode of the PMOS tube is connected with a current sampling signal, the drain electrode of the PMOS tube is grounded, the source electrode of the PMOS tube is connected with the output end of the first current source and one end of the capacitor, the input end of the first current source is connected with a power supply, and the other end of the capacitor is grounded; the connection point of the PMOS tube source electrode, the first current source and the capacitor is the output end of the sampling circuit.
Further, the source follower comprises an NMOS tube and a second current source; the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a second current source, the output end of the second current source is connected with the output end of the sampling circuit, and the connection point of the source electrode of the NMOS tube and the second current source is the output end of a source follower.
Further, the first-stage filter circuit is an RC filter circuit and is used for filtering signals with the frequency of more than or equal to 100 kHz; the second-stage filter circuit is an RC filter circuit and is used for filtering signals with the frequency of more than or equal to 2 kHz.
Further, the output duty cycle d=5% of the pulse signal transmitter.
The beneficial effects of the invention are as follows: on the premise of meeting the current demodulation requirement, the capacitance of C2 can be reduced, so that the area of the chip is reduced.
Drawings
Fig. 1 is a schematic diagram of wireless charging of a mobile phone.
Fig. 2 is a typical peak current demodulation circuit.
Fig. 3 is a typical valley current demodulation circuit.
Fig. 4 is a core schematic diagram of the current demodulation circuit of the present invention.
Fig. 5 is a circuit diagram of peak current demodulation according to the present invention.
Fig. 6 is a schematic diagram of a valley current demodulation circuit according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
The principle of the invention is shown in fig. 4, and the small signal formula is deduced as follows:
a. when the transmission gate is opened
b. When the transmission gate is closed
Vout＝0
Overview:
the average value of Vout in one cycle is then:
therefore, the transfer function of the circuit is
Due to duty cycle 0<D<1, so the structure realizes RC filteringThe time constant of the circuit is increased toMultiple times. For example, when the duty ratio=5%, the RC time constant in the current demodulation circuit can be multiplied by 20 times, so that the purpose of reducing the capacitance C2 can be achieved.
As shown in fig. 3, is a typical peak current demodulation circuit. As can be seen from fig. 1, the signal to be demodulated is a 2kHz frequency, and in order to be able to demodulate normally, R1 and C1 form a filter network, which needs to filter out the 100kHz signal, and R2 and C2 need to filter out the 2kHz frequency. Usually, for better filtering effect, the cut-off frequency of a filtering network formed by R1 and C1 is set at 5kHz; the cut-off frequency of the filter network formed by R2 and C2 will be around 100 Hz. Since the system generally has a limitation on the current demodulation depth, namely the minimum current variable quantity which can be demodulated is generally about 20mA, and the corresponding filter network has a variable quantity of only a few mV, in order to reduce the influence of voltage drop generated by electric leakage on the resistor on demodulation, the R1 and R2 resistors generally cannot exceed 10Mohm, and therefore, the calculation can be known that: the capacitance of C1 is probably around 10pF, whereas the capacitance of C2 may be around 200 pF. The capacitance of C2 is too large and the area occupied is too large.
Fig. 5 shows an optimized peak current demodulation circuit, where an NMOS transistor MN1, a current source I1, and a capacitor Cpeak form a peak sampling circuit; the PMOS tubes MP1 and I2 form a source follower, a certain driving capacity is mainly provided for the later stage, R1 and C1 form a first stage filter network, and frequencies of 100kHz and above are filtered; r2 and C2 form a second stage filter circuit, and mainly filter out frequencies of 2kHz and above. The two filtered signals are fed to a comparator Comp1 for comparison, so that a demodulated signal d_dmod can be obtained.
Fig. 6 is an optimized valley current demodulation circuit, where the PMOS transistor MP1, the current source I1, and the capacitor cvaly form a valley sampling circuit; NMOS tubes MN1 and I2 form a source follower, a certain driving capacity is mainly provided for a later stage, R1 and C1 form a first stage filter network, and frequencies of 100kHz and above are filtered; r2 and C2 form a second stage filter circuit, and mainly filter out frequencies of 2kHz and above. The two filtered signals are fed to a comparator Comp1 for comparison, so that a demodulated signal d_dmod can be obtained.
Claims (9)
1. The current demodulation circuit for wireless charging comprises a sampling circuit, a source electrode follower, a first-stage filter circuit, a second-stage filter circuit and a comparator, wherein the sampling circuit is used for sampling the coupling inductance current of a transmitting end in a wireless charging system, the output of the sampling circuit passes through the source electrode follower and then passes through the first-stage filter circuit to be connected to the positive input end of the comparator, the output of the sampling circuit also passes through the first-stage filter circuit and the second-stage filter circuit to be connected to the negative input end of the comparator, and the comparator outputs a demodulated signal; the circuit is characterized by further comprising an adjusting circuit between the first-stage filter circuit and the second-stage filter circuit, wherein the adjusting circuit comprises a transmission gate, an inverter and a pulse signal generator, the input end of the transmission gate is connected with the output end of the first-stage filter circuit, the output end of the transmission gate is connected with the input end of the second-stage filter circuit, the first control end of the transmission gate is connected with the output end of the pulse signal generator, and the second control end of the transmission gate is connected with the output end of the inverter; the input end of the inverter is connected with the output end of the pulse signal generator, and the other end of the pulse signal generator is grounded; defining the output duty cycle of the pulse signal transmitter as D, the regulating circuit is used for increasing the time constant of the second-stage filter circuit to beMultiple times.
2. The current demodulation circuit for wireless charging of claim 1, wherein the sampling circuit is a peak sampling circuit.
3. The current demodulation circuit for wireless charging according to claim 2, wherein the sampling circuit comprises an NMOS tube, a first current source, and a capacitor; the grid electrode of the NMOS tube is connected with a current sampling signal, the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a first current source and one end of a capacitor, and the output end of the first current source and the other end of the capacitor are grounded; the connection point of the NMOS tube source electrode, the first current source and the capacitor is the output end of the sampling circuit.
4. A current demodulation circuit for wireless charging according to claim 3, wherein the source follower comprises a PMOS tube and a second current source; the input end of the second current source is connected with the power supply, the output end of the second current source is connected with the source electrode of the PMOS tube, the grid electrode of the PMOS tube is connected with the output end of the sampling circuit, the drain electrode of the PMOS tube is grounded, and the connection point of the source electrode of the PMOS tube and the second current source is the output end of the source follower.
5. The current demodulation circuit for wireless charging of claim 1, wherein the sampling circuit is a valley sampling circuit.
6. The current demodulation circuit for wireless charging according to claim 5, wherein the sampling circuit comprises a PMOS tube, a first current source, and a capacitor; the grid electrode of the PMOS tube is connected with a current sampling signal, the drain electrode of the PMOS tube is grounded, the source electrode of the PMOS tube is connected with the output end of the first current source and one end of the capacitor, the input end of the first current source is connected with a power supply, and the other end of the capacitor is grounded; the connection point of the PMOS tube source electrode, the first current source and the capacitor is the output end of the sampling circuit.
7. The current demodulation circuit for wireless charging of claim 6, wherein the source follower comprises an NMOS transistor and a second current source; the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a second current source, the output end of the second current source is connected with the output end of the sampling circuit, and the connection point of the source electrode of the NMOS tube and the second current source is the output end of a source follower.
8. The current demodulation circuit for wireless charging according to any one of claims 1 to 7, wherein the first stage filter circuit is an RC filter circuit for filtering signals with a frequency greater than or equal to 100 kHz; the second-stage filter circuit is an RC filter circuit and is used for filtering signals with the frequency of more than or equal to 2 kHz.
9. A current demodulation circuit for wireless charging according to claim 8, wherein the output duty cycle D = 5% of the pulse signal transmitter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210003039.3A CN114336875B (en) | 2022-01-04 | 2022-01-04 | Current demodulation circuit for wireless charging |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210003039.3A CN114336875B (en) | 2022-01-04 | 2022-01-04 | Current demodulation circuit for wireless charging |
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| CN114336875A CN114336875A (en) | 2022-04-12 |
| CN114336875B true CN114336875B (en) | 2023-10-27 |
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| CN202210003039.3A Active CN114336875B (en) | 2022-01-04 | 2022-01-04 | Current demodulation circuit for wireless charging |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0484568A (en) * | 1990-07-27 | 1992-03-17 | New Japan Radio Co Ltd | Vertical synchronizing signal separator circuit |
| US6597238B1 (en) * | 1999-04-22 | 2003-07-22 | Matsushita Electric Industrial Co., Ltd | Demodulating circuit of wireless receiving apparatus and demodulating method |
| CN1744442A (en) * | 2004-08-30 | 2006-03-08 | 三洋电机株式会社 | Digital to analog converter |
| CN112202231A (en) * | 2020-12-09 | 2021-01-08 | 上海南芯半导体科技有限公司 | Wireless charging demodulation circuit |
| CN112311329A (en) * | 2019-12-21 | 2021-02-02 | 成都华微电子科技有限公司 | Low-power-consumption crystal oscillator circuit capable of starting oscillation rapidly |
-
2022
- 2022-01-04 CN CN202210003039.3A patent/CN114336875B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0484568A (en) * | 1990-07-27 | 1992-03-17 | New Japan Radio Co Ltd | Vertical synchronizing signal separator circuit |
| US6597238B1 (en) * | 1999-04-22 | 2003-07-22 | Matsushita Electric Industrial Co., Ltd | Demodulating circuit of wireless receiving apparatus and demodulating method |
| CN1744442A (en) * | 2004-08-30 | 2006-03-08 | 三洋电机株式会社 | Digital to analog converter |
| CN112311329A (en) * | 2019-12-21 | 2021-02-02 | 成都华微电子科技有限公司 | Low-power-consumption crystal oscillator circuit capable of starting oscillation rapidly |
| CN112202231A (en) * | 2020-12-09 | 2021-01-08 | 上海南芯半导体科技有限公司 | Wireless charging demodulation circuit |
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| CN114336875A (en) | 2022-04-12 |
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