CN112202231A

CN112202231A - Wireless charging demodulation circuit

Info

Publication number: CN112202231A
Application number: CN202011424820.5A
Authority: CN
Inventors: 曹灿华
Original assignee: Southchip Semiconductor Technology Shanghai Co Ltd
Current assignee: Shanghai Southchip Semiconductor Technology Co Ltd
Priority date: 2020-12-09
Filing date: 2020-12-09
Publication date: 2021-01-08
Anticipated expiration: 2040-12-09
Also published as: CN112202231B

Abstract

A sampling module is used for sampling inductive current of a charging base in a wireless charging system and converting the inductive current into corresponding voltage signals, an amplifying module receives the voltage signals output by the sampling module and amplifies the voltage signals by a band-pass structure to obtain output current, a processing module processes the current signals output by the amplifying module to obtain one or more of average current, peak current and valley current, and a demodulating module demodulates the current signals output by the processing module. According to the invention, peak current demodulation and valley current demodulation are added, so that normal demodulation can be ensured under the condition of light load; the amplifying module adopts a band-pass structure, so that the problem of swing amplitude during current amplification can be solved, and normal demodulation of peak current demodulation and valley current demodulation can be ensured when the current changes greatly before and after demodulation; in addition, a time division multiplexing mode is adopted for processing when multiple demodulation schemes are used together, so that the chip area and the power consumption are reduced.

Description

Wireless charging demodulation circuit

Technical Field

The invention belongs to the technical field of wireless charging, and relates to a novel wireless charging demodulation circuit.

Background

At present, most wireless charging is performed by adopting an electromagnetic induction principle, as shown in fig. 1, a circuit diagram for realizing the wireless charging system is shown, coils are respectively arranged in a charging base (transmitter) and a mobile phone terminal (Receiver), and a transmitting coil of the charging base generates a certain current in a receiving coil of the mobile phone through electromagnetic induction based on a certain frequency alternating current, so that energy is transferred from the transmitting end of the base to a receiving end of the mobile phone, and the charging base starts to supply power to the mobile phone.

The energy required to be transmitted by the base is controlled by a related instruction sent by the mobile phone, as shown in fig. 1, the mobile phone Controller pulls down the capacitors Cm1 and Cm2 by turning on the switching tubes M25 and M26, so as to change the impedance characteristic of the mobile phone end, cause the change of the Ls inductive current of the mobile phone, affect the Lp inductive current of the coil in the base in an electromagnetic induction mode, a current sampling circuit in the base samples the inductive current of the base, send the sampled current signal to a Demodulation module (Demodulation) for Demodulation, send the successfully demodulated signal to a base Controller, and the base Controller controls the energy transmitted to the mobile phone by generating a first pulse width modulation signal PWM1 and a second pulse width modulation signal PWM2 with different frequencies and different duty ratios.

The current demodulation scheme mostly adopts an average voltage and average current demodulation method, however, the method has the obvious defect that demodulation failure is easy to occur when the load is small. As shown in fig. 2, a schematic diagram of the inductor current IL before and after modulation and the average current demodulation result Iaverge _ DM under the condition of space-time load by using the average current demodulation scheme is shown, and it is obvious that the inductor current IL is zero before and after the average current demodulation and Iaverge _ DM is demodulated, and the demodulation cannot be normally demodulated, which results in demodulation failure. In addition, when the demodulation module demodulates the inductive current, the inductive current is usually sampled and then amplified, but the existing current amplifier is generally equivalent to a low-pass structure, a signal DC point after amplification changes with load current, and when the load current is large, the DC point may be relatively close to a power supply voltage VDD, so that the peak current before and after demodulation does not change (because the peak current reaches the maximum output voltage range), and thus demodulation failure is caused.

Disclosure of Invention

Aiming at the problem of demodulation failure in the traditional current demodulation scheme, the invention provides a wireless charging demodulation circuit, which introduces peak current demodulation and valley current demodulation and solves the problem that average current demodulation is easy to fail under the no-load condition; in addition, the amplifying module adopts a band-pass voltage amplifier to process voltage signals converted by the inductive current, so that the swing amplitude problem during current amplification is solved, the central point of the output current ILsns _ out of the amplifying module is still close to 1/2VDD when the load current is large, the upper swing amplitude and the lower swing amplitude of the amplifying module are ensured to be equal as much as possible, and the normal demodulation of the peak current and the valley current can be ensured even if the current changes greatly before and after demodulation.

The technical scheme of the invention is as follows:

a wireless charging demodulation circuit comprises a charging base and a terminal, wherein inductance coils are respectively arranged in the charging base, the charging base comprises two switch control branches which are respectively controlled by a first pulse width modulation signal and a second pulse width modulation signal, and the inductance coils of the charging base are connected between the output ends of the two switch control branches;

the demodulation circuit comprises a sampling module, an amplifying module, a processing module and a demodulation module, wherein the sampling module is used for sampling the inductive current of a charging base in the wireless charging system and converting the inductive current into a corresponding voltage signal to be connected to the input end of the amplifying module;

the amplifying module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a first current source, a second current source, a first NPN triode, a second NPN triode, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a third PMOS tube,

the grid drain of the fourth NMOS tube is in short circuit and is connected with the output end of the amplifying module after passing through a fourth resistor, and the source electrode of the fourth NMOS tube is grounded;

the base electrode and the collector electrode of the first NPN type triode are connected with the base electrode of the second NPN type triode and are connected with power voltage through a first current source, and the emitter electrode of the first NPN type triode is used as the input end of the amplification module after passing through the first resistor;

the grid electrode of the first NMOS tube is connected with the collector electrode of the second NPN type triode and is connected with power voltage through a second current source, the source electrode of the first NMOS tube is connected with the emitter electrode of the second NPN type triode and is grounded through a second resistor, and the drain electrode of the first NMOS tube is connected with one end of a third resistor, the grid electrode of a third PMOS tube, the grid electrode of the first PMOS tube and the drain electrode of the third PMOS tube;

the grid electrode of the second PMOS tube is connected with the other end of the third resistor and is connected with power supply voltage after passing through the first capacitor, the source electrode of the second PMOS tube is connected with the source electrodes of the first PMOS tube and the third PMOS tube and is connected with the power supply voltage, and the drain electrode of the second PMOS tube is connected with the grid electrode and the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube;

the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube and is connected with the output end of the amplification module, and the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube and is grounded;

the processing module is used for processing the current signal output by the output end of the amplifying module to obtain one or more of average current, peak current and valley current of the current signal output by the amplifying module;

the demodulation module demodulates the current signal output by the processing module to obtain an output signal of the demodulation circuit.

Specifically, the processing module comprises a third current source, a fourth current source, a second capacitor, a fifth NMOS transistor and a fourth PMOS transistor, wherein a gate of the fifth NMOS transistor is connected to the output end of the amplifying module, a drain of the fifth NMOS transistor is connected to the power supply voltage, and a source of the fifth NMOS transistor is connected to a gate of the fourth PMOS transistor, grounded after passing through the second capacitor and grounded after passing through the third current source respectively; the drain electrode of the fourth PMOS tube is grounded, and the source electrode of the fourth PMOS tube outputs the peak current of the current signal output by the amplification module and is connected with the power supply voltage after passing through the fourth current source.

Specifically, the processing module comprises a fifth current source, a sixth current source, a third capacitor, a sixth NMOS tube and a fifth PMOS tube, wherein the gate of the fifth PMOS tube is connected to the output end of the amplifying module, the drain of the fifth PMOS tube is grounded, and the source of the fifth PMOS tube is connected to the gate of the sixth NMOS tube, grounded through the third capacitor and connected to the supply voltage through the fifth current source; the drain electrode of the sixth NMOS tube is connected with the power supply voltage, and the source electrode of the sixth NMOS tube outputs valley current of the current signal output by the amplification module and is grounded after passing through the sixth current source.

Specifically, the processing module includes an RC low-pass filter, and the average current of the current signal output by the amplifying module is obtained after the current signal passes through the RC low-pass filter.

Specifically, the demodulation module comprises a multiplexer, a fourth capacitor, a fifth capacitor, a seventh resistor, an eighth resistor and a comparator,

the input signal of the multiplexer comprises the average current, the peak current and the valley current of the current signal output by the amplifying module, and the output end of the multiplexer is connected with one end of a seventh resistor;

one end of the eighth resistor is connected with the other end of the seventh resistor and the positive input end of the comparator and is grounded after passing through the fourth capacitor, and the other end of the eighth resistor is connected with the negative input end of the comparator and is grounded after passing through the fifth capacitor;

the output end of the comparator is used as the output end of the demodulation circuit.

Specifically, the sampling module comprises a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifth resistor and a sixth resistor,

the grid electrode of the seventh NMOS tube is connected with the first pulse width modulation signal, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube and is connected with the input voltage of the charging base, and the source electrode of the seventh NMOS tube is connected with the drain electrodes of the ninth NMOS tube and the eleventh NMOS tube and the output end of the switch control branch controlled by the first pulse width modulation signal in the charging base;

the grid electrode of the eighth NMOS tube is connected with the second pulse width modulation signal, and the source electrode of the eighth NMOS tube is connected with the drain electrodes of the tenth NMOS tube and the twelfth NMOS tube and the output end of the switch control branch controlled by the second pulse width modulation signal in the charging base;

the grid electrode of the thirteenth NMOS tube is connected with the grid electrodes of the ninth NMOS tube and the eleventh NMOS tube and is connected with the inverted signal of the first pulse width modulation signal, the drain electrode of the thirteenth NMOS tube is connected with the source electrode of the eleventh NMOS tube and the first output end of the sampling module and is grounded through a fifth resistor, and the source electrode of the thirteenth NMOS tube is connected with the source electrodes of the ninth NMOS tube, the tenth NMOS tube and the fourteenth NMOS tube and is grounded;

the grid electrode of the fourteenth NMOS tube is connected with the grid electrodes of the tenth NMOS tube and the twelfth NMOS tube and is connected with the inverted signal of the second pulse width modulation signal, and the drain electrode of the fourteenth NMOS tube is connected with the source electrode of the twelfth NMOS tube and the second output end of the sampling module and is grounded through a sixth resistor;

the first output end and the second output end of the sampling module alternately generate the voltage signal output by the sampling module.

The invention has the beneficial effects that: firstly, compared with the traditional average current demodulation scheme, the peak current demodulation scheme and the valley current demodulation scheme are added in the demodulation circuit provided by the invention, so that the demodulation capability of a wireless charging system can be enhanced, and normal demodulation can be ensured particularly under the condition of light load; secondly, the circuit for acquiring the peak current and the valley current is simple in structure, and the area of a chip can be saved; moreover, based on various demodulation schemes provided by the invention, in order to reduce the chip area and the power consumption, the invention also provides a method for processing average current demodulation, peak current demodulation and valley current demodulation in a time-sharing multiplexing mode; finally, the invention adopts the amplifying module with a band-pass structure to process the voltage signal converted by the sampled inductive current, solves the swing amplitude problem during current amplification, and ensures that peak current demodulation and valley current demodulation can be normally demodulated when the current change is large before and after demodulation.

Drawings

The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.

Fig. 1 is a circuit diagram of one implementation of a wireless charging system.

Fig. 2 is a waveform diagram of the inductor current IL and the demodulation result Iaverge _ DM when the average current demodulation scheme is adopted.

Fig. 3 is a waveform diagram of the inductor current IL and the demodulation result Ipeak _ DM when the peak current demodulation scheme is adopted in the demodulation circuit for wireless charging according to the present invention.

Fig. 4 is a waveform diagram of the inductor current IL and the demodulation results Iaverge _ DM and Ipeak _ DM when the demodulation circuit for wireless charging simultaneously samples the peak current demodulation scheme and the average current demodulation scheme according to the present invention.

Fig. 5 is a schematic structural diagram of a wireless charging demodulation circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

As shown in fig. 1, the charging base of the wireless charging system includes two switch control branches, a first switch control branch includes a first switch tube M11 and a second switch tube M13, and is controlled by a first pulse width modulation signal PWM1 and an inverse signal PWM1z thereof; the second switch control branch comprises a third switch tube M12 and a fourth switch tube M14, and is controlled by a second pulse width modulation signal PWM2 and an inverse signal PWM2z thereof. The first switching tube M11 and the second switching tube M13 are connected in series between the input voltage VIN _ TX of the charging base and the ground GND _ TX, and the connection point is used as the output terminal SW1_ TX of the first switch control branch; the third switching tube M12 and the fourth switching tube M14 are also connected in series between the input voltage VIN _ TX of the charging base and the ground GND _ TX, and the connection point is used as the output terminal SW2_ TX of the second switch control branch; an inductance coil arranged in the charging base is connected between the SW1_ TX and the SW2_ TX.

As shown in fig. 5, the wireless charging demodulation circuit provided by the present invention includes a sampling module a1, an amplifying module a2, a processing module A3, and a demodulation module a4, where the sampling module a1 is configured to sample an inductive current of a charging base in a wireless charging system, convert the inductive current into a corresponding voltage signal, and output the voltage signal, the amplifying module a2 receives the voltage signal output by the sampling module a1, and performs amplification processing by using a band-pass structure to obtain an output current ILsns _ out, the processing module A3 processes the current signal snils _ out to obtain one or more of an average current, a peak current, and a valley current, and finally, the demodulation module a4 demodulates the output current signal of the processing module A3.

One implementation of the sampling module a1 is shown in fig. 5, although other sampling configurations are suitable for use with the present invention. The sampling module a1 in this embodiment adopts a synchronous rectifier bridge SR to sample a corresponding current sampling circuit, and includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifth resistor R5, and a sixth resistor R6, a gate of the seventh NMOS transistor MN7 is connected to the first pulse width modulation signal PWM1, a drain thereof is connected to a drain of the eighth NMOS transistor MN8 and to an input voltage VIN _ TX of the charging base, a source thereof is connected to drains of the ninth NMOS transistor MN9 and the eleventh NMOS transistor MN11, and an output terminal SW1_ TX of a switch control branch controlled by the first pulse width modulation signal PWM1 in the charging base; the gate of the eighth NMOS transistor MN8 is connected to the second PWM signal PWM2, and the source thereof is connected to the drains of the tenth NMOS transistor MN10 and the twelfth NMOS transistor MN12 and the output SW2_ TX of the switch control branch controlled by the second PWM signal PWM2 in the charging base; the gate of the thirteenth NMOS transistor MN13 is connected to the gates of the ninth NMOS transistor MN9 and the eleventh NMOS transistor MN11 and to the inverse signal PWM1z of the first pulse width modulation signal, the drain thereof is connected to the source of the eleventh NMOS transistor MN11 and the first output terminal of the sampling module a1 and to ground through the fifth resistor R5, and the source thereof is connected to the sources of the ninth NMOS transistor MN9, the tenth NMOS transistor MN10 and the fourteenth NMOS transistor MN14 and to ground; the gate of the fourteenth NMOS transistor MN14 is connected to the gates of the tenth NMOS transistor MN10 and the twelfth NMOS transistor MN12 and to the inverted signal PWM2z of the second PWM signal, and the drain of the fourteenth NMOS transistor MN14 is connected to the source of the twelfth NMOS transistor MN12 and the second output terminal of the sampling module a1, and is grounded through the sixth resistor R6.

In normal operation, the sampling module a1 shown in fig. 5 is operated alternately in this embodiment, and there are two paths: one path is that when the first PWM signal PWM1 is high and the second PWM signal PWM2 is low, the seventh NMOS transistor MN7 and the tenth NMOS transistor MN10 are turned on, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are turned off, and the input voltage VIN _ TX passes through the seventh NMOS transistor MN7, the SW1_ TX node, the LC resonant circuit formed by Lp and Cp in the charging base, the SW2_ TX node, and the tenth NMOS transistor MN10, thereby generating a resonant current; the resonant current generates a voltage through the tenth NMOS transistor MN10, and then is divided by the twelfth NMOS transistor MN12 and the fourteenth NMOS transistor MN14 to obtain a sampling signal VIL _ SNS 2. The other path is that when the first pulse width modulation signal PWM1 is low and the second pulse width modulation signal PWM2 is high, the eighth NMOS transistor MN8 and the ninth NMOS transistor are turned on, the seventh NMOS transistor MN7 and the tenth NMOS transistor MN10 are turned off, and the input voltage VIN _ TX passes through the eighth NMOS transistor MN8, the SW2_ TX node, the LC resonant circuit, the SW1_ TX node, and the ninth NMOS transistor MN9 to form a path, so as to generate a resonant current; the resonant current generates a voltage through the ninth NMOS transistor MN9, and then is divided by the eleventh NMOS transistor MN11 and the thirteenth NMOS transistor MN13 to obtain a sampling signal VIL _ SNS 1. Only one of the two paths is in operation, so the first output terminal and the second output terminal of the sampling module a1 alternately generate the output voltage signals VIL _ SNS1 and VIL _ SNS2 of the sampling module a1 and are connected to the input terminal of the amplifying module a 2.

Because the sampling module a1 alternately outputs the voltage signals VIL _ SNS1 and VIL _ SNS2, the amplification module a2 may be provided with two left and right groups of structures as shown in fig. 5, each of which is composed of a first resistor, a second resistor, a third resistor, a first capacitor, a first current source, a second current source, a first NPN type triode, a second NPN type triode, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, and is respectively connected to the VIL _ SNS1 and the VIL _ SNS2 for amplification, the amplification module a2 further includes a fourth resistor R4 and a fourth NMOS transistor MN4, the gate-drain of the fourth NMOS transistor MN4 is shorted, and is connected to the output terminal of the amplification module a2 through the fourth resistor R4, and the source thereof is grounded. As shown in FIG. 5, two voltage signals VIL _ SNS1 and VIL _ SNS2 generated by the sampling module A1 alternately are connected to the second two sets of structures respectivelyA resistor R1₁And R1₂The third PMOS transistor MP3 in the above two structures₁And MP3₂Are connected to the output of the amplifying block a2 and output a current ILsns out.

The connection structures of the devices in the two groups of structures are the same, and the structure of the left group of processing signals VIL _ SNS1 is taken as an example, and as shown in fig. 5, the structure includes a first resistor R1₁A second resistor R2₁A third resistor R3₁A first capacitor C1₁A first current source I1₁A second current source I2₁A first NPN type triode Q1₁A second NPN transistor Q2₁A first NMOS transistor MN1₁A second NMOS transistor MN2₁A third NMOS transistor MN3₁The first PMOS transistor MP1₁A second PMOS transistor MP2₁And a third PMOS transistor MP3₁A first NPN transistor Q1₁The base electrode and the collector electrode of the transistor are connected with a second NPN type triode Q2₁And through a first current source I1₁Connected to a supply voltage and having its emitter passing through a first resistor R1₁A back connection signal VIL _ SNS 1; first NMOS transistor MN1₁Is connected with a second NPN type triode Q2₁And through a second current source I2₁A power supply voltage is connected, and the source of the power supply voltage is connected with a second NPN type triode I2₁Emitter electrode and pass through a second resistor R2₁Back grounded, and its drain connected to a third resistor R3₁One end of the third PMOS tube MP3₁And the first PMOS transistor MP1₁A gate and a drain of (1); second PMOS pipe MP2₁Is connected to a third resistor R3₁And through the first capacitor C1₁A back-connected power supply voltage, a source connected with the first PMOS transistor MP1₁And a third PMOS transistor MP3₁Is connected with the power supply voltage, and the drain electrode of the transistor is connected with a second NMOS transistor MN2₁And a third NMOS transistor MN3₁A gate electrode of (1); third NMOS transistor MN3₁Is connected with the third PMOS tube MP3₁Is connected with the output end of the amplifying module, and the source electrode of the amplifying module is connected with a second NMOS tube MN2₁And to ground.

The structure of the right group of processing signals VIL _ SNS2A resistor R1₂A second resistor R2₂A third resistor R3₂A first capacitor C1₂A first current source I1₂A second current source I2₂A first NPN type triode Q1₂A second NPN transistor Q2₂A first NMOS transistor MN1₂A second NMOS transistor MN2₂A third NMOS transistor MN3₂The first PMOS transistor MP1₂A second PMOS transistor MP2₂And a third PMOS transistor MP3₂The connection and processing principles are similar and will not be described in detail herein.

The current amplification in the conventional demodulation scheme adopts a low-pass structure, while the amplification module a2 of the present invention adopts an AC voltage signal amplification circuit with a band-pass structure, which has the advantages that when the load current is large, the central point of the output current ILsns _ out of the amplification module a2 of the present invention is still near 1/2VDD, VDD is the supply voltage, so that the upper and lower swing of ILsns _ out are as equal as possible, and thus, even if the current before and after demodulation varies greatly, normal demodulation of the peak current Ipeak and the valley current ivally processed by ILsns _ out can be ensured.

The current signal ILsns _ out output by the amplifying module a2 is processed by the processing module A3 to obtain any one or more of an average current, a peak current, and a valley current of the ILsns _ out. It is preferable that all three signals of the average current, the peak current, and the valley current of the ILsns _ out are obtained to ensure that demodulation is normal, but it is also possible to obtain only any one or any two of the average current, the peak current, and the valley current of the ILsns _ out.

As shown in fig. 5, an implementation structure of the processing module A3 obtaining a peak current according to ILsns _ out is provided, where a peak sample-and-hold circuit of the processing module A3 includes a third current source I3, a fourth current source I4, a second capacitor C2, a fifth NMOS transistor MN5, and a fourth PMOS transistor MP4, a gate of the fifth NMOS transistor MN5 is connected to an output terminal of the amplifying module a2, a drain of the fifth NMOS transistor MN5 is connected to a power supply voltage, and a source of the fifth NMOS transistor MN5 is connected to a gate of the fourth PMOS transistor MP4, and is grounded after passing through the second capacitor C2 and the third current source I3, respectively; the drain of the fourth PMOS transistor MP4 is grounded, and the source thereof outputs the peak current Ipeak of the current signal output by the amplifying module and is connected to the power voltage after passing through the fourth current source I4.

As shown in fig. 5, an implementation structure that the processing module A3 obtains the valley current according to ILsns _ out is also provided, the valley sample-and-hold circuit of the processing module A3 includes a fifth current source I5, a sixth current source I6, a third capacitor C3, a sixth NMOS transistor MN6, and a fifth PMOS transistor MP5, a gate of the fifth PMOS transistor MP5 is connected to the output terminal of the amplifying module a2, a drain thereof is grounded, a source thereof is connected to a gate of the sixth NMOS transistor MN6, and is grounded after passing through the third capacitor C3 and connected to the power supply voltage after passing through the fifth current source I5, respectively; the drain of the sixth NMOS transistor MN6 is connected to the power supply voltage, and the source thereof outputs the valley current ivally of the current signal output by the amplifying module, and is grounded after passing through the sixth current source I6.

There are various ways for the processing module a3 to obtain the average current Iaverage of the current signal output by the amplifying module, for example, the RC low-pass filter may be used to process the current signal output by the amplifying module ILsns _ out, so that the dc component of the current signal ILsns _ out passes through and the high frequency component is blocked, thereby obtaining the average current Iaverage.

The demodulation module a4 demodulates the signal output from the processing module A3, including average current demodulation, peak current demodulation, and/or valley current demodulation. If only one demodulation scheme is selected for demodulation, as shown in fig. 2, only the average current demodulation scheme is selected, and a demodulation failure condition may occur; as shown in fig. 3, only the peak current demodulation scheme is adopted, and the inductive current IL before and after modulation and the peak current demodulation result Ipeak _ DM under no-load condition are shown in fig. 3, it can be seen that the signal Ipeak _ DM after the inductive current IL is demodulated by the peak current is obviously different before and after demodulation, so that the peak current demodulation scheme can be normally demodulated; the principle of valley current demodulation is similar to that of peak current demodulation, and it can be seen that if only one demodulation scheme is selected, normal demodulation can be ensured by selecting peak current demodulation or valley current demodulation, and the problem of demodulation failure under no-load condition can be solved by increasing peak current Ipeak demodulation and valley current IValy demodulation.

If two schemes are selected for demodulation, the average current demodulation, the peak current demodulation and the valley current demodulation can be combined randomly, as shown in fig. 4, if the average current demodulation and the peak current demodulation are adopted at the same time, it can be seen that when the average current demodulation is used, the inductor current IL before and after modulation under no-load conditions is zero before and after the average current demodulation, i.e., before and after the iaverage _ DM demodulation, and normal demodulation cannot be performed; the signal Ipeak _ DM demodulated by the peak current is obviously different before and after demodulation, and can be normally demodulated; therefore, the two schemes are selected to be demodulated together, so that the accuracy of the demodulation result can be improved. Certainly, the three schemes of average current demodulation, peak current demodulation and valley current demodulation can ensure the correctness of the demodulation result compared with the traditional average current demodulation.

When the processing module A3 outputs two or three of the average current Iaverage, the peak current Ipeak and the valley current Ivaly, the demodulation module a4 may demodulate all signals output by the processing module A3 in parallel, but any demodulation method in the wireless charging system can meet the requirement as long as the demodulation method can demodulate the signals normally, so in order to reduce the area, the average current Iaverage, the peak current Ipeak and the valley current ivay are processed in a time-division multiplexing manner in some embodiments. As shown in fig. 5, the demodulation module a4 of the time division multiplexing in this embodiment includes a multiplexer, a fourth capacitor C4, a fifth capacitor C5, a seventh resistor R7, an eighth resistor R8 and a comparator, where input signals of the multiplexer include an average current Iaverage, a peak current Ipeak and a valley current ivally of an output current signal of the amplification module, and an output end of the multiplexer is connected to one end of the seventh resistor R7; one end of the eighth resistor R8 is connected with the other end of the seventh resistor R7 and the positive input end of the comparator and is grounded after passing through the fourth capacitor C4, and the other end of the eighth resistor R8 is connected with the negative input end of the comparator and is grounded after passing through the fifth capacitor C5; the output end of the comparator is used as the output end of the demodulation circuit to output the demodulation result IDM _ OUT.

In summary, in the embodiment, the sampling module a1 is used to sample the inductive current of the charging base in the wireless charging system and convert the current into the corresponding voltage signals VIL _ SNS1 and VIL _ SNS2, and the output voltages VIL _ SNS1 and VIL _ SNS2 are processed by the AC voltage amplifier with the band-pass structure to obtain the output current signal ILsns _ out of the amplifying module a2, so that the swing problem of the ILsns _ out is solved, and the demodulation can be performed normally when the load current is large.

The swing problem of the ILsns _ out also reflects the capability of normally demodulating the peak current Ipeak and the valley current Ivaly on the side, especially when the current difference before and after demodulation is large, so the average current Iaverage, the peak current Ipeak and the valley current Ivaly obtained by sampling and holding the average value, the peak value and the valley value of the current signal ILsns _ out generated by the amplifying module a2 with a band-pass structure through the processing module A3 also have better normal demodulation capability; the specific implementation circuits of the peak value sampling and holding circuit and the valley value sampling and holding circuit of the processing module A3 adopted by the invention are simple, and the area of a chip can be saved.

Finally, the demodulation module a4 sends the signal output by the processing module A3 to a comparator for demodulation, and particularly, when the processing module A3 generates two or three signals of an average current Iaverage, a peak current Ipeak and a valley current ivally, the demodulation module a4 performs processing by using a time-division multiplexing method, so that the circuit area and the power consumption are saved.

Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims

1. A wireless charging demodulation circuit comprises a charging base and a terminal, wherein inductance coils are respectively arranged in the charging base, the charging base comprises two switch control branches which are respectively controlled by a first pulse width modulation signal and a second pulse width modulation signal, and the inductance coils of the charging base are connected between the output ends of the two switch control branches;

the amplifier is characterized in that the amplifying module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a first current source, a second current source, a first NPN type triode, a second NPN type triode, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a third PMOS tube,

2. The wireless charging demodulation circuit according to claim 1, wherein the processing module includes a third current source, a fourth current source, a second capacitor, a fifth NMOS transistor and a fourth PMOS transistor, a gate of the fifth NMOS transistor is connected to the output terminal of the amplifying module, a drain of the fifth NMOS transistor is connected to the supply voltage, and a source of the fifth NMOS transistor is connected to the gate of the fourth PMOS transistor and is grounded after passing through the second capacitor and the third current source, respectively; the drain electrode of the fourth PMOS tube is grounded, and the source electrode of the fourth PMOS tube outputs the peak current of the current signal output by the amplification module and is connected with the power supply voltage after passing through the fourth current source.

3. The wireless charging demodulation circuit according to claim 1 or 2, wherein the processing module comprises a fifth current source, a sixth current source, a third capacitor, a sixth NMOS transistor and a fifth PMOS transistor, a gate of the fifth PMOS transistor is connected to the output terminal of the amplifying module, a drain of the fifth PMOS transistor is grounded, and a source of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor, and is grounded after passing through the third capacitor and is connected to a power supply voltage after passing through the fifth current source, respectively; the drain electrode of the sixth NMOS tube is connected with the power supply voltage, and the source electrode of the sixth NMOS tube outputs valley current of the current signal output by the amplification module and is grounded after passing through the sixth current source.

4. The wireless charging demodulation circuit according to claim 3, wherein the processing module comprises an RC low-pass filter, and the average current of the current signal output by the amplifying module is obtained after the current signal passes through the RC low-pass filter.

5. The wireless charging demodulation circuit of claim 4 wherein the demodulation module comprises a multiplexer, a fourth capacitor, a fifth capacitor, a seventh resistor, an eighth resistor, and a comparator,

6. The wirelessly charged demodulation circuit according to claim 1, 4 or 5,

the sampling module comprises a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifth resistor and a sixth resistor,