CN114336875A - Current demodulation circuit for wireless charging - Google Patents
Current demodulation circuit for wireless charging Download PDFInfo
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- CN114336875A CN114336875A CN202210003039.3A CN202210003039A CN114336875A CN 114336875 A CN114336875 A CN 114336875A CN 202210003039 A CN202210003039 A CN 202210003039A CN 114336875 A CN114336875 A CN 114336875A
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Abstract
The invention belongs to the technical field of wireless charging, and particularly relates to a current demodulation circuit for wireless charging. The invention aims to reduce the capacitance value and the area of a chip, mainly adjusts the time constant of a filter circuit through a pulse signal generator, and increases the time constant to the value of the output duty ratio D of the pulse signal generator
Therefore, the purpose of reducing the capacitance is realized, and the area of the chip is further reduced.
Description
Technical Field
The invention belongs to the technical field of wireless charging, and particularly relates to a current demodulation circuit for wireless charging.
Background
Most of the wireless mobile phones in the market currently adopt the scheme shown in fig. 1 for charging. The wireless charging base Transimiter (Tx) charges the mobile phone receiver (Rx) through the coupling coil. Then Tx knows how much power is being transferred to Rx, that is, how much charging current is being provided to Rx. The Rx necessarily needs to send information to the Tx for it to transmit the proper power. The path of Rx transfer information is as follows: when Rx needs more energy, then a Controller (Rx _ control) in the mobile phone turns on modulation tubes M25 and M26 in Rx simultaneously, so that modulation capacitors Cm1 and Cm2 are inserted into Ls and Cs resonant circuits in Rx, after Cm1 and Cm2 are inserted, impedance characteristics of Ls and Cs resonant circuits in Rx are changed, so as to cause a change in Current of Ls, then inductor Current of Lp in Tx is changed through coupling, a Current Snse circuit in Tx samples Current of coupling inductor Lp through rectification tubes M13 and M14, and sends the sampled signal to a Tx-side Demodulation module, and then the Demodulation sends the demodulated signal to a Controller (Tx _ control) of Tx, so that Tx _ control adjusts the frequency and duty ratio of PWM1 and PWM2 in Tx to adjust transmission power. Typically the frequencies adjusted by M25 and M26 inside Rx are 2KHz square waves. The frequency of the PWM1 and PWM2 signals in Tx is generally 100 kHz-200 kHz.
As shown in fig. 2 and 3, typical peak current and valley current demodulation circuits, respectively. From fig. 1, it is known that the signal to be demodulated is a 2kHz frequency, in order to enable normal demodulation, R1 and C1 form a filter network to filter out a 100kHz signal, and R2 and C2 need to filter out a 2kHz frequency. In general, for better filtering effect, the cut-off frequency of the filter network formed by R1 and C1 is set at 5 kHz; the cut-off frequency of the filter network formed by R2 and C2 is about 100 Hz. Since the system has a limit on the depth of current demodulation, that is, the minimum current variation that can be demodulated is usually about 20mA, and there is only a few mV variations on the corresponding filter network, in order to reduce the influence of voltage drop generated by leakage on the resistor on demodulation, the R1 and R2 resistors usually do not exceed 10Mohm, so it can be known through calculation: the capacitance of C1 is about 10pF, and the capacitance of C2 may be about 200pF, so that the capacitance of C2 is too large, and the occupied area is too large.
Disclosure of Invention
In view of the above problems, the present invention provides a current demodulation circuit for wireless charging, which can reduce the capacitance of C2 and reduce the chip area.
The technical scheme of the invention is as follows:
the utility model provides a current demodulation circuit for wireless charging, includes sampling circuit, source follower, first order filter circuit, second level filter circuit and comparator, sampling circuit is arranged in sampling to transmitting terminal coupling inductive current among the wireless charging system, and sampling circuit's output is connected to the positive input of comparator behind the first order filter circuit through the source follower, connects after first order filter circuit and second level filter circuit in proper orderThe comparator outputs a demodulated signal to the negative input end of the price comparator; the circuit is characterized by further comprising an adjusting circuit between the first-stage filter circuit and the second-stage filter circuit, wherein the adjusting circuit comprises a transmission gate, a phase inverter and a pulse signal generator, the input end of the transmission gate is connected with the output end of the first-stage filter circuit, the output end of the transmission gate is connected with the input end of the second-stage filter circuit, the first control end of the transmission gate is connected with the output end of the pulse signal generator, and the second control end of the transmission gate is connected with the output end of the phase inverter; the input end of the phase inverter is connected with the output end of the pulse signal generator, and the other end of the pulse signal generator is grounded; defining the output duty ratio of the pulse signal transmitter as D, and the regulating circuit is used for increasing the time constant of the second stage filter circuit to
And (4) doubling.
Further, the sampling circuit is a peak value sampling circuit.
Further, the sampling circuit comprises an NMOS tube, a first current source and a capacitor; the grid electrode of the NMOS tube is connected with a current sampling signal, the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a first current source and one end of a capacitor, and the output end of the first current source and the other end of the capacitor are grounded; and the connection point of the source electrode of the NMOS tube, the first current source and the capacitor is the output end of the sampling circuit.
Further, the source follower comprises a PMOS tube and a second current source; the input end of the second current source is connected with the power supply, the output end of the second current source is connected with the source electrode of the PMOS tube, the grid electrode of the PMOS tube is connected with the output end of the sampling circuit, the drain electrode of the PMOS tube is grounded, and the connection point of the source electrode of the PMOS tube and the second current source is the output end of the source electrode follower.
Further, the sampling circuit is a valley value sampling circuit.
Furthermore, the sampling circuit comprises a PMOS tube, a first current source and a capacitor; the grid electrode of the PMOS tube is connected with a current sampling signal, the drain electrode of the PMOS tube is grounded, the source electrode of the PMOS tube is connected with the output end of the first current source and one end of the capacitor, the input end of the first current source is connected with the power supply, and the other end of the capacitor is grounded; and the connection point of the source electrode of the PMOS tube, the first current source and the capacitor is the output end of the sampling circuit.
Further, the source follower comprises an NMOS tube and a second current source; the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a second current source, the output end of the second current source is grounded, the grid electrode of the NMOS tube is connected with the output end of the sampling circuit, and the connection point of the source electrode of the NMOS tube and the second current source is the output end of the source electrode follower.
Furthermore, the first stage filter circuit is an RC filter circuit and is used for filtering signals with the frequency of more than or equal to 100 kHz; the second stage filter circuit is an RC filter circuit and is used for filtering signals with the frequency more than or equal to 2 kHz.
Further, the output duty cycle D of the pulse signal transmitter is 5%.
The invention has the beneficial effects that: on the premise of meeting the requirement of current demodulation, the capacitance of the C2 can be reduced, so that the area of a chip is reduced.
Drawings
Fig. 1 is a schematic diagram of a wireless charging principle of a mobile phone.
Fig. 2 is a typical peak current demodulation circuit.
Fig. 3 is a typical valley current demodulation circuit.
Fig. 4 is a core schematic diagram of the current demodulation circuit of the present invention.
Fig. 5 is a circuit diagram of peak current demodulation according to the present invention.
Fig. 6 is a valley current demodulation circuit diagram of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The principle of the present invention is shown in fig. 4, and the small signal formula is derived as follows:
a. when the transmission door is opened
b. When the transmission door is closed
Vout＝0
For review:
the average value of Vout over one period is then:
therefore, the transfer function of the circuit is
Due to duty cycle 0<D<1, the structure realizes to increase the time constant of the RC filter circuit
And (4) doubling. For example, when the duty ratio is 5%, the RC time constant in the current demodulation circuit can be multiplied by 20 times, so that the purpose of reducing the capacitor C2 can be achieved.
As shown in fig. 3, is a typical peak current demodulation circuit. It can be known from fig. 1 that the signal to be demodulated is a 2kHz frequency, in order to enable normal demodulation, R1 and C1 form a filter network to filter the signal of 100kHz, and R2 and C2 need to filter the frequency of 2 kHz. In general, for better filtering effect, the cut-off frequency of the filter network formed by R1 and C1 is set at 5 kHz; the cut-off frequency of the filter network formed by R2 and C2 is about 100 Hz. Usually, because the system has a limitation on the depth of current demodulation, that is, the minimum current variation that can be demodulated is usually about 20mA, and there is only a few mV variations on the corresponding filter network, in order to reduce the influence of voltage drop generated on the resistor by leakage on demodulation, the resistors R1 and R2 are usually not more than 10Mohm, so it can be known through calculation: the capacitance of C1 is roughly around 10pF, while the capacitance of C2 may be around 200 pF. The capacitance of C2 is too large and occupies too large an area.
Fig. 5 is an optimized peak current demodulation circuit, in which an NMOS transistor MN1, a current source I1, and a capacitor cpaak form a peak sampling circuit; the PMOS tubes MP1 and I2 form a source follower which mainly provides certain driving capability for a later stage, and R1 and C1 form a first stage filter network for filtering frequencies of 100kHz and above; r2 and C2 form a second stage filter circuit, which mainly filters frequencies of 2kHz and above. The two filtered signals are sent to a comparator Comp1 for comparison, so as to obtain a demodulated signal D _ Dmod.
Fig. 6 is an optimized valley current demodulation circuit, in which a PMOS transistor MP1, a current source I1, and a capacitor Cvally form a valley sampling circuit; the NMOS tubes MN1 and I2 form a source follower which mainly provides certain driving capability for a later stage, and R1 and C1 form a first stage filter network for filtering frequencies of 100kHz and above; r2 and C2 form a second stage filter circuit, which mainly filters frequencies of 2kHz and above. The two filtered signals are sent to a comparator Comp1 for comparison, so as to obtain a demodulated signal D _ Dmod.
Claims (9)
1. A current demodulation circuit for wireless charging comprises a sampling circuit, a source follower, a first-stage filter circuit, a second-stage filter circuit and a comparator, wherein the sampling circuit is used for sampling coupling inductive current of a transmitting end in a wireless charging system; the circuit is characterized by further comprising an adjusting circuit between the first-stage filter circuit and the second-stage filter circuit, wherein the adjusting circuit comprises a transmission gate, a phase inverter and a pulse signal generator, the input end of the transmission gate is connected with the output end of the first-stage filter circuit, the output end of the transmission gate is connected with the input end of the second-stage filter circuit, the first control end of the transmission gate is connected with the output end of the pulse signal generator, and the second control end of the transmission gate is connected with the output end of the phase inverter; the input end of the phase inverter is connected with the output end of the pulse signal generatorThe other end of the signal generator is grounded; defining the output duty ratio of the pulse signal transmitter as D, and the regulating circuit is used for increasing the time constant of the second stage filter circuit to
And (4) doubling.
2. The current demodulation circuit for wireless charging as claimed in claim 1, wherein said sampling circuit is a peak sampling circuit.
3. The current demodulation circuit for wireless charging according to claim 2, wherein the sampling circuit comprises an NMOS transistor, a first current source, a capacitor; the grid electrode of the NMOS tube is connected with a current sampling signal, the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a first current source and one end of a capacitor, and the output end of the first current source and the other end of the capacitor are grounded; and the connection point of the source electrode of the NMOS tube, the first current source and the capacitor is the output end of the sampling circuit.
4. The current demodulation circuit for wireless charging according to claim 3, wherein the source follower comprises a PMOS transistor and a second current source; the input end of the second current source is connected with the power supply, the output end of the second current source is connected with the source electrode of the PMOS tube, the grid electrode of the PMOS tube is connected with the output end of the sampling circuit, the drain electrode of the PMOS tube is grounded, and the connection point of the source electrode of the PMOS tube and the second current source is the output end of the source electrode follower.
5. The current demodulation circuit for wireless charging as claimed in claim 1, wherein said sampling circuit is a valley sampling circuit.
6. The current demodulation circuit for wireless charging according to claim 5, wherein the sampling circuit comprises a PMOS tube, a first current source, a capacitor; the grid electrode of the PMOS tube is connected with a current sampling signal, the drain electrode of the PMOS tube is grounded, the source electrode of the PMOS tube is connected with the output end of the first current source and one end of the capacitor, the input end of the first current source is connected with the power supply, and the other end of the capacitor is grounded; and the connection point of the source electrode of the PMOS tube, the first current source and the capacitor is the output end of the sampling circuit.
7. The current demodulation circuit for wireless charging according to claim 6, wherein the source follower comprises an NMOS transistor and a second current source; the drain electrode of the NMOS tube is connected with a power supply, the source electrode of the NMOS tube is connected with the input end of a second current source, the output end of the second current source is grounded, the grid electrode of the NMOS tube is connected with the output end of the sampling circuit, and the connection point of the source electrode of the NMOS tube and the second current source is the output end of the source electrode follower.
8. The current demodulation circuit for the wireless charging according to any one of claims 1 to 7, wherein the first stage filter circuit is an RC filter circuit and is used for filtering signals with a frequency of 100kHz or more; the second stage filter circuit is an RC filter circuit and is used for filtering signals with the frequency more than or equal to 2 kHz.
9. The current demodulation circuit for wireless charging according to claim 8, wherein the output duty cycle D of the pulse signal transmitter is 5%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210003039.3A CN114336875B (en) | 2022-01-04 | 2022-01-04 | Current demodulation circuit for wireless charging |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210003039.3A CN114336875B (en) | 2022-01-04 | 2022-01-04 | Current demodulation circuit for wireless charging |
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| Publication Number | Publication Date |
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| CN114336875A true CN114336875A (en) | 2022-04-12 |
| CN114336875B CN114336875B (en) | 2023-10-27 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0484568A (en) * | 1990-07-27 | 1992-03-17 | New Japan Radio Co Ltd | Vertical synchronizing signal separator circuit |
| US6597238B1 (en) * | 1999-04-22 | 2003-07-22 | Matsushita Electric Industrial Co., Ltd | Demodulating circuit of wireless receiving apparatus and demodulating method |
| CN1744442A (en) * | 2004-08-30 | 2006-03-08 | 三洋电机株式会社 | Digital to analog converter |
| CN112202231A (en) * | 2020-12-09 | 2021-01-08 | 上海南芯半导体科技有限公司 | Wireless charging demodulation circuit |
| CN112311329A (en) * | 2019-12-21 | 2021-02-02 | 成都华微电子科技有限公司 | Low-power-consumption crystal oscillator circuit capable of starting oscillation rapidly |
-
2022
- 2022-01-04 CN CN202210003039.3A patent/CN114336875B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0484568A (en) * | 1990-07-27 | 1992-03-17 | New Japan Radio Co Ltd | Vertical synchronizing signal separator circuit |
| US6597238B1 (en) * | 1999-04-22 | 2003-07-22 | Matsushita Electric Industrial Co., Ltd | Demodulating circuit of wireless receiving apparatus and demodulating method |
| CN1744442A (en) * | 2004-08-30 | 2006-03-08 | 三洋电机株式会社 | Digital to analog converter |
| US20060071836A1 (en) * | 2004-08-30 | 2006-04-06 | Sanyo Electric Co., Ltd. | Digital to analog converter |
| CN112311329A (en) * | 2019-12-21 | 2021-02-02 | 成都华微电子科技有限公司 | Low-power-consumption crystal oscillator circuit capable of starting oscillation rapidly |
| CN112202231A (en) * | 2020-12-09 | 2021-01-08 | 上海南芯半导体科技有限公司 | Wireless charging demodulation circuit |
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| CN114336875B (en) | 2023-10-27 |
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