CN214278949U - Power regulating circuit and NFC card reader - Google Patents
Power regulating circuit and NFC card reader Download PDFInfo
- Publication number
- CN214278949U CN214278949U CN202120561337.5U CN202120561337U CN214278949U CN 214278949 U CN214278949 U CN 214278949U CN 202120561337 U CN202120561337 U CN 202120561337U CN 214278949 U CN214278949 U CN 214278949U
- Authority
- CN
- China
- Prior art keywords
- clock signal
- module
- power supply
- mos tube
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The application relates to the technical field of communication and discloses a power regulating circuit. This application is through the voltage of adjusting MOS pipe grid among the power regulating circuit, adjusts the absolute value of the voltage difference of MOS pipe grid and source electrode promptly, has changed the equivalent resistance of MOS pipe, and then adjusts wireless transceiver's transmitting power, compares in current power regulating circuit, and the parallelly connected quantity that need not change the power pipe just can realize power regulation, and is more convenient. The application also discloses an NFC card reader.
Description
Technical Field
The application relates to the technical field of communication, for example, to a power regulating circuit and an NFC card reader.
Background
Wireless communication devices are now increasingly used in life. The antenna of the wireless communication device has different coupling coefficients at different distances, and the communication between the devices is very dependent on the field intensity and the transmitting power of the electromagnetic field, so that the communication distance and the communication quality can be effectively adjusted by adjusting the transmitting power of the wireless communication device. The power amplifier of the conventional wireless communication device adjusts the transmission power by changing the parallel number of Metal Oxide Semiconductor (MOS) transistors, increases the parallel number of power transistors when the transmission power needs to be increased, and decreases the parallel number of power transistors when the transmission power needs to be decreased.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
it is common for communication devices that the number of power transistors in the power conditioning circuit has been fixed, making it difficult to perform power conditioning by changing the number of power transistors of the same communication device.
SUMMERY OF THE UTILITY MODEL
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a power regulation circuit and an NFC card reader, so that power regulation is facilitated.
In some embodiments, the power conditioning circuit comprises:
the clock signal generating module is used for generating a first clock signal;
the power adjusting module is used for adjusting the power of the antenna radiating body; the power regulation module comprises an MOS (metal oxide semiconductor) tube, the grid electrode of the MOS tube is connected with the clock signal generation module, and the clock signal generation module outputs the first clock signal to the MOS tube, so that VGS (voltage variation System) of the MOS tube is changed.
In some embodiments, the power conditioning circuit comprises:
the first clock signal generating module is used for generating a first clock signal;
the grid electrode of the first MOS tube is connected with the first clock signal generation module, and the first clock signal generation module outputs the first clock signal to the first MOS tube so as to change VGS of the first MOS tube;
the second clock signal generating module is used for generating a third clock signal;
the grid electrode of the second MOS tube is connected with the second clock signal generation module, and the second clock signal generation module outputs the third clock signal to the second MOS tube so as to change VGS of the second MOS tube; the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the first MOS tube and the second MOS tube form a power regulator for regulating the power of the antenna radiator.
In some embodiments, the NFC reader includes the power conditioning circuit described above.
The power regulating circuit and the NFC card reader provided by the embodiment of the disclosure can realize the following technical effects:
through the voltage of the grid of the MOS pipe among the regulation power regulating circuit, adjust the absolute value of the voltage difference of MOS pipe grid and source electrode promptly, changed the equivalent resistance of MOS pipe, and then adjust wireless transceiver's transmitting power, compare in current power regulating circuit, do not need to change the parallelly connected quantity of power pipe and just can realize power control, it is more convenient.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
FIG. 1 is a schematic diagram of a power conditioning circuit provided by embodiments of the present disclosure;
FIG. 2 is a schematic diagram of another power conditioning circuit provided by an embodiment of the present disclosure;
fig. 3 is a schematic diagram of another power conditioning circuit provided by an embodiment of the present disclosure.
Reference numerals:
11: a PMOS tube; 12: an NMOS tube; 21: a level conversion module; 22: a charge pump; 23: an amplifier; 31: a capacitor; 32: an inductor coil; 41 a first level conversion module; 42: a first charge pump; 43: a first amplifier; 5: a first MOS transistor; 61: a second level shift module; 62: a second charge pump; 63: a second amplifier; 7: and a second MOS transistor.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the disclosed embodiments and their examples and are not intended to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meanings of these terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art as appropriate.
In addition, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. Specific meanings of the above terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art according to specific situations.
The term "plurality" means two or more unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.
At present, communication between wireless communication devices depends on transmission power, communication distance and quality can be effectively adjusted by adjusting the transmission power of the wireless communication devices, and a power adjusting circuit is needed to conveniently adjust the transmission power of the wireless communication devices.
With reference to fig. 1 and fig. 2, an embodiment of the present disclosure provides a power conditioning circuit including a clock signal generation module and a power conditioning module. The clock signal generating module is used for generating a first clock signal; the power adjusting module is used for adjusting the power of the antenna radiating body; the power regulation module comprises an MOS (metal oxide semiconductor) tube, the grid electrode of the MOS tube is connected with the clock signal generation module, and the clock signal generation module outputs a first clock signal to the MOS tube, so that VGS (voltage variation System) of the MOS tube is changed. VGS is the absolute value of the voltage difference of the grid and the source of the MOS tube.
By adopting the power regulating circuit provided by the embodiment of the disclosure, the voltage of the grid electrode of the MOS tube in the power regulating circuit is regulated, namely the absolute value of the voltage difference between the grid electrode and the source electrode of the MOS tube is regulated, the equivalent resistance of the MOS tube is changed, and then the transmitting power of the wireless transceiver is regulated.
Optionally, the clock signal generation module comprises a level conversion module 21 and a charge pump 22. The level conversion module 21 is connected with a clock signal source, and the level conversion module 21 is configured to amplify a signal amplitude of a second clock signal received from the clock signal source to obtain a first clock signal; the input end of the charge pump 22 is connected with a power supply module, and the output end of the charge pump 22 is connected with the power supply input end of the level conversion module 21; the charge pump 22 is configured to convert a power supply voltage input by the power supply module and provide the converted voltage to the level conversion module 21.
Optionally, the power conditioning circuit further comprises an antenna matching network. Optionally, the antenna matching network comprises an inductor coil 32 and a capacitor 31; the inductor 32 is connected in parallel with the capacitor 31.
As shown in fig. 1, optionally, the MOS transistor is a PMOS transistor 11, and a source of the PMOS transistor 11 is connected to the power module. Optionally, the antenna matching network is connected in series with the PMOS transistor 11, a power input end of the antenna matching network is connected to a drain of the PMOS transistor 11, and a power output end of the antenna matching network is grounded. Optionally, the PMOS transistor is further connected in parallel with a plurality of PMOS transistors. Therefore, the equivalent resistance of the power adjusting module can be further adjusted by changing the parallel connection quantity of the PMOS tubes, and the effect of adjusting the transmitting power of the antenna is achieved.
Optionally, a charge pump is used to convert the first positive supply voltage input by the power supply module to a negative supply voltage. Optionally, the level conversion module converts a low level voltage value of the second clock signal into the negative power supply voltage. The negative power supply voltage is obtained according to the charge pump in the clock signal generation module, the low level voltage value of the second clock signal is adjusted through the level conversion module in the clock signal generation module, and then the voltage of the grid electrode of the PMOS tube is adjusted, namely VGS of the PMOS tube is changed, so that the equivalent resistance of the PMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved.
Optionally, the value range of the negative power supply voltage satisfies a first preset range. Optionally, the first preset range is a safe operating voltage range of the PMOS transistor.
In some embodiments, the charge pump converts the first positive power supply voltage VBAT into the negative power supply voltage VNEG, and the level conversion module converts the low level voltage value of the second clock signal into VNEG, so that the voltage value of the first clock signal ranges from VNEG to VBAT; the source voltage of the PMOS tube is VBAT; under the condition that the voltage value of the first clock signal is VNEG, VGS of the PMOS tube is | VBAT-VNEG |, and compared with VGS of the PMOS tube before adjustment, the VGS of the PMOS tube is adjusted by adjusting the low level voltage value of the second clock signal, so that the VGS of the PMOS tube is adjusted, the equivalent resistance of the PMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved.
As shown in fig. 2, optionally, the MOS transistor is an NMOS transistor 12, and the source of the NMOS transistor 12 is grounded. Optionally, the antenna matching network is connected in parallel with the NMOS transistor 12, a power input end of the antenna matching network is connected to the drain of the NMOS transistor 12, and a power output end of the antenna matching network is connected to the source of the NMOS transistor 12. Optionally, the NMOS transistor is further connected in parallel with a plurality of NMOS transistors. Therefore, the equivalent resistance of the power adjusting module can be further adjusted by changing the parallel connection quantity of the NMOS tubes, and the effect of adjusting the transmitting power of the antenna is achieved.
Optionally, the charge pump is configured to convert a first positive power supply voltage input by the power supply module into a second positive power supply voltage, where the second positive power supply voltage is greater than the first positive power supply voltage. Optionally, the level conversion module converts a high level voltage value of the second clock signal into the second positive power supply voltage. And acquiring a second positive power supply voltage according to the charge pump in the clock signal generation module, adjusting a high level voltage value of the second clock signal through the level conversion module in the clock signal generation module, and further adjusting the grid voltage of the NMOS tube, namely changing VGS (voltage gradient system) of the NMOS tube, so that the equivalent resistance of the NMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved.
Optionally, a value range of the second positive power supply voltage satisfies a first preset range. Optionally, the first preset range is a safe operating voltage range of the NMOS transistor.
In some embodiments, the charge pump converts the first positive power supply voltage VBAT into the second positive power supply voltage VPOS, VPOS is greater than VBAT, the level conversion module converts a high level voltage value of the second clock signal into VPOS, and then the voltage value of the first clock signal ranges from 0 to VPOS; the source voltage of the NMOS tube is 0; under the condition that the voltage value of the first clock signal is VPOS, VGS of the NMOS tube is | VPOS |, and compared with the condition that VGS of the NMOS tube before adjustment is | VBAT |, the VGS of the NMOS tube is adjusted by adjusting the high-level voltage value of the second clock signal, so that the equivalent resistance of the NMOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved.
Optionally, the clock signal generation module further comprises an amplifier 23; the output end of the level conversion module 21 is connected with the input end of the amplifier 23, and the output end of the amplifier 23 is connected with the grid electrode of the MOS tube 1; the power supply input end of the amplifier 23 is connected with the output end of the charge pump 22; the power supply output of the amplifier 23 is connected to ground. Thus, the amplifier is used as a driving unit, and the driving capability of the circuit is increased.
Referring to fig. 3, an embodiment of the present disclosure provides a power conditioning circuit, which includes a first clock signal generating module, a first MOS transistor 5, a second clock signal generating module, and a second MOS transistor 7.
The first clock signal generating module is used for generating a first clock signal; the grid electrode of the first MOS tube 5 is connected with the first clock signal generation module, and the first clock signal generation module outputs a first clock signal to the first MOS tube 5, so that VGS of the first MOS tube 5 is changed; the second clock signal generating module is used for generating a third clock signal; the grid electrode of the second MOS transistor 7 is connected with the second clock signal generation module, and the second clock signal generation module outputs a third clock signal to the second MOS transistor 7, so that VGS of the second MOS transistor 7 changes; the drain electrode of the second MOS tube 7 is connected to the drain electrode of the first MOS tube 5, and the first MOS tube 5 and the second MOS tube 7 constitute a power regulator for regulating the power of the antenna radiator.
Optionally, VGS is an absolute value of a voltage difference between the gate and the source of the MOS transistor.
By adopting the power regulating circuit provided by the embodiment of the disclosure, the voltage of the grid electrode of the MOS tube in the power regulating circuit is regulated, namely the absolute value of the voltage difference between the grid electrode and the source electrode of the MOS tube is regulated, the equivalent resistance of the MOS tube is changed, and then the transmitting power of the wireless transceiver is regulated.
Optionally, the first MOS transistor 5 is a PMOS transistor, and the second MOS transistor 7 is an NMOS transistor; the source electrode of the first MOS tube 5 is connected with the power supply module; the source electrode of the second MOS tube 7 is grounded; the drain electrode of the first MOS tube 5 is connected with the drain electrode of the second MOS tube 7. Optionally, the first MOS transistor is further connected in parallel with a plurality of PMOS transistors. Optionally, the second MOS transistor is further connected in parallel with a plurality of NMOS transistors.
Optionally, the power regulating circuit further comprises an antenna matching network; the antenna matching network is connected in parallel between the source and the drain of the second MOS tube 7. Optionally, the antenna matching network comprises an inductor coil 32 and a capacitor 31; the inductor 32 is connected in parallel with the capacitor 31.
Optionally, the first clock signal generating module includes a first level shift module 41, a first charge pump 42 and a first amplifier 43; the signal input end of the first level conversion module 41 is connected to a clock signal source, and the first level conversion module 41 is configured to receive a second clock signal from the clock signal source and amplify the signal amplitude of the second clock signal to obtain a first clock signal; the signal output end of the first level conversion module 41 is connected with the input end of the first amplifier 43, and the output end of the first amplifier 43 is connected with the gate of the first MOS transistor 5; an output terminal of the first charge pump 42 is connected to a power supply input terminal of the first level shift module 41 and a power supply input terminal of the first amplifier 43, respectively, to supply a voltage to the first level shift module 41 and the first amplifier 43. Thus, the first amplifier 43 serves as a driving unit, increasing the driving capability of the circuit.
Optionally, the second clock signal generating module includes a second level shifting module 61, a second charge pump 62 and a second amplifier 63; the signal input end of the second level conversion module 61 is connected to the clock signal source, and the second level conversion module 61 is configured to receive the second clock signal from the clock signal source and amplify the signal amplitude of the second clock signal to obtain a third clock signal; the signal output end of the second level conversion module 61 is connected with the input end of a second amplifier 63, and the output end of the second amplifier 63 is connected with the gate of the second MOS transistor 7; an output terminal of the second charge pump 62 is connected to a power supply input terminal of the second level shift module 61 and a power supply input terminal of the second amplifier 63, respectively, to supply a voltage to the second level shift module 61 and the second amplifier 63. Thus, the second amplifier 63 serves as a driving unit, increasing the driving capability of the circuit.
Optionally, the input end of the first charge pump is connected to the power supply module, and the first charge pump is configured to convert the first positive power supply voltage input by the power supply module into the negative power supply voltage. Optionally, the first level shift module shifts a low level voltage value of the second clock signal to a negative power supply voltage. The negative power supply voltage is obtained according to the first charge pump in the first clock signal generation module, the low level voltage value of the second clock signal is adjusted through the first level conversion module in the first clock signal generation module, and then the voltage of the grid electrode of the first MOS tube is adjusted, namely the VGS of the first MOS tube is changed, so that the equivalent resistance of the first MOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved. Optionally, the value range of the negative power supply voltage satisfies a first preset range. Optionally, the first preset range is a safe operating voltage range of the MOS transistor. In some embodiments, the first charge pump converts the first positive power supply voltage VBAT into a negative power supply voltage VNEG, and the level conversion module converts a low level voltage value of the second clock signal into VNEG to obtain a first clock signal, wherein the first clock signal has a voltage value ranging from VNEG to VBAT; the source voltage of the first MOS tube is VBAT; under the condition that the voltage value of the first clock signal is VNEG, VGS of the first MOS tube is | VBAT-VNEG |, and compared with VGS of the first MOS tube before adjustment, the VGS of the first MOS tube is adjusted by adjusting the low level voltage value of the second clock signal, so that VGS of the first MOS tube is adjusted, the equivalent resistance of the first MOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved.
Optionally, an input end of a second charge pump is connected to the power supply module, the second charge pump is configured to convert a first positive power supply voltage input by the power supply module into a second positive power supply voltage, and the second positive power supply voltage is greater than the first positive power supply voltage. Optionally, the second level shift module shifts a high level voltage value of the second clock signal to the second positive power supply voltage. And acquiring a second positive power supply voltage according to a second charge pump in the second clock signal generation module, adjusting a high level voltage value of a second clock signal through a second level conversion module in the second clock signal generation module, and further adjusting the voltage of a grid of a second MOS (metal oxide semiconductor) transistor, namely changing VGS (voltage gradient system) of the second MOS transistor, so that the equivalent resistance of the second MOS transistor is changed, and the effect of adjusting the transmitting power of the antenna is achieved. Optionally, a value range of the second positive power supply voltage satisfies a first preset range. Optionally, the first preset range is a safe operating voltage range of the MOS transistor. In some embodiments, the second charge pump converts the first positive power supply voltage VBAT into a second positive power supply voltage VPOS, VPOS is greater than VBAT, the level conversion module converts a high level voltage value of the second clock signal into VPOS to obtain a third clock signal, and a voltage value of the third clock signal ranges from 0 to VPOS; the source voltage of the second MOS tube is 0; under the condition that the voltage value of the third clock signal is VPOS, VGS of the second MOS tube is | VPOS |, and compared with the condition that VGS of the second MOS tube before adjustment is | VBAT |, the VGS of the second MOS tube is adjusted by adjusting the high-level voltage value of the second clock signal, so that the equivalent resistance of the second MOS tube is changed, and the effect of adjusting the transmitting power of the antenna is achieved.
In the prior art, a power amplifier of a wireless communication device can adjust a voltage of a source of an MOS transistor by adding a DC/DC (direct current/direct current converter) circuit and an LDO (low dropout regulator) circuit, so as to achieve an effect of adjusting a transmission power of the wireless communication device. However, since the current output of the MOS transistor becomes the load of the DC/DC circuit and the LDO circuit, the circuit has high power and resistance, and a large number of electronic components need to be integrated to ensure sufficient driving capability. By adopting the power regulating circuit provided by the embodiment of the disclosure, the voltage of the grid of the MOS tube is regulated to regulate the transmitting power, and the circuit has no high-power resistive load, thereby reducing the use of electronic elements and saving the chip area.
The embodiment of the disclosure provides an NFC card reader, which comprises the power regulating circuit.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A power conditioning circuit, comprising:
the clock signal generating module is used for generating a first clock signal;
the power adjusting module is used for adjusting the power of the antenna radiating body; the power regulation module comprises an MOS (metal oxide semiconductor) tube, the grid electrode of the MOS tube is connected with the clock signal generation module, and the clock signal generation module outputs the first clock signal to the MOS tube, so that VGS (voltage variation System) of the MOS tube is changed.
2. The circuit of claim 1, wherein the clock signal generation module comprises:
the level conversion module is connected with a clock signal source and used for amplifying the signal amplitude of a second clock signal received from the clock signal source to obtain a first clock signal;
the input end of the charge pump is connected with a power supply module, and the output end of the charge pump is connected with the power supply input end of the level conversion module; the charge pump is used for converting the power supply voltage input by the power supply module and providing the converted voltage for the level conversion module.
3. The circuit of claim 2, wherein the charge pump is configured to convert a first positive supply voltage input by the power supply module to a negative supply voltage.
4. The circuit of claim 2, wherein the charge pump is configured to convert a first positive supply voltage input by the power supply module to a second positive supply voltage, the second positive supply voltage being greater than the first positive supply voltage.
5. The circuit of claim 2, wherein the clock signal generation module further comprises an amplifier;
the output end of the level conversion module is connected with the input end of the amplifier, and the output end of the amplifier is connected with the grid electrode of the MOS tube; and the power supply input end of the amplifier is connected with the output end of the charge pump.
6. A power conditioning circuit, comprising:
the first clock signal generating module is used for generating a first clock signal;
the grid electrode of the first MOS tube is connected with the first clock signal generation module, and the first clock signal generation module outputs the first clock signal to the first MOS tube so as to change VGS of the first MOS tube;
the second clock signal generating module is used for generating a third clock signal;
the grid electrode of the second MOS tube is connected with the second clock signal generation module, and the second clock signal generation module outputs the third clock signal to the second MOS tube so as to change VGS of the second MOS tube; the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the first MOS tube and the second MOS tube form a power regulator for regulating the power of the antenna radiator.
7. The circuit of claim 6, wherein the first clock signal generation module comprises: the charge pump comprises a first level conversion module, a first charge pump and a first amplifier;
the signal input end of the first level conversion module is connected with a clock signal source, and the first level conversion module is used for receiving a second clock signal from the clock signal source and amplifying the signal amplitude of the second clock signal to obtain a first clock signal; the signal output end of the first level conversion module is connected with the input end of the first amplifier, and the output end of the first amplifier is connected with the grid electrode of the first MOS tube; the output end of the first charge pump is respectively connected with the power supply input end of the first level conversion module and the power supply input end of the first amplifier so as to provide voltage for the first level conversion module and the first amplifier;
the second clock signal generation module comprises a second level conversion module, a second charge pump and a second amplifier;
the signal input end of the second level conversion module is connected with the clock signal source, and the second level conversion module is used for receiving a second clock signal from the clock signal source and amplifying the signal amplitude of the second clock signal to obtain a third clock signal; the signal output end of the second level conversion module is connected with the input end of the second amplifier, and the output end of the second amplifier is connected with the grid electrode of the second MOS tube; the output end of the second charge pump is respectively connected with the power input end of the second level conversion module and the power input end of the second amplifier so as to provide voltage for the second level conversion module and the second amplifier.
8. The circuit of claim 7, wherein a power supply module is connected to an input terminal of the first charge pump, and the first charge pump is configured to convert a first positive power supply voltage input by the power supply module into a negative power supply voltage;
the input end of the second charge pump is connected with the power supply module, the second charge pump is used for converting a first positive power supply voltage input by the power supply module into a second positive power supply voltage, and the second positive power supply voltage is greater than the first positive power supply voltage.
9. The circuit of any of claims 6 to 8, wherein the power conditioning circuit further comprises an antenna matching network; the antenna matching network is connected in parallel between the source electrode and the drain electrode of the second MOS tube.
10. An NFC reader, characterized in that it comprises a power regulating circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120561337.5U CN214278949U (en) | 2021-03-19 | 2021-03-19 | Power regulating circuit and NFC card reader |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120561337.5U CN214278949U (en) | 2021-03-19 | 2021-03-19 | Power regulating circuit and NFC card reader |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214278949U true CN214278949U (en) | 2021-09-24 |
Family
ID=77798414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120561337.5U Active CN214278949U (en) | 2021-03-19 | 2021-03-19 | Power regulating circuit and NFC card reader |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214278949U (en) |
-
2021
- 2021-03-19 CN CN202120561337.5U patent/CN214278949U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10476308B2 (en) | Magnetic resonance wireless power transmission device capable of adjusting resonance frequency | |
| CN101604173B (en) | Low drop-out regulator | |
| TWI280736B (en) | High frequency power amplifier circuit device | |
| US9484150B2 (en) | Multi-mode power amplifying circuit, and multi-mode wireless transmission module and method thereof | |
| US9941936B2 (en) | Method and apparatus for radio modulator and antenna driver | |
| US7945208B2 (en) | Radio frequency integrated circuit | |
| US20190280597A1 (en) | Switching power supply for low step down conversion ratio with reduced switching losses | |
| EP3672046A1 (en) | Power supply system, switched tank converter, and method thereof | |
| US11476725B2 (en) | Wireless power transmitter for high fidelity communications and high power transfer | |
| CN104793672A (en) | Low-dropout linear voltage regulator with high power supply rejection ratio | |
| CN107078703A (en) | Power amplifier matching circuit with DVC | |
| Pérez-Nicoli et al. | Maximum efficiency tracking in inductive power transmission using both matching networks and adjustable AC–DC converters | |
| CN214278949U (en) | Power regulating circuit and NFC card reader | |
| US10476553B2 (en) | Energy transmission using wireless communication system | |
| CN103872992A (en) | Electronic system, radio frequency power amplifier and output power compensation method thereof | |
| CN108880228A (en) | A kind of loop compensation system based on zero pole point tracking mechanism | |
| EP1630926B1 (en) | Power switching device in mobile communication terminal | |
| Yang | A class E power oscillator for 6.78-MHz wireless power transfer system | |
| CN101854114A (en) | Power supply module | |
| Guo et al. | Highly efficient fully integrated multivoltage-domain power management with enhanced PSR and low cross-regulation | |
| Youn et al. | High efficiency magnetic resonance wireless power transfer system and charging IC for mobile devices | |
| US6452457B1 (en) | Electronic apparatus comprising a power amplifier | |
| CN209692618U (en) | Converter control circuit and chip | |
| CN102035478B (en) | Frequency compensation circuit applicable to high speed integrated amplifier | |
| CN111796622A (en) | Low ripple coefficient voltage stabilizing circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |