CN114203811A - 半导体装置以及其控制方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 263
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000012535 impurity Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 97
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
实施方式涉及半导体装置及其控制方法。半导体装置具备第一导电型的第一半导体层、设置在第一半导体层上的第二导电型的第二半导体层、选择性地设置在第二半导体层上的第一导电型的第三半导体层、选择性地设置在第二半导体层上并与第三半导体层并排的第二导电型的第四半导体层及第二导电型的第五半导体层。第一半导体层位于第二半导体层与第五半导体层之间。第四半导体层在与第二半导体层的上表面平行的平面内,第四半导体层的面积具有比第三半导体层的面积大的面积。半导体装置还具备:控制电极,设置在从第三半导体层的上表面至第一半导体层中的深度的沟道的内部;第一电极,与第三半导体层电连接;及第二电极,与第四半导体层电连接。
Description
本申请通过参照该基础申请而包括基础申请的全部内容。本申请将日本专利申请2020-157529号(申请日:2020年9月18日)作为基础申请而享有优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
实施方式涉及半导体装置以及其控制方法。
背景技术
构成逆变器等电力转换器的半导体装置被要求使针对短路电流等的耐破坏性提高。
发明内容
实施方式提供使耐破坏性提高了的半导体装置以及其控制方法。
实施方式涉及的半导体装置具备:第一导电型的第一半导体层;第二导电型的第二半导体层,设置在所述第一半导体层上;所述第一导电型的第三半导体层,选择性地设置在所述第二半导体层上;所述第二导电型的第四半导体层,选择性地设置在所述第二半导体层上,并与所述第三半导体层并排;以及第二导电型的第五半导体层。所述第一半导体层位于所述第二半导体层与所述第五半导体层之间。所述第四半导体层在与所述第二半导体层的上表面平行的平面内,所述第四半导体层的面积具有比所述第三半导体层的面积大的面积。所述半导体装置还具备:控制电极,设置在沟道的内部,所述沟道的深度为从所述第三半导体层的上表面至所述第一半导体层中;第一电极,与所述第三半导体层电连接;第二电极,与所述第四半导体层电连接;第三电极,与所述第五半导体层电连接;以及控制端子,与所述控制电极电连接。所述控制电极通过第一绝缘膜与所述第一半导体层、所述第二半导体层以及所述第三半导体层电绝缘。所述第二半导体层隔着所述第一绝缘膜与所述控制电极相对,所述第三半导体层与所述第一绝缘膜相接。
实施方式涉及的半导体装置的控制方法使经由所述第二电极与所述第四半导体层连接的电位比经由所述第一电极与所述第三半导体层连接的电位低。
附图说明
图1是表示实施方式涉及的半导体装置的示意剖视图。
图2(a)~(d)是表示实施方式涉及的半导体装置的示意俯视图。
图3是表示实施方式涉及的半导体装置的特性的图表。
图4是表示实施方式涉及的半导体装置的控制方法的时间图。
图5是表示实施方式的变形例涉及的半导体装置的控制方法的时间图。
图6(a)、(b)是表示比较例涉及的电力转换器的示意图。
具体实施方式
以下,参照附图对实施方式进行说明。对附图中的同一部分赋予同一编号而适当地省略其详细说明,对不同的部分进行说明。其中,附图是示意图或者概念图,各部分的厚度与宽度的关系、部分间的大小的比率等并不限定为一定与现实的相同。另外,即便在表示相同部分的情况下,也存在相互的尺寸、比率根据附图而被不同地表示的情况。
并且,使用各图中所示的X轴、Y轴以及Z轴来对各部分的配置以及构成进行说明。X轴、Y轴、Z轴相互正交,分别表示X方向、Y方向、Z方向。另外,存在将Z方向作为上方、将其相反方向作为下方来进行说明的情况。
图1是表示实施方式涉及的半导体装置1的示意剖视图。半导体装置1例如是IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)。
如图1所示,半导体装置1具备第一导电型的第一半导体层11、第二导电型的第二半导体层13、第一导电型的第三半导体层15、第二导电型的第四半导体层17、第二导电型的第五半导体层19、第一控制电极20以及第二控制电极30。以下,将第一导电型设为n型、将第二导电型设为p型来进行说明。
第一~第五半导体层例如为硅。第一半导体层11例如是n型基极层。第二半导体层13例如是p型基极层。第二半导体层13设置于第一半导体层11之上。
第三半导体层15例如是n型发射极层。第三半导体层15选择性地设置在第二半导体层13之上。第三半导体层15例如包含比第一半导体层11的第一导电型杂质浓度高的第一导电型杂质。
第四半导体层17例如是p型发射极层。第四半导体层17选择性地设置在第二半导体层13之上。第四半导体层17例如包含比第二半导体层13的第二导电型杂质浓度高的第二导电型杂质。第三半导体层15以及第四半导体层17在第二半导体层13上并排。
第五半导体层19例如是p型集电极层。第一半导体层11设置在第二半导体层13与第五半导体层19之间。
第一控制电极20例如是栅极电极。第一控制电极20例如是导电性的多晶硅,被设置在沟道GT1的内部。沟道GT1例如沿Z方向延伸,具有从第三半导体层15的上表面至第一半导体层11中的深度。另外,沟道GT1例如还沿Y方向延伸。第一控制电极20在沟道GT1的内部例如沿X方向以及Y方向延伸,并通过第一绝缘膜23而与第一半导体层11、第二半导体层13以及第三半导体层15电绝缘。第一绝缘膜23例如是栅极绝缘膜。第一绝缘膜23例如是硅氧化膜。
第一控制电极20具有延伸至第一半导体层11中的部分。第一半导体层11隔着第一绝缘膜23与第一控制电极20相对。另外,第二半导体层13隔着第一绝缘膜23与第一控制电极20相对。第三半导体层15与第一绝缘膜23相接。
第二控制电极30例如是场板(field plate)。第二控制电极30例如是导电性的多晶硅,被设置在沟道GT2的内部。沟道GT2例如沿Z方向延伸,具有从第四半导体层17的上表面至第一半导体层11中的深度。另外,沟道GT2例如还沿Y方向延伸。第二控制电极30在沟道GT2的内部例如沿X方向以及Y方向延伸,并通过第二绝缘膜33而与第一半导体层11、第二半导体层13以及第四半导体层17电绝缘。第二绝缘膜33例如是硅氧化膜。
第二控制电极30具有延伸至第一半导体层11中的部分。第一半导体层11隔着第二绝缘膜33与第二控制电极30相对。另外,第二半导体层13隔着第二绝缘膜33与第二控制电极30相对。第四半导体层17例如与第二绝缘膜33相接。
半导体装置1例如还具备第一电极ET1、第二电极ET2、第三电极CT以及控制端子GTE。
第一电极ET1与第三半导体层15电连接。第二电极ET2与第四半导体层17电连接。第三电极CT与第五半导体层19电连接。
控制端子GTE与第一控制电极20电连接。控制端子GTE例如经由设置于覆盖第一控制电极20的上端的绝缘膜25的接触孔与第一控制电极20电连接。绝缘膜25例如是硅氧化膜。
另外,第一控制电极20例如在Y方向的端具有延伸至沟道GT1的外侧的接触部(未图示),控制端子GTE与第一控制电极20的接触部电连接。
第二控制电极30与第一控制电极20独立地被控制。第二控制电极30例如被控制为与第一电极ET1成为同电位。第二控制电极30经由设置于覆盖其上端的绝缘膜35的接触孔(未图示)例如与第一电极ET1电连接。绝缘膜35例如是硅氧化膜。
另外,第二控制电极30也可以被控制为成为与第一电极ET1以及第一控制电极20不同的电位。
图2(a)~(d)是表示实施方式涉及的半导体装置1的示意俯视图。图2(a)~(d)是表示第三半导体层15以及第四半导体层17的配置的示意图。各图所示的CH1以及CH2表示了设置于未图示的层间绝缘膜的接触孔。
如图2(a)~(d)所示,第三半导体层15以及第四半导体层17在X-Y平面内并排配置。在X-Y平面内,第四半导体层17的面积被设定得比第三半导体层15的面积大。
第一电极ET1经由接触孔CH1与第三半导体层15电连接。第二电极ET2经由接触孔CH2与第四半导体层17电连接。
图3是表示实施方式涉及的半导体装置1的特性的图表。横轴表示在第一电极ET1与第三电极CT之间施加的集电极电压Vce。纵轴表示在第一电极ET1与第三电极CT之间流动的集电极电流Ic。
在该例子中,设第一电极ET1的电位Ve1为0V、在第一控制电极20与第一电极ET1之间施加的栅极电压Vg1为15V、在第二控制电极30与第一电极ET1之间施加的电压为0V。该情况下,第一控制电极20的阈值电压低于15V。
图3表示了相对于第一电极ET1的电位Ve1使第二电极ET2的电位Ve2变化的情况下的集电极电流Ic。例如,当使第二电极ET2的电位Ve2为0V时,图3所示的集电极电流Ic表示具有与第三半导体层15以及第四半导体层17双方电连接的发射极电极的通常的IGBT的特性。
如图3所示,随着使第二电极ET2的电位Vc2相对于第一电极ET1的电位Vc1(=0V)降低-0.5V、-2V以及-4V,集电极电流Ic变小。另外,若使第二电极ET2的电位Vc2为0.5V,则集电极电流Ic变大。
图4是表示实施方式涉及的半导体装置1的控制方法的时间图。图4表示了集电极电压Vce、集电极电流Ic、栅极电压Vg1、第一电极ET1的电位Ve1以及第二电极ET2的电位Ve2的时间变化。
这里,集电极电压Vce是被施加在第一电极ET1与第三电极CT之间的电压。集电极电流Ic是在第一电极ET1与第三电极CT之间流动的电流。另外,栅极电压Vg1是被施加在第一电极ET1与第一控制电极20之间的电压。
例如,在时间t1,以在第一电极ET1与第三电极CT之间施加有规定的集电极电压Vce的状态,使第一电极ET1与第一控制电极20之间的栅极电压Vg1从负电压向比阈值电压高的+15V变化。此时,第一电极ET1的电位Ve1以及第二电极ET2的电位Ve2都为0V。
通过第一控制电极20的电位,在第一绝缘膜23与第二半导体层13的界面感应出第一导电型的反转层,集电极电流Ic上升至规定的导通电流的电平。
接着,在比时间t1靠后的时间t2,例如若检测到因短路故障(参照图6)引起的集电极电压Vce的上升,则使第二电极ET2的电位Ve2降低至比第一电极ET1的电位Ve1低的电平,例如降低至-4V。由此,集电极电流Ic减少(参照图3)。例如,在集电极电压Vce超过了规定的阈值时检测到短路故障。
图6(a)以及(b)是表示比较例涉及的电力转换器2的示意图。图6(a)是电力转换器2的电路图。图6(b)是对电力转换器2在故障时的动作进行例示的时间图。
如图6(a)所示,电力转换器2例如是单相逆变器。电力转换器2包括半导体装置1A~1D。半导体装置1A~1D例如是发射极电极与n型发射极层以及p型发射极层双方电连接的通常的IGBT。
图6(b)表示了半导体装置1B的集电极电压Vce、集电极电流Ic以及栅极电压Vg的时间变化。
电力转换器2例如以在时间t1使半导体装置1B以及半导体装置1C成为导通状态、使半导体装置1A以及半导体装置1D成为截止状态的方式被控制。半导体装置1B的栅极电压Vg从截止电平上升至导通电平,例如上升至15V。与此相伴,集电极电流Ic上升至导通电流的电平,集电极电压降低至导通电压的电平。
例如,若设在时间t2半导体装置1A发生了短路故障,则集电极电压Vce例如上升至电源电压Vcc的电平。与此相伴,集电极电流Ic也上升,突入所谓的热失控的状态。其结果是,半导体装置1B也被破坏,存在电力转换器2达到爆发性破坏的情况。
与此相对,如果使用实施方式涉及的半导体装置1作为半导体装置1A~1D,则例如在检测到半导体装置1A的短路故障的情况下,在半导体装置1B中使第二电极ET2的电位Ve2降低至比第一电极ET1的电位Ve1低的电平。由此,能够抑制集电极电流Ic的增加、防止热失控。
此外,在上述的实施方式中,例示了在半导体装置1的导通状态下使第二电极ET2的电位Ve2降低的例子,但并不限定于此。例如,也可以在半导体装置1处于截止状态时,检测集电极电压Vce的上升,使第二电极ET2的电位Ve2降低。由此,能够抑制半导体装置1成为导通状态时的集电极电流Ic的电平、避免热失控。另外,使第二电极ET2的电位Ve2降低的时机的检测并不限定于集电极电压Vce的上升,例如也可以检测电力转换器2中的其他参数的变化来使第二电极ET2的电位Ve2降低。
图5是表示实施方式的变形例涉及的半导体装置1的控制方法的时间图。图5表示了集电极电压Vce、集电极电流Ic、栅极电压Vg1、第一电极ET1的电位Ve1以及第二电极ET2的电位Ve2的时间变化。
在该例子中,第二电极ET2的电位Ve2总是被维持为比第一电极ET1的电位Ve1低的电平,例如被维持为-4V。由此,在时间t1,即便使栅极电压Vg1从负电压上升至比阈值电压高的15V,在第二半导体层13与第一绝缘膜23的界面感应出第一导电型的反转层,集电极电流Ic也不会上升至原本的导通电流的电平。即,通过控制第二电极ET2的电位Ve2,能够稳定地抑制导通电流。
根据这样的控制方法,例如在半导体装置1的原本的导通电流的电平过高的情况下,能够抑制为所希望的电平。另外,存在因导通电流的增加而在栅极电压Vg1产生振动的情况(参照图6(b))。这样的振动并不限定于热失控,在通常的动作时的导通电流的电平过高的情况下也会产生。因此,通过使用图5所示的控制方法,还能够抑制栅极电压Vg1的振动。
对本发明的几个实施方式进行了说明,但这些实施方式只是例示,并不意图限定发明的范围。这些新的实施方式能够通过其他各种方式来实施,在不脱离发明主旨的范围能够进行各种省略、置换、变更。这些实施方式及其变形包含于发明的范围、主旨,并且包含于权利要求书所记载的发明和其等同的范围。
Claims (10)
1.一种半导体装置,其特征在于,具备:
第一导电型的第一半导体层;
第二导电型的第二半导体层,设置在所述第一半导体层上;
所述第一导电型的第三半导体层,选择性地设置在所述第二半导体层上;
所述第二导电型的第四半导体层,选择性地设置在所述第二半导体层上,并与所述第三半导体层并排,且在与所述第二半导体层的上表面平行的平面内,所述第四半导体层的面积比所述第三半导体层的面积大;
第二导电型的第五半导体层,所述第一半导体层位于所述第二半导体层与所述第五半导体层之间;
第一控制电极,设置在第一沟道的内部,所述第一沟道从所述第三半导体层的上表面延伸到所述第一半导体层中,所述第一控制电极通过第一绝缘膜与所述第一半导体层、所述第二半导体层以及所述第三半导体层电绝缘,所述第二半导体层隔着所述第一绝缘膜与所述第一控制电极相对,所述第三半导体层与所述第一绝缘膜相接;
第一电极,与所述第三半导体层电连接;
第二电极,与所述第四半导体层电连接;
第三电极,与所述第五半导体层电连接;以及
控制端子,与所述控制电极电连接。
2.根据权利要求1所述的半导体装置,其特征在于,
具备第二控制电极,设置在第二沟道的内部,所述第二沟道从所述第四半导体层的上表面延伸到所述第一半导体层中,所述第二控制电极通过第二绝缘膜与所述第一半导体层、所述第二半导体层以及所述第四半导体层电绝缘,所述第二半导体层隔着所述第二绝缘膜与所述第二控制电极相对,所述第四半导体层与所述第二绝缘膜相接。
3.根据权利要求2所述的半导体装置,其特征在于,
所述第二控制电极设置在与所述第一控制电极相邻的位置。
4.根据权利要求1所述的半导体装置,其特征在于,
所述第三半导体层包括与所述第一半导体层的第一导电型杂质的浓度相比浓度高的第一导电型杂质,
所述第四半导体层包括与所述第二半导体层的第二导电型杂质的浓度相比浓度高的第二导电型杂质。
5.一种半导体装置的控制方法,其特征在于,
所述半导体装置具备:
第一导电型的第一半导体层;
第二导电型的第二半导体层,设置在所述第一半导体层上;
所述第一导电型的第三半导体层,选择性地设置在所述第二半导体层上;
所述第二导电型的第四半导体层,选择性地设置在所述第二半导体层上,并与所述第三半导体层并排;
第二导电型的第五半导体层,所述第一半导体层位于所述第二半导体层与所述第五半导体层之间;
第一控制电极,设置在第一沟道的内部,所述第一沟道从所述第三半导体层的上表面延伸到所述第一半导体层中,所述第一控制电极通过第一绝缘膜与所述第一半导体层、所述第二半导体层以及所述第三半导体层电绝缘,所述第二半导体层隔着所述第一绝缘膜与所述第一控制电极相对,所述第三半导体层与所述第一绝缘膜相接;
第一电极,与所述第三半导体层电连接;
第二电极,与所述第四半导体层电连接;
第三电极,与所述第五半导体层电连接;以及
控制端子,与所述控制电极电连接,
所述控制方法使经由所述第二电极而与所述第四半导体层连接的电位比经由所述第一电极而与所述第三半导体层连接的电位低。
6.一种半导体装置的控制方法,其特征在于,
所述半导体装置具备:
第一导电型的第一半导体层;
第二导电型的第二半导体层,设置在所述第一半导体层上;
所述第一导电型的第三半导体层,选择性地设置在所述第二半导体层上;
所述第二导电型的第四半导体层,选择性地设置在所述第二半导体层上,并与所述第三半导体层并排;
第二导电型的第五半导体层,所述第一半导体层位于所述第二半导体层与所述第五半导体层之间;
第一控制电极,设置在第一沟道的内部,所述第一沟道从所述第三半导体层的上表面延伸到所述第一半导体层中,所述第一控制电极通过第一绝缘膜与所述第一半导体层、所述第二半导体层以及所述第三半导体层电绝缘,所述第二半导体层隔着所述第一绝缘膜与所述第一控制电极相对,所述第三半导体层与所述第一绝缘膜相接;
第一电极,与所述第三半导体层电连接;
第二电极,与所述第四半导体层电连接;
第三电极,与所述第五半导体层电连接;以及
控制端子,与所述控制电极电连接,
所述控制方法在所述第一电极与所述第三电极之间的电压超过了规定的值时,使经由所述第二电极而与所述第四半导体层连接的电位比经由所述第一电极而与所述第三半导体层连接的电位低。
7.根据权利要求6所述的半导体装置的控制方法,其特征在于,
在向所述控制端子与所述第一电极之间施加了比所述控制电极的阈值电压高的电压的期间,使与所述第四半导体层连接的电位比经由所述第一电极而与所述第三半导体层连接的电位低。
8.根据权利要求6所述的半导体装置的控制方法,其特征在于,
在使经由所述第二电极而与所述第四半导体层连接的电位比经由所述第一电极而与所述第三半导体层连接的电位低之前,将与所述第三半导体层相同的电位经由所述第二电极向所述第四半导体层供给。
9.根据权利要求6所述的半导体装置的控制方法,其特征在于,
所述半导体装置还具备与所述第一控制电极相邻的第二控制电极,所述第二控制电极设置在第二沟道的内部,所述第二沟道从所述第四半导体层的上表面延伸到所述第一半导体层中,所述第二控制电极通过第二绝缘膜与所述第一半导体层、所述第二半导体层以及所述第四半导体层电绝缘,所述第二半导体层隔着所述第二绝缘膜与所述第二控制电极相对,
所述控制方法以使所述第二控制电极的电位与所述第一电极的电位相同的方式进行控制。
10.根据权利要求6所述的半导体装置的控制方法,其特征在于,
所述半导体装置还具备与所述第一控制电极相邻的第二控制电极,所述第二控制电极设置在第二沟道的内部,所述第二沟道从所述第四半导体层的上表面延伸到所述第一半导体层中,所述第二控制电极通过第二绝缘膜与所述第一半导体层、所述第二半导体层以及所述第四半导体层电绝缘,所述第二半导体层隔着所述第二绝缘膜与所述第二控制电极相对,
所述控制方法以使所述第二控制电极的电位与所述第一电极的电位以及所述第一控制电极的电位不同的方式进行控制。
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