CN113986792B - Data bit width conversion method and communication equipment - Google Patents
Data bit width conversion method and communication equipment Download PDFInfo
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Abstract
The application provides a data bit width conversion method and communication equipment, wherein the method comprises the following steps: determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the buffer unit; splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits; when each receiving port receives data, the received data is stored into the storage address of the caching unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port. In the application, the input/output bit width conversion of different types of ports is realized by splitting the buffer unit and setting the control time sequence of the different types of ports, thereby improving the data bit width conversion efficiency and reducing the resource waste.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a data bit width conversion method and a communication device.
Background
Communication systems including various communication devices often involve various input/output interfaces, and the data bit widths between the various interfaces are required to be different, so that bit width conversion between the various interfaces is required.
With the development of communication technology, the transmission of high-speed signals is more and more commonly used in the design, and higher requirements are put on the conversion of data bit width, however, the existing bit width conversion device needs to set more caches, so that resources are wasted.
Disclosure of Invention
The application aims to provide a data bit width conversion method and communication equipment, so as to improve the data bit width conversion efficiency and reduce the resource waste.
The first aspect of the present application provides a data bit width conversion method, applied to a receiving module, where the receiving module includes a plurality of receiving ports and a buffer unit, and bit widths of at least two receiving ports in the plurality of receiving ports are different, the method includes:
Determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the buffer unit;
splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the minimum input bit width;
determining the write operation time sequence of each receiving port to the plurality of cache subunits;
When each receiving port receives data, the received data is stored into the storage address of the caching unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port.
The second aspect of the present application provides a data bit width conversion method, applied to a transmission module, where the transmission module includes a buffer unit and a plurality of transmission ports, and the bit widths of the plurality of transmission ports are the same, and the method includes:
Splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the same as that of the sending port;
determining the read operation time sequence of each sending port to the plurality of cache subunits;
determining a storage address and a target sending port of data to be sent in the cache unit;
and transmitting the data in the storage address according to the read operation time sequence corresponding to the target transmitting port.
The third aspect of the present application provides a data bit width conversion method, applied to a data bit width conversion device, where the data bit width conversion device includes a plurality of receiving ports, a buffer unit, and a plurality of transmitting ports, bit widths of at least two receiving ports in the plurality of receiving ports are different, bit widths of the plurality of transmitting ports are the same, and the method includes:
determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the buffer unit; splitting the cache unit into a plurality of first cache subunits with the same bit width, wherein the bit width of the first cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits;
splitting the buffer unit into a plurality of second buffer subunits with the same bit width, wherein the bit width of the second buffer subunits is the same as that of the sending port; determining the reading operation time sequence of each sending port to the plurality of second cache subunits;
When each receiving port receives data, the received data is stored into a target storage address of the cache unit applied by the receiving port according to a write operation time sequence corresponding to the receiving port;
Determining a target sending port of the data in the target storage address;
And transmitting the data in the target storage address according to the read operation time sequence corresponding to the target transmission port.
A fourth aspect of the present application provides a receiving module comprising:
the device comprises a plurality of receiving ports and a buffer unit, wherein the bit widths of at least two receiving ports in the plurality of receiving ports are different;
a determining unit, configured to determine a minimum input bit width according to bit widths of the plurality of receiving ports and bit widths of the buffer unit; splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits;
and the receiving unit is used for storing the received data into the storage address of the caching unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port when each receiving port receives the data.
A fifth aspect of the present application provides a transmitting module, including:
the buffer memory unit and the plurality of sending ports are the same in bit width;
a determining unit, configured to split the buffer unit into a plurality of buffer subunits with the same bit width, where the bit width of the buffer subunit is the same as the bit width of the transmitting port; determining the read operation time sequence of each sending port to the plurality of cache subunits;
A sending unit, configured to determine a storage address and a target sending port of data to be sent in the buffer unit; and transmitting the data in the storage address according to the read operation time sequence corresponding to the target transmitting port.
A sixth aspect of the present application provides a displacement width input-output device, comprising:
The device comprises a plurality of receiving ports, a buffer unit and a plurality of transmitting ports, wherein the bit widths of at least two receiving ports in the plurality of receiving ports are different, and the bit widths of the plurality of transmitting ports are the same;
A determining module, configured to determine a minimum input bit width according to bit widths of the plurality of receiving ports and bit widths of the buffer unit; splitting the cache unit into a plurality of first cache subunits with the same bit width, wherein the bit width of the first cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits;
The determining module is further configured to split the buffer unit into a plurality of second buffer subunits with the same bit width, where the bit width of the second buffer subunit is the same as the bit width of the transmitting port; determining the reading operation time sequence of each sending port to the plurality of second cache subunits;
The receiving module is used for storing the received data into a target storage address of the cache unit applied by the receiving port according to a write operation time sequence corresponding to the receiving port when each receiving port receives the data;
the sending module is used for determining a target sending port of the data in the target storage address; and transmitting the data in the target storage address according to the read operation time sequence corresponding to the target transmission port.
A seventh aspect of the present application provides a communication apparatus comprising the displacement width input output device described in the sixth aspect.
Compared with the prior art, the data bit width conversion method and the communication equipment provided by the application have the advantages that the buffer memory unit is split into the buffer memory subunits with the same bit width, the receiving port stores the received data into the storage address of the buffer memory unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port, and the sending port sends the data in the storage address according to the corresponding read operation time sequence. In the application, the input/output bit width conversion of different types of ports is realized by splitting the buffer unit and setting the control time sequence of the different types of ports, thereby improving the data bit width conversion efficiency and reducing the resource waste.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
Fig. 1 shows a schematic structural diagram of a conventional communication device;
FIG. 2 is a schematic diagram of a conventional message input/output device;
Fig. 3 shows a schematic diagram of a specific receiving module provided by the present application;
FIG. 4 illustrates one of the write operation timings of the receiving port provided by the present application;
FIG. 5 is a diagram showing a second write operation timing of the receiving port according to the present application;
FIG. 6 is a flow chart illustrating a method for converting data bit width according to the present application;
FIG. 7 is a schematic diagram of a specific transmitting module according to the present application;
FIG. 8 illustrates a read operation timing of a transmit port provided by the present application;
FIG. 9 is a flowchart illustrating another method of converting data bit widths according to the present application;
FIG. 10 is a schematic diagram of a specific displacement width input-output device provided by the present application;
FIG. 11 is a flow chart illustrating another method of converting data bit widths according to the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
In addition, the terms "first" and "second" etc. are used to distinguish different objects and are not used to describe a particular order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of a conventional communication device, and as shown in fig. 1, the communication device includes a front panel port (i.e., an input interface of the communication device), an FPGA (field programmable gate array), and a back panel port (i.e., an interconnection interface of the communication device). As shown in FIG. 1, the panel port has 10 input interfaces, supporting multiple rates, 25G, 10G, 5G/1G; the backplane port supports 4 sets of interconnect interfaces, each set supporting 10G. Serdes is an acronym for English Serializer/Deserializer, which is a time division multiplexed, point-to-point serial communication technique.
In the communication device, the FPGA realizes interface conversion: in the uplink direction, after receiving the message in the direction of the panel port, carrying out certain treatment, and then forwarding the message to the back panel port according to the forwarding specification; and in the downlink direction, receiving a message in the direction of the back plate port, and forwarding the message to the front plate port. The application discusses that the uplink panel port receives the packet and forwards the packet to the direction of the back panel port, and the downlink back panel port forwards the packet to the direction of the panel port, which is similar to the processing, and the description is omitted.
For the message received by the panel port, in general, after a complete message is formed, the message is parsed, and is forwarded to the corresponding back panel port according to the parsing result.
Fig. 2 is a schematic diagram of a conventional message input/output device.
In fig. 2, there are three types of MAC (physical layer interface) inputs. The input bit width of the low-rate MAC (receiving ports 0 to 7) is 32 bits wide, the input bit width of the medium-rate MAC (receiving port 8) is 256 bits wide, and the input bit width of the high-rate MAC (receiving port 9) is 512 bits wide.
Firstly, after each MAC receives external input, asynchronous transition is carried out firstly, and an interface clock is synchronized to an internal master clock; then, reading out data in a receiving FIFO (first in first out buffer) and performing bit width conversion; finally, the data is written into the receive packet level FIFO. The receive packet level FIFO requires that multiple packets can be packed, consuming relatively more memory resources.
And the dispatching module reads out the data in the receiving packet-level FIFO according to the polling mode and distributes the data to each sending port in the sending module.
And the sending module is used for storing the message into the packet-level FIFO to play a role of absorbing burst, simultaneously facilitating the following bit width conversion and clock domain conversion, and finally sending the message to a sending port for sending after the bit width conversion and asynchronous conversion.
The above prior art has the following disadvantages:
1) Two-level large message buffering is needed, and resource sharing is not achieved. For example, the first-level packet buffer can not absorb burst when no traffic exists in the 25G packet receiving direction.
2) The input needs to be firstly converted in bit width and then processed by other functions, so that more resources are wasted.
3) The output is also distributed first and then the shift width processing is performed, so that the logic resource consumption is relatively high for the function module of shift width.
In view of this, embodiments of the present application provide a data bit width conversion method, a receiving module, a transmitting module, a bit width input/output device, and a communication apparatus, which are described below with reference to the accompanying drawings.
The application provides a receiving module for a data receiving side of a deflection wide input/output device, which comprises:
The device comprises a plurality of receiving ports and a buffer unit, wherein the bit widths of at least two receiving ports in the plurality of receiving ports are different, and each receiving port corresponds to one receiving buffer;
a determining unit, configured to determine a minimum input bit width according to bit widths of the plurality of receiving ports and bit widths of the buffer unit; splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits;
and the receiving unit is used for storing the received data into the storage address of the caching unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port when each receiving port receives the data.
Referring to fig. 3, a schematic diagram of a specific receiving module provided by the present application is shown, wherein the receiving ports are macjrx 0-9, and 10 receiving ports are total, wherein the bit width of macjrx 0-7 is 32 bits wide, the bit width of macjrx 8 is 256 bits wide, and the bit width of macjrx 9 is 512 bits wide. The bit width of the buffer unit is 512 bits wide, that is, each memory address corresponds to 512 bits wide data. Each receiving port also corresponds to a receiving buffer (FIFO), as shown in fig. 3, and macjrx 0 to 9 correspond to receiving buffers 0 to 9, and each receiving port receives data, and stores the data in the receiving buffer first, and then waits for the write operation timing to reach the re-write unit.
The minimum input bit width of the mac_rx0 to 9 is 32 bits wide, and the buffer units need to be split according to the 32 bits wide, 512/32=16, and the total buffer units are split into 16 buffer subunits with 32 bits wide, and the 16 buffer subunits are respectively from 0 th block of RAM to 15 th block of RAM.
And then determining the write operation time sequence of each receiving port to the 0 th-15 th block RAM, wherein the constraint condition of the operation time sequence is to ensure that no packet is lost. Fig. 4 shows the write operation sequence from the 0 th receiving port to the 7 th receiving port according to the present application. The write operation timing of the 8 th receiving port and the 9 th receiving port provided by the present application is shown in fig. 5. In fig. 4 and 5, -0 is the 0 th receive port, -1 is the 1 st receive port, and so on. The write operation timing for each receiving port is determined in fig. 4 and 5.
Setting a T0-T15 timer, determining 16 time sequences, dividing the 16 time sequences into odd time sequences (such as T1, T3 and the like) and even time sequences (such as T0, T2 and the like), operating the odd-numbered row RAMs (such as 1 st, 3 rd and 5 th RAMs) at the odd time sequences by the first 8 receiving ports, and operating the even-numbered row RAMs (such as 2 nd, 4 th and 6 th RAMs) at the even time sequences. Each receiving port can finish a conversion operation with 32 to 512 bits wide by 16 time sequences with one period, thereby realizing write bit wide.
The application operates with the RAM divided into parity rows because there is also a receiving port 9 with bit width 512 that does not need to be bit-wide, and a receiving port 8 with bit width 256 that does need to be bit-wide. Dividing the RAM into parity rows operates to free up timing for the RAM for use by receive ports 8 and 9. The two ports, namely the receiving port 8 and the receiving port 9, operate the even line RAM at the odd timing and operate the odd line RAM at the even timing, and can operate 256 bits at most each time.
As shown in fig. 5, the first four timing 8 th receive ports (256 bits wide) occupy the RAM write bus, and the last four timing 9 th receive ports (512 bits wide) occupy the RAM write bus. The last 8 timings are repetition periods of the first 8 timings.
Fig. 6 shows a flowchart of a data bit width conversion method provided by the present application, where the method is applied to the receiving module provided by the foregoing embodiment, and the method includes:
S101, determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the buffer unit;
S102, splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the minimum input bit width;
s103, determining the write operation time sequence of each receiving port to the plurality of cache subunits;
and S104, when each receiving port receives data, storing the received data into the storage address of the caching unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port.
The receiving module and the data bit width conversion method applied to the receiving module provided by the application have the advantages that the same buffer unit is operated according to the port jump time sequence, so that the simultaneous conversion of a plurality of bit widths into one bit width is realized.
The application provides a transmitting module for a data transmitting side of a variable-width input-output device, which comprises:
the buffer memory unit and the plurality of sending ports are the same in bit width;
a determining unit, configured to split the buffer unit into a plurality of buffer subunits with the same bit width, where the bit width of the buffer subunit is the same as the bit width of the transmitting port; determining the read operation time sequence of each sending port to the plurality of cache subunits;
A sending unit, configured to determine a storage address and a target sending port of data to be sent in the buffer unit; and transmitting the data in the storage address according to the read operation time sequence corresponding to the target transmitting port.
Referring to fig. 7, a schematic diagram of a specific transmitting module provided by the present application is shown, wherein the transmitting ports are mactx 0-3, and total 4 transmitting ports, and the bit widths of mactx 0-3 are 128 bits wide. The bit width of the buffer unit is 512 bits wide, that is, each memory address corresponds to 512 bits wide data. As shown in fig. 7, each transmitting port waits for the read operation timing to arrive for transmitting the data in the re-read buffer unit.
The sending bit width of the mac_tx0 to 3 is 128 bits wide, and then the buffer units are split according to the 128 bits wide, 512/128=4, and are split into 4 buffer subunits with 128 bits wide, and the 4 buffer subunits are respectively from 0 block RAM to 3 block RAM.
And then determining the reading operation time sequence of each sending port to the 0 th-3 rd RAMs, wherein the constraint condition of the operation time sequence is to ensure that no packet is lost. Fig. 8 shows the timing sequence of the reading operation from the 0 th transmission port to the 3 rd transmission port according to the present application. In fig. 8, -0 is the 0 th transmission port, -1 is the 1 st transmission port, -2 is the 2 nd transmission port, -3 is the 3 rd transmission port. The timing of the read operation for each transmit port is determined in fig. 8.
Setting a T0-T3 timer, and determining 4 time sequences, wherein the specific time sequences are as follows as shown in FIG. 8:
At the 0 th time sequence, the read address of the 0 th RAM is distributed to the 0 th transmitting port, the read address of the 1 st RAM is distributed to the 3 rd transmitting port, the read address of the 2 nd RAM is distributed to the 2 nd transmitting port, and the read address of the 3 rd RAM is distributed to the 1 st transmitting port;
The 1 st time sequence, the 0 th RAM read address is distributed to the 1 st transmitting port, the 1 st RAM read address is distributed to the 0 th transmitting port, the 2 nd RAM read address is distributed to the 3 rd transmitting port, the 3 rd RAM read address is distributed to the 2 nd transmitting port;
The 2 nd time sequence, the read address of the 0 th RAM is distributed to the 2 nd transmitting port, the read address of the 1 st RAM is distributed to the 1 st transmitting port, the read address of the 2 nd RAM is distributed to the 0 th transmitting port, and the read address of the 3 rd RAM is distributed to the 3 rd transmitting port;
in the 3 rd time sequence, the read address of the 0 th block RAM is distributed to the 3 rd transmitting port, the read address of the 1 st block RAM is distributed to the 2 nd transmitting port, the read address of the 2 nd block RAM is distributed to the 1 st transmitting port, and the read address of the 3 rd block RAM is distributed to the 0 th transmitting port.
The transmitting module realizes the change of the bit width of the transmitting side from 512 natural to 128 through accurate time sequence control, and a special bit width conversion module is not needed. In the prior art, 4 groups of data with 512 bit width are read out respectively, and four modules with 512-128 turns are used for realizing the bit width conversion.
Fig. 9 shows a flowchart of a data bit width conversion method provided by the present application, where the method is applied to the sending module provided by the foregoing embodiment, and the method includes:
s201, splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the same as that of the sending port;
s202, determining a reading operation time sequence of each sending port to the plurality of cache subunits;
S203, determining a storage address and a target sending port of data to be sent in the cache unit;
s204, transmitting the data in the storage address according to the read operation time sequence corresponding to the target transmitting port.
The sending module and the data bit width conversion method applied to the sending module provided by the application operate the same buffer unit according to the port jump time sequence, realize bit width conversion, and compared with the prior art, the method does not need a special module to realize bit width conversion, thereby greatly saving resources.
The application also provides a deflection width input and output device, which comprises a receiving module and a transmitting module in the embodiment of the application; wherein the receiving module and the sending module share a buffer unit.
Referring to fig. 10, a schematic diagram of a specific variable-width input/output device according to the present application is shown. Because the receiving module and the transmitting module share one buffer unit, for the receiving module, the buffer units are split according to the width of 32 bits, 512/32=16, and the buffer units are split into 16 blocks of buffer subunits with the width of 32 bits; for the transmitting module, the buffer units are split according to 128 bit width, 512/128=4, and a total of the buffer units are split into 4 blocks of buffer subunits with 128 bit width.
In some embodiments of the present application, as shown in fig. 10, the variable-width input/output device further includes:
And the scheduling module is used for scheduling the storage address and the sending port of the data between the receiving module and the sending module. In fig. 10, 100 and 200 are information storage units that are needed by the scheduling module.
In some embodiments of the present application, as shown in fig. 10, the variable-width input/output device further includes:
and the address management module is used for recovering and initializing the storage address of the data. In fig. 10, 300 and 400 are information storage units that are required by the address management module.
The working principle of the displacement width input output device shown in fig. 10 is as follows:
and 10 receiving ports are provided, each receiving port operates the buffer unit according to the respective write time sequence, and independently applies for the respective address pointer queue, and stores the received MAC data into the storage address of the corresponding applied buffer unit. After the message is received, the storage address information corresponding to the message is written into the information storage unit 100, and the sending port information corresponding to the message is also written into the information storage unit 100.
The scheduling module schedules information in the information storage unit 100 and stores the information in the information storage unit 200 according to the transmission port information.
And the sending module reads out the packet information in the 4 sending port information storage units 200, acquires the storage addresses of the packets in the buffer units, and reads the storage addresses of the buffer units to obtain the sending packets according to the corresponding reading operation time sequence of the 0-3 sending ports. The four transmit ports read out at each timing are each exactly 128 bits wide.
And the sending module releases the storage address to the information storage unit 300 after the message sending is completed.
The address management module completes the initialization of the address pointer and distributes the storage address to the information storage unit 400; in addition, if there is a memory address already released in the information storage unit 300, it is also necessary to read out and store it in the information storage unit 400.
Fig. 11 shows a flowchart of a data bit width conversion method provided by the present application, where the method is applied to the variable bit width input/output device provided by the foregoing embodiment, and the method includes:
S301, determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the buffer unit; splitting the cache unit into a plurality of first cache subunits with the same bit width, wherein the bit width of the first cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits;
S302, splitting the buffer unit into a plurality of second buffer subunits with the same bit width, wherein the bit width of the second buffer subunits is the same as that of the sending port; determining the reading operation time sequence of each sending port to the plurality of second cache subunits;
s303, when each receiving port receives data, storing the received data into a target storage address of the cache unit applied by the receiving port according to a write operation time sequence corresponding to the receiving port;
s304, determining a target sending port of the data in the target storage address;
S305, transmitting the data in the target storage address according to the read operation time sequence corresponding to the target transmission port.
The shift width input/output device and the data bit width conversion method applied to the shift width input/output device provided by the application furthest realize the sharing of the cache units and avoid the waste of resources. The output and input do not need a special bit width conversion module to carry out bit width conversion, thereby greatly saving resources.
The embodiment of the application also provides communication equipment which comprises the variable-width input-output device in the embodiment of the application.
Finally, it should be noted that: the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application, and are intended to be included within the scope of the appended claims and description.
Claims (9)
1. A data bit width conversion method applied to a receiving module, wherein the receiving module comprises a plurality of receiving ports and a buffer unit, and bit widths of at least two receiving ports in the plurality of receiving ports are different, the method comprises the following steps:
Determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the buffer unit;
splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the minimum input bit width;
Determining the write operation time sequence of each receiving port to the plurality of cache subunits; dividing a write operation time sequence of one period into an odd time sequence and an even time sequence, dividing a plurality of cache subunits split by the cache units into odd lines and even lines so as to realize the write operation of the cache units by a port jump time sequence, and finishing the conversion operation from the minimum input bit width to the bit width of the cache units by each receiving port through the write operation time sequence of one period;
When each receiving port receives data, the received data is stored into the storage address of the caching unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port.
2. The data bit width conversion method is applied to a sending module, wherein the sending module comprises a buffer unit and a plurality of sending ports, and the bit widths of the plurality of sending ports are the same, and is characterized in that the method comprises the following steps:
Splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the same as that of the sending port;
determining the reading operation time sequence of each sending port to the plurality of cache subunits so as to realize the reading operation of the cache units in the sub-port jump time sequence; each sending port completes the conversion operation from the bit width of the buffer unit to the bit width of the sending port through the reading operation time sequence of one period;
determining a storage address and a target sending port of data to be sent in the cache unit;
and transmitting the data in the storage address according to the read operation time sequence corresponding to the target transmitting port.
3. The data bit width conversion method is applied to a bit width conversion input/output device, the bit width conversion input/output device comprises a plurality of receiving ports, a buffer unit and a plurality of sending ports, the bit widths of at least two receiving ports in the plurality of receiving ports are different, and the bit widths of the plurality of sending ports are the same, and the method is characterized by comprising the following steps:
Determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the buffer unit; splitting the cache unit into a plurality of first cache subunits with the same bit width, wherein the bit width of the first cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits; dividing a write operation time sequence of one period into an odd time sequence and an even time sequence, dividing a plurality of cache subunits split by the cache units into odd lines and even lines so as to realize the write operation of the cache units by a port jump time sequence, and finishing the conversion operation from the minimum input bit width to the bit width of the cache units by each receiving port through the write operation time sequence of one period;
Splitting the buffer unit into a plurality of second buffer subunits with the same bit width, wherein the bit width of the second buffer subunits is the same as that of the sending port; determining the reading operation time sequence of each sending port to the plurality of second cache subunits so as to realize the reading operation of the cache units by the port-separated jump time sequence; each sending port completes the conversion operation from the bit width of the buffer unit to the bit width of the sending port through the reading operation time sequence of one period;
When each receiving port receives data, the received data is stored into a target storage address of the cache unit applied by the receiving port according to a write operation time sequence corresponding to the receiving port;
Determining a target sending port of the data in the target storage address;
And transmitting the data in the target storage address according to the read operation time sequence corresponding to the target transmission port.
4. A receiving module, comprising:
the device comprises a plurality of receiving ports and a buffer unit, wherein the bit widths of at least two receiving ports in the plurality of receiving ports are different;
A determining unit, configured to determine a minimum input bit width according to bit widths of the plurality of receiving ports and bit widths of the buffer unit; splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of the cache subunits is the minimum input bit width; determining the write operation time sequence of each receiving port to the plurality of cache subunits; dividing a write operation time sequence of one period into an odd time sequence and an even time sequence, dividing a plurality of cache subunits split by the cache units into odd lines and even lines so as to realize the write operation of the cache units by a port jump time sequence, and finishing the conversion operation from the minimum input bit width to the bit width of the cache units by each receiving port through the write operation time sequence of one period;
and the receiving unit is used for storing the received data into the storage address of the caching unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port when each receiving port receives the data.
5. A transmission module, comprising:
the buffer memory unit and the plurality of sending ports are the same in bit width;
A determining unit, configured to split the buffer unit into a plurality of buffer subunits with the same bit width, where the bit width of the buffer subunit is the same as the bit width of the transmitting port; determining the reading operation time sequence of each sending port to the plurality of cache subunits so as to realize the reading operation of the cache units in the sub-port jump time sequence; each sending port completes the conversion operation from the bit width of the buffer unit to the bit width of the sending port through the reading operation time sequence of one period;
A sending unit, configured to determine a storage address and a target sending port of data to be sent in the buffer unit; and transmitting the data in the storage address according to the read operation time sequence corresponding to the target transmitting port.
6. A displacement width input/output device is characterized by comprising:
the receiving module of claim 4;
The transmit module of claim 5;
Wherein the receiving module and the sending module share a buffer unit.
7. The variable displacement width input output device of claim 6, further comprising:
And the scheduling module is used for scheduling the storage address and the sending port of the data between the receiving module and the sending module.
8. The displacement width input output device according to claim 6 or 7, further comprising:
and the address management module is used for recovering and initializing the storage address of the data.
9. A communication apparatus comprising the displacement width input-output device according to any one of claims 6 to 8.
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