CN112600567A

CN112600567A - High-speed multichannel parallel-serial conversion circuit

Info

Publication number: CN112600567A
Application number: CN202011510470.4A
Authority: CN
Inventors: 杨海玲
Original assignee: Shanghai Weijing Electronic Technology Co ltd
Current assignee: Shanghai Weijing Electronic Technology Co ltd
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2021-04-02
Anticipated expiration: 2040-12-18
Also published as: CN112600567B

Abstract

The invention provides a high-speed multi-channel parallel-serial conversion circuit, which is characterized in that a conversion pulse signal and a half-rate orthogonal clock signal are driven and copied by M parallel-serial buffer units to generate M conversion control signals and M half-rate control signals; the M paths of parallel data signals are respectively accessed to the input ends of the M half-rate parallel-serial conversion circuits, the output ends of the M half-rate parallel-serial conversion circuits output M primary serial signals, the primary serial signals are connected to the input end of a selector together, the control end of the selector is accessed to the half-rate orthogonal clock signal, and the output end of the selector outputs a serialized signal. By generating the half-rate quadrature clock and driving the clock to each channel, the signal interference problem of a clock driving module and the consumption of dynamic current are reduced, and the absolute matching of paths is ensured, so that the circuit can realize higher time sequence performance, and the method has obvious significance.

Description

High-speed multichannel parallel-serial conversion circuit

Technical Field

The invention relates to the technical field of power supply, in particular to a high-speed multi-channel parallel-serial conversion circuit.

Background

High-speed digital systems are often used for parallel processing of multi-bit data, and when data is exchanged to the outside, serial IO with high-speed driving capability is used for high-bandwidth data transmission, which involves the application of a parallel-serial conversion circuit that converts multi-bit bus data into a high-speed serial bit stream.

In order to increase the IO bandwidth, the prior art adopts a multi-channel serial interface mode, fig. 1 is a multi-channel parallel-serial conversion circuit based on asynchronous FIFO (First Input First output) in the prior art, as shown in fig. 1, the multi-channel parallel-serial conversion circuit in the prior art generally includes a reset synchronization circuit, M-channel asynchronous FIFOs and a balance tree, and the working principle of the multi-channel parallel-serial conversion circuit is that after all parallel-serial conversion is realized, all parallel-serial conversion circuits are driven to the positions of all channels, the positions of different channels are limited by the layout width of the IO circuit, the longest of the channels may have a driving length of several millimeters, and all timing alignment is balanced through automatic design software. In the structure, a write-in clock DCLK of the digital FIFO is a system clock frequency, a read-out clock SCLK of the digital FIFO is a serial interface clock frequency which is generally N times of the DCLK, and the digital FIFO needs to work at N × T_DCLKResulting in tight timing constraints for the FIFO. Moreover, after the M digital FIFOs complete the parallel-to-serial conversion, M channels of data signals need to be driven to the positions corresponding to the interfaces IO, and crosstalk between lines and large dynamic driving current consumption may occur during the transmission process, resulting in signal misalignment between channels and signal quality degradation.

The realization of the circuit utilizes automatic design software to solve the time sequence alignment problem among multi-channel serial data, cannot realize absolute matching of paths, is difficult to ensure alignment at all corners of PVT, and can form larger dynamic current when long-distance driving transmission is carried out on the multi-channel serial data, so that the problem of more serious signal crosstalk is easy to occur, thereby influencing the interface rate; and, the finally realized parallel-to-serial conversion rate also depends on the speed of the used basic unit library, and the requirement of the working speed of a high-speed digital system is difficult to achieve. In addition, the DDR clock is generally output by dividing the serial clock provided by the system by two, and since the path of the DDR clock is not consistent with the data serialization path, timing alignment is difficult, which causes a parallel-to-serial conversion circuit implemented by a digital circuit to restrict the IO bandwidth of the system.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and to provide a high-speed multi-channel parallel-serial conversion circuit.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a high speed multi-channel parallel-to-serial conversion circuit, comprising: the input end of the half-rate orthogonal sampling clock generation module is connected with a system reset signal, a parallel clock signal and a serial clock signal, and the output end of the half-rate orthogonal sampling clock generation module outputs a conversion pulse signal and a half-rate orthogonal clock signal;

the clock driving module is coupled with the half-rate orthogonal sampling clock generating module and comprises M cascaded parallel-serial buffer units, the conversion pulse signals and the half-rate orthogonal clock signals are driven and copied by the M parallel-serial buffer units to generate M conversion control signals and M half-rate control signals, and M corresponds to the number of output channels and is an integer larger than 1;

a half-rate parallel-serial conversion module coupled to the clock driving module, and including M half-rate parallel-serial conversion circuits and a selector correspondingly coupled to the M parallel-serial buffer units, where input ends of the M half-rate parallel-serial conversion circuits access the M conversion control signals, the M half-rate control signals, and the M parallel data signals, and output ends thereof output M primary serial signals, the primary serial signals are commonly connected to an input end of the selector, a control end of the selector accesses the half-rate orthogonal clock signal, and an output end thereof outputs a serialized signal; wherein the content of the first and second substances,

the path lengths of the M parallel-serial buffer units are the same;

the rising edge of the half-rate quadrature clock signal is used for serial sampling of even bits of the parallel data signal, the falling edge is used for serial sampling of odd bits of the parallel data signal, the period of the conversion pulse signal is equal to the period of the sampling clock of the parallel data signal, and the serial signal is aligned with the edge of the half-rate quadrature clock signal.

Preferably, the half-rate quadrature sampling clock generating module further outputs a half-rate clock signal, the half-rate quadrature sampling clock generating module includes a reset synchronizing circuit, a conversion pulse generating circuit and a quadrature clock generating circuit, an input end of the reset synchronizing circuit is connected to the system reset signal, the parallel clock signal and the serial clock signal, the system reset signal is synchronized by the parallel clock signal and the serial clock signal respectively and then outputs a synchronous reset signal, the synchronous reset signal is output to a reset end of the conversion pulse generating circuit and a reset end of the quadrature clock generating circuit through an output end of the reset synchronizing circuit, the serial clock signal is input to the conversion pulse generating circuit and the quadrature clock generating circuit, and the synchronous reset signal outputs a conversion pulse signal after the conversion pulse generating circuit is synchronized by the N-frequency division and the serial clock signal, the synchronous reset signal outputs the half-rate clock signal after the quadrature clock generating circuit is subjected to frequency division by two and is synchronous with the serial clock signal, the half-rate clock signal outputs the half-rate quadrature clock signal after being synchronous with the serial clock signal, and the phase of the half-rate quadrature clock signal is later than the phase of the half-rate clock signal by 90 degrees.

Preferably, the reset synchronization circuit comprises a first reset D flip-flop and a second reset D flip-flop coupled; the data end of the first reset D trigger is connected with the system reset signal, the clock end of the first reset D trigger is connected with the parallel clock signal, the output end of the first reset D trigger outputs a primary synchronous signal to the data end of the second reset D trigger, the clock end of the second reset D trigger is connected with the serial clock signal, and the primary synchronous signal is synchronized by the serial clock signal and then outputs the synchronous reset signal.

Preferably, the conversion pulse generating circuit comprises a first frequency divider, a first synchronous D flip-flop, a second synchronous D flip-flop, a third synchronous D flip-flop and an and gate; the clock ends of the first frequency divider, the first synchronous D trigger and the third synchronous D trigger are connected with the serial clock signal together, the reset zero clearing ends of the first synchronous D trigger, the second synchronous D trigger and the third synchronous D trigger are connected with the primary synchronous signal, the reset end of the first frequency divider is connected with the synchronous reset signal, the output end of the first frequency divider outputs a frequency division signal to the data input end of the first synchronous D trigger, the output end of the first synchronous D trigger outputs a primary synchronous signal to the data input end of the second synchronous D trigger and the first input end of the AND gate, the output end of the second synchronous D trigger outputs a secondary synchronous signal to the second input end of the AND gate, and the output end of the AND gate outputs a conversion signal to the data input end of the third synchronous D trigger, and the output end of the third synchronous D trigger outputs the conversion pulse signal.

Preferably, the secondary synchronization signal is an inverted signal lagging behind the primary synchronization signal by one serial clock cycle.

Preferably, the quadrature clock generation circuit includes a second frequency divider, a first quadrature D flip-flop, and a second quadrature D flip-flop; the clock ends of the second frequency divider, the first orthogonal D trigger and the second orthogonal D trigger are jointly connected with the serial clock signal, the reset zero clearing ends of the first orthogonal D trigger and the second orthogonal D trigger are connected with the primary synchronous signal, the reset end of the second frequency divider is connected with the synchronous reset signal, the output end of the second frequency divider outputs a frequency-divided signal to the data input end of the first orthogonal D trigger, the output end of the first orthogonal D trigger outputs the half-rate clock signal to the data input end of the second orthogonal D trigger, and the output end of the second orthogonal D trigger outputs the half-rate orthogonal clock signal.

Preferably, the DDR clock generation circuit is further included, and the half-rate quadrature clock signal is driven and output to the DDR clock generation circuit through the buffer unit.

Preferably, the DDR interface clock generating circuit includes a DDR selector, a control end of the DDR selector is connected to the half-rate clock signal, a first input end of the DDR selector is connected to the low level, a second input end of the DDR selector is connected to the high level, an output end of the DDR selector outputs a DDR clock signal, and phases of the DDR clock signal and the half-rate clock signal are aligned.

Preferably, the structure of the buffer unit includes an inverter structure or a CML structure.

Preferably, the half-rate parallel-to-serial conversion circuit includes a first conversion circuit, a second conversion circuit and a conversion selector coupled to each other, output terminals of the first conversion circuit and the second conversion circuit are respectively connected to an input terminal of the selector, an output terminal of the first conversion circuit outputs a first conversion signal, an output terminal of the second conversion circuit outputs a second conversion signal, an input terminal of the selector is respectively connected to the first conversion signal and the second conversion signal, a control terminal is connected to the half-rate quadrature clock signal, and an output terminal outputs the serialized signal; wherein the content of the first and second substances,

the half-rate quadrature clock signal is at a low level and the serialized signal is the first converted signal; the half-rate quadrature clock signal is at a high level and the serialized signal is the second converted signal.

It can be seen from the above technical solutions that, the present invention provides a high-speed multi-channel parallel-to-serial conversion circuit, where the generation of the conversion pulse signal, the half-rate clock signal, and the half-rate orthogonal clock signal and the delay between the rising edges of the parallel clock signals are maintained within a number of serial clock cycles, and are all clock-synchronized with the serial clock signals, thereby implementing control of the internal sampling timing. Meanwhile, by generating a half-rate quadrature clock and driving the clock to each channel, the signal interference problem of a clock driving module and the consumption of dynamic current are reduced, and the absolute matching of paths is ensured, so that the circuit can realize higher time sequence performance. In addition, the half-rate parallel-serial conversion module realizes a half-rate architecture through the coupled first conversion circuit, the second conversion circuit and the conversion selector, further reduces dynamic current consumption, is favorable for better time sequence alignment of a clock channel and a data channel, and has remarkable significance.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a multi-channel parallel-serial conversion circuit based on asynchronous FIFO in the prior art

FIG. 2 is a schematic diagram of a high-speed multi-channel parallel-to-serial conversion circuit according to an embodiment of the present invention

FIG. 3 is a block diagram of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention

FIG. 4 is a timing diagram of an embodiment of a conversion control signal generating circuit according to the present invention

FIG. 5 is a timing diagram of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention

FIG. 6 is a schematic diagram of clock tree balancing according to an embodiment of the present invention

FIG. 7 is a diagram of a half-rate serializer module according to an embodiment of the invention

FIG. 8 is a timing diagram corresponding to the half rate parallel to serial conversion module of FIG. 7

FIG. 9 is a diagram of a DDR clock generation circuit according to an embodiment of the invention

Detailed Description

In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.

In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.

To make the objects, technical solutions and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention is made with reference to the accompanying drawings, and fig. 2 shows a schematic diagram of a high-speed multi-channel parallel-serial conversion circuit according to an embodiment of the present invention. The high-speed multichannel parallel-serial conversion circuit includes: the device comprises a half-rate quadrature sampling clock generation module 1, a clock driving module 2 and a half-rate parallel-serial conversion module 3.

In this embodiment, the half-rate quadrature sampling clock generating module 1 is coupled to the clock driving module 2, and has an input terminal connected to the system reset signal RST, the parallel clock signal DCLK and the serial clock signal SCLK, and an output terminal outputting the conversion pulse signal DIV _ SEL, the half-rate clock signal DDRCLK _ I and the half-rate quadrature clock signal DDRCLK _ Q to the clock driving module 2. The delay between the generation of the conversion pulse signal DIV _ SEL, the half-rate clock signal, and the half-rate quadrature clock signal and the rising edge of the parallel clock signal DCLK is maintained within a number of serial clock cycles and is clock-synchronized with the serial clock signal, thereby achieving control of the internal sampling timing. In another embodiment, the output terminal of the rate quadrature sampling clock generation block 1 outputs a conversion pulse signal DIV _ SEL and a half-rate quadrature clock signal DDRCLK _ Q to the clock driving block 2.

In this embodiment, the clock driving module 2 accesses the conversion pulse signal DIV _ SEL, the half-rate clock signal DDRCLK _ I, and the half-rate quadrature clock signal DDRCLK _ Q, and outputs a conversion control signal DIV _ SEL < M-1:0>, a half-rate control signal DDRCLK _ Q < M-1:0>, and a half-rate clock signal DDRCLK _ I. Wherein M is an integer greater than 1 and represents the number of high-speed IO data channels.

As shown in fig. 2, in this embodiment, the clock driving module 2 includes M cascaded parallel-serial buffer units (not shown), the path lengths of the M parallel-serial buffer units are the same, and M is an integer greater than 1 corresponding to the number of output channels. The conversion pulse signal DIV _ SEL and the half-rate quadrature clock signal DDRCLK _ Q are driven and copied by the M parallel-serial buffer units to generate M paths of conversion control signals and M paths of half-rate control signals, and the conversion control signals DIV _ SEL < M-1:0> and the half-rate control signals DDRCLK _ Q < M-1:0> are output to the input end of the half-rate parallel-serial conversion module 3. The high-speed multi-channel parallel-serial conversion circuit can also comprise 1 DDR clock generation circuit 4 according to a serial IO protocol used by a system if the system supports forward clock transmission; if the system does not support forward clock transfer, then no DDR interface clock generation circuit is needed. In this embodiment, the half-rate clock signal DDRCLK _ I is driven by 1 clock buffer unit with the same path length as the parallel-serial buffer unit and then output to the input terminal of the DDR clock generation circuit 4.

The half-rate parallel-serial conversion module 3 comprises M half-rate parallel-serial conversion circuits and a selector which are correspondingly coupled with the M parallel-serial buffer units, M paths of parallel data signals D0< N-1:0> -DM-1 < N-1:0> are respectively connected to the input end of the M paths of half-rate parallel-serial conversion circuits 3, N is an integer larger than 1 and represents the bit width of the parallel data signals, and M primary serial signals S < M-1:0> are output by the output end 3 of the M paths of half-rate parallel-serial conversion circuits.

Fig. 3 is a schematic diagram of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention, and as shown in fig. 3, the half-rate quadrature sampling clock generation circuit 1 includes a reset synchronization circuit 11, a transition pulse generation circuit 12, and a quadrature clock generation circuit 13. The system reset signal RST is respectively synchronized by a parallel clock signal DCLK and a serial clock signal SCLK and then outputs a synchronous reset signal RST _ SYN, the synchronous reset signal RST _ SYN is output to the reset terminal of the conversion pulse generation circuit 12 and the reset terminal of the quadrature clock generation circuit 13 through the output terminal of the reset synchronization circuit 11, the serial clock signal SCLK is input to the conversion pulse generation circuit and the quadrature clock generation circuit, the synchronous reset signal RST _ SYN is output by the conversion pulse generation circuit after being subjected to N frequency division and synchronized by the serial clock signal SCLK, the synchronous reset signal RST _ SYN is output by the quadrature clock generation circuit after being subjected to two frequency division and synchronized by the serial clock signal SCLK, the half-rate clock signal DDRCLK _ I is output by the half-rate clock signal DDRCLK _ Q after being synchronized by the serial clock signal SCLK, the half rate quadrature clock signal DDRCLK _ Q is later in phase than the half rate clock signal by 90 °, with rising edges of the half rate quadrature clock signal DDRCLK _ Q being used for serialized sampling of even bits of the parallel data signal and falling edges being used for serialized sampling of odd bits of the parallel data signal.

As shown in fig. 3, the input terminal of the reset synchronization circuit 11 is connected to the system reset signal RST, the parallel clock signal DCLK and the serial clock signal SCLK, wherein the system reset signal RST is synchronized with the parallel clock signal DCLK to control the start of the parallel data serialization, and then synchronized with the serial clock signal SCLK to generate a synchronous reset signal RST _ SYN having a timing relationship with the parallel clock signal DCLK and the serial clock signal SCLK, respectively, the synchronous reset signal RST _ SYN is connected to the reset terminals of the transition pulse generation circuit and the quadrature clock generation circuit to control the generation of the transition pulse signal DIV _ SEL, the half-rate clock signal DDRCLK _ I and the half-rate quadrature clock signal DDRCLK _ Q, respectively, and the delay between the generation of the transition pulse signal DIV _ SEL, the half-rate clock signal and the half-rate quadrature clock signal and the rising edge of the parallel clock signal DCLK remains several serial clock signals DCLK And in the clock period, the clock period and the serial clock signal are in clock synchronization, so that the control of the internal sampling time sequence is realized.

The reset synchronization circuit 11 comprises a first reset D flip-flop and a second reset D flip-flop which are coupled; the data terminal of the first reset D flip-flop is connected with the system reset signal RST, the clock terminal is connected with the parallel clock signal DCLK, the output terminal outputs a primary synchronization signal RST _1 to the data terminal of the second reset D flip-flop, the clock terminal of the second reset D flip-flop is connected with the serial clock signal SCLK, the primary synchronization signal RST _1 is synchronized by the serial clock signal SCLK and then outputs a synchronization reset signal RST _ SYN, wherein the clock cycle of the parallel clock signal DCLK is T_DCLKThe clock period of the serial clock signal SCLK is T_SCLK。

The switching pulse generating circuit 12 includes a first frequency divider 121, a first synchronous D flip-flop, a second synchronous D flip-flop, a third synchronous D flip-flop, and an and gate. In this embodiment, the first frequency divider is an N-frequency divider, N corresponds to the number of bits input to the parallel bus, and N is an integer greater than 1. The first mentionedThe clock ends of the frequency divider 121, the first synchronous D flip-flop and the third synchronous D flip-flop are commonly connected to the serial clock signal SCLK, the reset zero ends of the first synchronous D flip-flop, the second synchronous D flip-flop and the third synchronous D flip-flop are connected to the primary synchronous signal RST _1, the reset end of the first frequency divider is connected to the synchronous reset signal, the serial clock signal SCLK generates a signal frequency division signal div _ n synchronized with the serial clock signal SCLK after passing through the first frequency divider, and the output end of the first frequency divider outputs the frequency division signal div _ n. For a system with the parallel data bit width of N bits, T is satisfied_DCLK＝N*T_SCLKAnd the synchronous reset signal controls the phase difference between the rising edge of the frequency division signal div _ n and the rising edge of the parallel clock signal DCLK to be kept within 1-2 serial clock cycles.

Fig. 4 is a timing diagram corresponding to an embodiment of the conversion control signal generation circuit according to the invention, please refer to fig. 3 and fig. 4 in combination, where the frequency-divided signal div _ n is output to the data input terminal of the first synchronous D flip-flop, the output terminal of the first synchronous D flip-flop outputs a primary synchronization signal div _ syn _0 to the data input terminal of the second synchronous D flip-flop and the first input terminal of the and gate, the output terminal of the second synchronous D flip-flop outputs a secondary synchronization signal div _ syn _1 to the second input terminal of the and gate, and the secondary synchronization signal div _ syn _1 is an inverted signal delayed from the primary synchronization signal div _ syn _0 by 1 clock cycle of the serial clock signal SCLK. And the output end of the AND gate outputs a conversion signal to the data input end of the third synchronous D trigger. The conversion signal is a signal with a pulse width of 1 SCLK period and a period of N SCLK periods, the conversion signal is connected to an input end of the third synchronous D flip-flop and is synchronously sampled by the SCLK periods, an output end of the third synchronous D flip-flop outputs a conversion pulse signal DIV _ SEL, the period of the conversion pulse signal DIV _ SEL is equal to the period of the parallel data sampling clock signal, and the serialized signal is aligned with the edge of the half-rate orthogonal clock signal.

This embodiment represents only one implementation manner of the present invention, in which the first frequency divider can freely select various circuit implementation structures, and the internal synchronization unit can flexibly adjust according to the timing constraints of the actual circuit.

In the present embodiment, the quadrature clock generation circuit 13 includes a second frequency divider, a first quadrature D flip-flop, and a second quadrature D flip-flop.

As shown in fig. 3, the serial clock signal SCLK is accessed to the clock terminals of the second frequency divider, the first quadrature D flip-flop, and the second quadrature D flip-flop together, the primary synchronization signal is accessed to the reset zero terminals of the first quadrature D flip-flop and the second quadrature D flip-flop, the synchronization reset signal is accessed to the reset terminal of the second frequency divider, and the serial clock signal SCLK generates a cycle N × T through the second frequency divider_SCLKThe output terminal of the second frequency divider is output to the data input terminal of the first quadrature D flip-flop, and the phase difference between the rising edge of the frequency-divided signal and the rising edge of the parallel clock signal DCLK is kept within 1 SCLK period. Fig. 5 is a timing diagram of a half-rate quadrature sampling clock generation module according to an embodiment of the present invention, as shown in fig. 5, the two-frequency-divided signal is synchronously sampled by SCLK, the two-frequency-divided signal generates a half-rate clock signal DDRCLK _ I after being synchronized by the serial clock signal SCLK, the output terminal of the first quadrature D flip-flop outputs the half-rate clock signal DDRCLK _ I to the data input terminal of the second quadrature D flip-flop, and then is synchronously sampled by the reverse clock of the serial clock signal SCLK, that is, the half-rate clock signal DDRCLK _ I obtains a quadrature half-rate clock signal DDRCLK _ Q with a phase difference of 90 °, the half-rate clock signal DDRCLK _ I is synchronized by the reverse phase of SCLK to obtain the half-rate quadrature clock signal DDRCLK _ Q, and the output terminal of the second quadrature D flip-flop outputs the half-rate quadrature clock signal DDRCLK _ Q.

In this embodiment, the clock driving circuit 2 is a balanced tree, and the path lengths between M data channels and clock channels from the half-rate quadrature sampling clock generating circuit 1 and the number of parallel-serial buffer units are precisely matched, so as to achieve precise matching.

Fig. 6 is a schematic diagram of clock tree balancing according to an embodiment of the present invention, as shown in fig. 6, in this embodiment, the clock driving circuit 2 adopts a balanced binary tree structure to implement absolute balance between the paths, the clock driving module 2 includes M cascaded parallel-serial buffer units (not shown), the conversion pulse signal DIV _ SEL and the half-rate quadrature clock signal are driven by the M parallel-serial buffer units and copied to generate M conversion control signals and M half-rate control signals, where the number of buffer units on each driving path can be flexibly set according to load conditions and timing requirements. The buffer circuit can be realized in various forms, the structure of the buffer unit comprises an inverter structure or a CML structure, and a common realization circuit is the inverter structure. The structure of the buffer unit can flexibly set the structure of the driving circuit according to the frequency and the load condition of the driving signal, and is not limited to the structure of the inverter or the structure of the CML. The invention reduces the signal interference problem and the consumption of dynamic current on the balance tree by advancing the balance tree, firstly generating the half-rate orthogonal clock signal DDRCLK _ Q and driving to each channel, and simultaneously, the clock tree designed by a full customization method ensures the absolute matching of paths, so that the circuit can realize higher time sequence performance.

The half-rate parallel-serial conversion module comprises M half-rate parallel-serial conversion circuits and a selector, wherein the M half-rate parallel-serial conversion circuits and the selector are correspondingly coupled with the M parallel-serial buffer units, M parallel data signals are respectively connected to input ends of the M half-rate parallel-serial conversion circuits, M primary serial signals are output by output ends of the M half-rate parallel-serial conversion circuits, the primary serial signals are connected to the input end of the selector together, a control end of the selector is connected to the half-rate orthogonal clock signal, and a serialized signal is output by an output end of the selector.

The half rate parallel to serial conversion circuit includes a first conversion circuit, a second conversion circuit, and a conversion selector coupled. The output ends of the first conversion circuit and the second conversion circuit are respectively connected with the input end of the selector, the output end of the first conversion circuit outputs a first conversion signal, the output end of the second conversion circuit outputs a second conversion signal, the input end of the selector is respectively connected with the first conversion signal and the second conversion signal, the control end is connected with the half-rate quadrature clock signal, and the output end outputs the serialized signal; wherein the half-rate quadrature clock signal is at a low level and the serialized signal is the first converted signal; the half-rate quadrature clock signal is at a high level and the serialized signal is the second converted signal.

In one embodiment, the half rate parallel to serial conversion circuit includes (N +1) D flip-flop cells and (N-1) selector cells. Wherein (N-1) selectors and N D flip-flop units are used for realizing a sampling serialization path of N bits of parallel data, and the remaining 1D flip-flop is used for generating a conversion control signal synchronous with a quadrature clock. Wherein the rising edge of the half rate quadrature clock signal DDRCLK _ Q is used for the serial sampling output of the even bits of the parallel data signal and the falling edge of the half rate quadrature clock signal DDRCLK _ Q is used for the serial sampling output of the odd bits of the parallel data signal. For the even-numbered bit-serialized sample output path, when the conversion control signal DIV _ SEL is low, the entire path serves as a shifter circuit, data is sequentially output from left to right, and when the conversion control signal DIV _ SEL is high, even-numbered bits of parallel data are updated into the respective DFFs on the path. Since the period of DIV _ SEL is equal to the period of the parallel data sampling clock signal, it is guaranteed that each bit of information of the parallel data can be updated for output. The ODD bits work as even bits, and the control signal is converted to DIV _ SEL _ ODD. Finally, the outputs of the odd and even paths are combined by a selector controlled by a half-rate quadrature clock signal DDRCLK _ Q to obtain the final serialized output serialized signal SOUT. The serialized signal SOUT is edge-aligned with the half-rate quadrature clock signal DDRCLK _ Q, maintaining only the delay of one selector cell.

The input signal of the half-rate parallel-serial conversion circuit comprises a half-rate control signal DDRCLK _ Q < M-1:0> and a conversion control signal DIV _ SEL < M-1:0> from a clock tree, and also comprises M parallel data signals D0< N-1:0> -DM-1 < N-1:0>, and the signals are converted into serial signals S < M-1:0> after parallel-serial conversion and are respectively output.

Fig. 7 is a schematic diagram of a half-rate parallel-serial conversion module according to an embodiment of the present invention, as shown in fig. 7, in this embodiment, N is an even number, and each of the first conversion circuit and the second conversion circuit includes N/2 conversion D flip-flop units and (N/2-1) conversion selector units. The other (N/2-1) repeated cascade units are composed of a conversion selector and a conversion D trigger except the conversion D trigger connected with the highest odd-numbered bit data and the highest even-numbered bit data.

The input end of the conversion D trigger is connected with D < N-2>, DQ < N-4> … … DQ <0> in sequence, the output signals are Q < N-2> and Q < N-4> … … Q <0> in sequence, the input end of the conversion selector is connected with a bit from a preceding conversion D trigger and a parallel data signal respectively, and the control signal of the conversion selector is DIV _ SEL. When DIV _ SEL is low, the conversion selector respectively outputs sampling output signals Q < N-2>, Q < N-4> … … Q <2> of the front stage D flip-flop, and when DIV _ SEL is high, the conversion selector outputs parallel data signals D < N-4>, D < N-6> … … D <0 >. Similarly, the input end of the conversion D flip-flop is connected with D < N-1>, DQ < N-3> … … DQ <1> in sequence, the output signals are Q < N-1> and Q < N-3> … … Q <1> in sequence, the input end of the conversion selector MUX is respectively connected with one bit from the front stage D flip-flop and the parallel data signal, the control signal of the conversion selector is DIV _ SEL _ ODD, and the signal is a signal of DIV _ SEL synchronized by a half-rate orthogonal clock signal DDRCLK _ Q and is one serial clock period TSCLK later than the DIV _ SEL signal. When DIV _ SEL _ ODD is low, the conversion selector outputs sampling output signals Q < N-1>, Q < N-3> … … Q <3> of the front stage D flip-flops respectively, and when DIV _ SEL _ ODD is high, the conversion selector outputs parallel data signals D < N-3>, D < N-5> … … D <1 >. The final output signal of the first conversion circuit is Q <0>, the final output signal of the second conversion circuit is Q <1>, the two paths of signals of the first conversion circuit and the second conversion circuit are connected to two input ends of a conversion selector of the last stage, the conversion selector selects a control signal to be a half-rate quadrature clock signal DDRCLK _ Q, when the half-rate quadrature clock signal DDRCLK _ Q is low, the signal Q <0> of the first conversion circuit is selected to be output, and when the half-rate quadrature clock signal DDRCLK _ Q is high, the signal Q <1> of the second conversion circuit is selected to be output. The half-rate parallel-serial conversion module adopts a half-rate framework, further reduces the dynamic current consumption and is beneficial to better time sequence alignment of a clock channel and a data channel.

In this embodiment, the sampling clock of the D flip-flop of the first conversion circuit is a half-rate quadrature clock signal DDRCLK _ Q, and the sampling clock of the D flip-flop of the second conversion circuit is an inverted signal of the half-rate quadrature clock signal DDRCLK _ Q. The rising edge of the half-rate quadrature clock signal DDRCLK _ Q is used for the serialized sampling of even bits of the parallel data signal, the falling edge is used for the serialized sampling of odd bits of the parallel data signal, the period of the conversion pulse signal DIV _ SEL is equal to the period of the sampling clock of the parallel data signal, and the serialized signal is aligned with the edge of the half-rate quadrature clock signal.

In another embodiment, N is an odd number, the first conversion circuit includes (N-1)/2D flip-flop cells and ((N-1)/2-1) conversion selector cells, and the second conversion circuit includes (N +1)/2 conversion D flip-flop cells and ((N +1)/2-1) conversion selector cells. Similarly, in the first conversion circuit and the second conversion circuit, the following cascade units are each constituted by one conversion selector plus one conversion D flip-flop, except for the conversion D flip-flop to which the highest odd-numbered bit and the highest even-numbered bit are connected. In the second conversion circuit, from the input end to the output end, the input end of the conversion D trigger is connected with D < N-1>, DQ < N-3> … … DQ <0> in sequence, and the output signals are Q < N-1>, Q < N-3> … … Q <0> in sequence. The control signal of the selector is switched to DIV _ SEL. When DIV _ SEL is low, the selector outputs sampling output signals Q < N-1>, Q < N-3> … … Q <2> of the preceding stage conversion D flip-flop respectively, and when DIV _ SEL is high, the conversion selector outputs parallel data signals D < N-3>, D < N-5> … … D <0 >. In the first conversion circuit, from the input end to the output end, the input end of the conversion D trigger is connected with D < N-2>, DQ < N-4> … … DQ <1> in sequence, and the output signals are Q < N-2>, Q < N-4>, … … Q <1> in sequence. The control signal of the conversion selector is DIV _ SEL _ ODD. When DIV _ SEL _ ODD is low, the conversion selector outputs sampling output signals Q < N-2>, Q < N-4> … … Q <3> of the front stage conversion D flip-flop respectively, and when DIV _ SEL _ ODD is high, the conversion selector outputs parallel data signals D < N-4>, D < N-6> … … D <1 >. The final output signal of the second conversion circuit is Q <0>, the final output signal of the first conversion circuit is Q <1>, the two paths of signals of the first conversion circuit and the second conversion circuit are connected to two input ends of a conversion selector of the last stage, the conversion selector selects a control signal to be a half-rate quadrature clock signal DDRCLK _ Q, when the half-rate quadrature clock signal DDRCLK _ Q is low, the Q <0> output of the second conversion circuit signal is selected, and when the half-rate quadrature clock signal DDRCLK _ Q is high, the signal Q <1> output of the first conversion circuit is selected.

Fig. 8 is a timing chart corresponding to the half-rate parallel-serial conversion module shown in fig. seven, and as shown in fig. 8, the serialization output order of the above embodiment is that data is sequentially output from a low bit, and a high bit is finally output. In some high-speed IO protocols, the requirement that the high-bit bits are output first is not eliminated, and then the connection mode of the input signals D < N-1> to D <0> in the above embodiments may be changed to the corresponding connection of D <0> to D < N-1>, so that the serial output from the high-bit bits may be realized.

In this embodiment, the system supports forward clock transmission, the high-speed multi-channel parallel-to-serial conversion circuit further includes 1 DDR clock generation circuit, the half-rate quadrature sampling clock generation module further outputs a half-rate clock signal, and the clock driving module further includes 1 clock buffer unit to drive the half-rate clock signal, that is, the clock driving module of the present invention includes (M +1) buffer units in total, and the path lengths of the (M +1) buffer units are the same. In this embodiment, the half-rate clock signal is driven by a buffer unit and then output to the DDR clock generation circuit; the DDR interface clock generation circuit comprises a DDR selector, a control end of the DDR selector is connected with the half-rate clock signal, a first input end of the DDR selector is connected with the low level, a second input end of the DDR selector is connected with the high level, and an output end of the DDR selector outputs the DDR clock signal. The DDR clock signal is phase aligned with the half rate clock signal.

Fig. 9 is a schematic diagram of a DDR clock generation circuit according to an embodiment of the present invention, in which the DDR interface clock generation circuit includes a clock selector, a control terminal of the clock selector is connected to DDRCLK _ I, an input terminal of the clock selector is connected to a fixed low level and a fixed high level, respectively, when a half-rate clock signal DDRCLK _ I is at a low level, a clock outputs a low half period, and when the half-rate clock signal DDRCLK _ I is at a high level, the clock outputs a high half period. The output signal SCLK is phase aligned with the half-rate clock signal DDRCLK _ I, maintaining only the delay of one selector cell. The delay is consistent with the data path. The accurate matching on the time sequence is realized, and the more accurate channel alignment standard is achieved.

Based on the high-speed multi-channel parallel-serial conversion circuit, the delay between the generation of the conversion pulse signal, the half-rate clock signal and the half-rate orthogonal clock signal and the rising edge of the parallel clock signal is kept in a plurality of serial clock cycles and is in clock synchronization with the serial clock signal, so that the control of the internal sampling time sequence is realized. Meanwhile, by advancing the balance tree, generating a half-rate quadrature clock and driving the half-rate quadrature clock to each channel, the signal interference problem on the balance tree and the consumption of dynamic current are reduced, and the absolute matching of paths is ensured, so that the circuit can realize higher time sequence performance. In addition, the half-rate parallel-serial conversion module comprises M half-rate parallel-serial conversion circuits and a selector which are correspondingly coupled with the M parallel-serial buffer units, M parallel data signals are respectively connected to the input ends of the M half-rate parallel-serial conversion circuits, M primary serial signals are output by the output ends of the M half-rate parallel-serial conversion circuits and are commonly connected to the input end of the selector, the control end of the selector is connected to the half-rate orthogonal clock signal, a serial signal is output by the output end, and a half-rate framework is realized through the coupled first conversion circuit, the second conversion circuit and the conversion selector, so that the dynamic current consumption is further reduced, the better time sequence alignment of a clock channel and a data channel is facilitated, and the half-rate parallel-serial conversion module has remarkable significance.

The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high speed multi-channel parallel-to-serial conversion circuit, comprising:

the input end of the half-rate orthogonal sampling clock generation module is connected with a system reset signal, a parallel clock signal and a serial clock signal, and the output end of the half-rate orthogonal sampling clock generation module outputs a conversion pulse signal and a half-rate orthogonal clock signal;

the path lengths of the M parallel-serial buffer units are the same;

2. The high-speed multi-channel parallel-to-serial conversion circuit of claim 1, wherein the half-rate quadrature sampling clock generation module further outputs a half-rate clock signal, the clock driving module further comprises 1 clock buffer unit for driving the half-rate clock signal, the half-rate quadrature sampling clock generation module comprises a reset synchronization circuit, a conversion pulse generation circuit and a quadrature clock generation circuit, an input terminal of the reset synchronization circuit is connected to the system reset signal, the parallel clock signal and the serial clock signal, the system reset signal is synchronized by the parallel clock signal and the serial clock signal, respectively, and then outputs a synchronization reset signal, the synchronization reset signal is output to a reset terminal of the conversion pulse generation circuit and a reset terminal of the quadrature clock generation circuit through an output terminal of the reset synchronization circuit, the serial clock signal is input into the conversion pulse generating circuit and the orthogonal clock generating circuit, the synchronous reset signal outputs a conversion pulse signal after the conversion pulse generating circuit is subjected to N frequency division and is synchronous with the serial clock signal, the synchronous reset signal outputs a half-rate clock signal after the orthogonal clock generating circuit is subjected to frequency division twice and is synchronous with the serial clock signal, the half-rate clock signal outputs a half-rate orthogonal clock signal after being synchronous with the serial clock signal, and the phase of the half-rate orthogonal clock signal is later than that of the half-rate clock signal by 90 degrees.

3. The high-speed multi-channel parallel-to-serial conversion circuit of claim 2, wherein the reset synchronization circuit includes a first reset D flip-flop and a second reset D flip-flop coupled; the data end of the first reset D trigger is connected with the system reset signal, the clock end of the first reset D trigger is connected with the parallel clock signal, the output end of the first reset D trigger outputs a primary synchronous signal to the data end of the second reset D trigger, the clock end of the second reset D trigger is connected with the serial clock signal, and the primary synchronous signal is synchronized by the serial clock signal and then outputs the synchronous reset signal.

4. The high-speed multi-channel parallel-to-serial conversion circuit of claim 2, wherein the conversion pulse generation circuit includes a first frequency divider, a first synchronous D flip-flop, a second synchronous D flip-flop, a third synchronous D flip-flop, and an and gate; the clock ends of the first frequency divider, the first synchronous D trigger and the third synchronous D trigger are connected with the serial clock signal together, the reset zero clearing ends of the first synchronous D trigger, the second synchronous D trigger and the third synchronous D trigger are connected with the primary synchronous signal, the reset end of the first frequency divider is connected with the synchronous reset signal, the output end of the first frequency divider outputs a frequency division signal to the data input end of the first synchronous D trigger, the output end of the first synchronous D trigger outputs a primary synchronous signal to the data input end of the second synchronous D trigger and the first input end of the AND gate, the output end of the second synchronous D trigger outputs a secondary synchronous signal to the second input end of the AND gate, and the output end of the AND gate outputs a conversion signal to the data input end of the third synchronous D trigger, and the output end of the third synchronous D trigger outputs the conversion pulse signal.

5. A high speed multi-channel parallel to serial conversion circuit as recited in claim 4 wherein said secondary synchronization signal is an inverted signal that lags said primary synchronization signal by one serial clock cycle.

6. A high speed multi-channel parallel-to-serial conversion circuit as recited in claim 2 wherein said quadrature clock generation circuit includes a second frequency divider, a first quadrature D flip-flop and a second quadrature D flip-flop; the clock ends of the second frequency divider, the first orthogonal D trigger and the second orthogonal D trigger are jointly connected with the serial clock signal, the reset zero clearing ends of the first orthogonal D trigger and the second orthogonal D trigger are connected with the primary synchronous signal, the reset end of the second frequency divider is connected with the synchronous reset signal, the output end of the second frequency divider outputs a frequency-divided signal to the data input end of the first orthogonal D trigger, the output end of the first orthogonal D trigger outputs the half-rate clock signal to the data input end of the second orthogonal D trigger, and the output end of the second orthogonal D trigger outputs the half-rate orthogonal clock signal.

7. The high-speed multi-channel parallel-to-serial conversion circuit of claim 2, further comprising a DDR clock generation circuit to which the half-rate clock signal is driven to be output through the buffer unit.

8. The high speed multi-channel parallel to serial conversion circuit of claim 7, wherein the DDR interface clock generation circuit includes a DDR selector having a control terminal coupled to the half rate clock signal, a first input terminal coupled to the low level, a second input terminal coupled to the high level, and an output terminal outputting a DDR clock signal, the DDR clock signal being phase aligned with the half rate clock signal.

9. The high-speed multi-channel parallel-to-serial conversion circuit of claim 1, wherein the structure of the buffer unit includes an inverter structure or a CML structure.

10. The high-speed multi-channel parallel-to-serial conversion circuit of claim 1, wherein the half-rate parallel-to-serial conversion circuit comprises a first conversion circuit, a second conversion circuit and a conversion selector coupled together, wherein output terminals of the first conversion circuit and the second conversion circuit are respectively connected to an input terminal of the selector, an output terminal of the first conversion circuit outputs a first conversion signal, an output terminal of the second conversion circuit outputs a second conversion signal, input terminals of the selector are respectively connected to the first conversion signal and the second conversion signal, a control terminal is connected to the half-rate quadrature clock signal, and an output terminal outputs the serialized signal; wherein the half-rate quadrature clock signal is at a low level and the serialized signal is the first converted signal; the half-rate quadrature clock signal is at a high level and the serialized signal is the second converted signal.