CN112306924A

CN112306924A - Data interaction method, device and system and readable storage medium

Info

Publication number: CN112306924A
Application number: CN202011352561.XA
Authority: CN
Inventors: 王贤坤; 周玉龙; 邹晓峰; 张贞雷; 于锦辉
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2021-02-02

Abstract

The invention discloses a data interaction method, a device, a system and a readable storage medium, wherein the method comprises the following steps: receiving target data sent by a processor according to an AXI protocol; wherein, the processor is connected with the AXI bus; and storing the target data into the storage device according to the storage read-write protocol so that the external device can read the target data from the storage device according to the storage read-write protocol. The method saves the link of conversion between a high-speed bus and a low-speed bus, can convert the AXI bus into an interface similar to a storage device, realizes clock frequency conversion and data interaction between a processor and an external device through the storage device, can keep high-speed transmission of data, can save the AXI bus time, and releases the performance of the AXI bus.

Description

Data interaction method, device and system and readable storage medium

Technical Field

The present invention relates to the field of data transmission technologies, and in particular, to a data interaction method, apparatus, system, and readable storage medium.

Background

Processors often require the mounting of peripherals to meet certain specific computing or functional requirements. In general, a processor mounts an external device on an AHB bus or an APB bus at a low speed through an AXI bus at a high speed. That is, by converting the high speed bus to a low speed bus, the processor may adapt to a low speed peripheral device.

However, in the architecture of the processor-high speed bus-low speed bus-external device, due to the existence of a processing link of high speed, low speed, and low speed, the data interaction rate between the processor and the external device is slow, and the data reading rates of different external devices are different, and the switching requirements for high speed, low speed and data interaction are also inconsistent. Thus, data transitions and relatively complex control logic involving multiple clock domains may be less flexible and convenient to apply.

In summary, how to effectively simplify the data interaction between the processor and the external device is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a data interaction method, a device, a system and a readable storage medium, which directly store data transmitted by a high-speed bus into a storage device and automatically read by an external device, saves conversion processing between the high-speed bus and a low-speed bus, is easy to realize and is convenient and flexible to configure.

In order to solve the technical problems, the invention provides the following technical scheme:

a data interaction method, comprising:

receiving target data sent by a processor according to an AXI protocol; wherein the processor is connected with an AXI bus;

and storing the target data into a storage device according to a storage read-write protocol, so that an external device can read the target data from the storage device according to the storage read-write protocol.

Preferably, the storing the target data into the storage device according to a storage read-write protocol includes:

transmitting the target data to a storage controller according to the storage read-write protocol; the storage controller is connected with a plurality of alternative storage devices, and each alternative storage device is respectively connected with one external device;

and determining a storage device corresponding to the external device from the plurality of candidate storage devices by using the storage controller, and storing the target data into the storage device.

if the storage equipment is an RAM, storing the target data into the RAM according to an RAM read-write protocol;

and if the storage equipment is an FIFO memory, storing the target data into the FIFO memory according to an FIFO read-write protocol.

Preferably, the storing the target data into the RAM according to a RAM read-write protocol includes:

and storing the target data into the RAM with a dual port according to the RAM read-write protocol.

Preferably, before the receiving the target data sent by the processor according to the AXI protocol, the method further includes:

monitoring signals generated by the processor and the external device;

and if the processor generates a VLAID signal and the external equipment generates a READY signal corresponding to the VLAID signal, executing the step of receiving the target data sent by the processor according to the AXI protocol.

A data interaction device, comprising:

the data receiving module is used for receiving the target data sent by the processor according to the AXI protocol; wherein the processor is connected with an AXI bus;

and the data unloading module is used for storing the target data into the storage equipment according to a storage read-write protocol so that the external equipment can read the target data from the storage equipment according to the storage read-write protocol.

A data interaction system, comprising:

the device comprises a processor, an external device, an AXI bus, a storage device and an AXI interface register;

wherein the AXI bus is connected with the processor and the AXI interface translator; the AXI interface register is connected with the storage device, and the external device is connected with the storage device;

the AXI interface register is used for receiving target data sent by the processor according to an AXI protocol; storing the target data into the storage device according to a storage read-write protocol;

and the external equipment is used for reading the target data from the storage equipment according to the storage read-write protocol.

Preferably, the number of the AXI interface registers is the same as the number of the memory devices and is greater than 1, and each of the AXI interface registers fixedly uses one segment of a bus address space of the AXI bus.

Preferably, between the AXI interface register and the storage device, a storage controller is further included;

the memory controller is connected to at least 2 of the memory devices for multiplexing a segment of a bus address space of the AXI bus.

A readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the above-mentioned data interaction method.

By applying the method provided by the embodiment of the invention, the target data sent by the processor is received according to the AXI protocol; wherein, the processor is connected with the AXI bus; and storing the target data into the storage device according to the storage read-write protocol so that the external device can read the target data from the storage device according to the storage read-write protocol.

In the method, the data transmission processing between the processor and the AXI bus keeps high-speed transmission, and the link of converting the high-speed bus into the low-speed bus is directly replaced by the link of storing the data transmitted by the AXI bus into the storage device, so that the data interaction between the processor and the storage device is finished in a mode that the external device reads from the storage device by self. That is to say, in the method, the conversion link between the high-speed bus and the low-speed bus is omitted, the AXI bus can be converted into a similar storage device interface, the clock frequency conversion between the processor and the external device is realized through the storage device, the data interaction is realized, the high-speed transmission of the data can be maintained, the AXI bus time can be saved, and the AXI bus performance is released.

Accordingly, embodiments of the present invention further provide a data interaction device, a system and a readable storage medium corresponding to the data interaction method, which have the above technical effects and are not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present invention or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flowchart illustrating an implementation of a data interaction method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a data interaction device according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a data interaction system according to an embodiment of the present invention;

FIG. 4 is a detailed diagram of a data interaction system according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an AXI write RAM data flow according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating an AXI RAM data reading process according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart of a data interaction method according to an embodiment of the present invention, where the method may be applied to an AXI interface dump, where the AXI interface dump refers to a method capable of dumping data transmitted on an AXI bus into a storage device. The method comprises the following steps:

since the AXI bus is a VALID/READY based handshake mechanism data transfer protocol, the transfer source generates a vladd signal to indicate when data or control information is VALID. And the destination source generates a READY signal to indicate that it is READY to accept data or control information. Transmission occurs when both VALID and READY signals are high. Therefore, before the steps in fig. 1 are executed, that is, before the step S101 is executed to receive the target data sent by the processor according to the AXI protocol, it is further determined that the processor and the external device have completed handshaking. Specifically, signals generated by a processor and external equipment are monitored; and if the processor generates a VLAID signal and the external equipment generates a READY signal corresponding to the VLAID signal, receiving the target data sent by the processor according to the AXI protocol.

S101, receiving target data sent by a processor according to an AXI protocol.

Wherein the processor is connected with the AXI bus.

The AXI protocol includes 5 independent transmission channels: the AXI protocol uses a transaction ID tags to process multi-address and out-of-order transmission, supports unaligned data transmission and burst transmission, and meets the requirements of ultra-high performance and complex system on chip (SoC) design.

The processor may be any processor capable of supporting AXI bus data transfers. For example, the processor may be embodied as a BOOM processor based on RISC-V instruction set, which is a superscalar out-of-order execution processor capable of flexibly modifying codes for testing based on a prototype verification system of FPGA. The FPGA has the programmable characteristic, is flexible and stable, has high speed and high efficiency, can supplement the ASIC and can also be used as a verification platform of the ASIC.

RISC-V instruction set, namely a brand new instruction established on the basis of the continuous development and maturity of the instruction set, the structure is clear and simple, the modular design can be matched at will according to the needs, the flexibility and convenience are realized, the transportability is strong, a complete tool chain is provided, and the BSD protocol has openness.

In this embodiment, the processor still adopts the transmission protocol corresponding to the AXI bus to perform data interaction to the outside.

The AXI interface register can obtain target data transmitted by a processor transmitted on an AXI bus through an AXI bus transmission protocol. For a specific implementation process of how to obtain target data transmitted on the AXI bus according to the AXI bus transmission protocol, reference may be made to the AXI bus transmission protocol and related applications, which are not described in detail herein.

S102, storing the target data into the storage device according to the storage read-write protocol, so that the external device can read the target data from the storage device according to the storage read-write protocol.

After the target data is obtained, the target data can be stored in the storage device according to a storage read-write protocol. That is, at this time, the high-speed data on the AXI bus is completely transferred to the storage device, and the external device can directly read the target data from the storage device according to the storage read-write protocol. That is, by transferring the data to the storage device, the conversion step of directly converting the high-speed bus and the low-speed bus can be omitted.

In the embodiment of the present invention, the storage device may be any storage device that can be read and written by an external device.

In one embodiment of the present invention, in order to enable efficient data transfer between the processor and the external device, the memory device may preferably employ a RAM or a FIFO memory with higher access efficiency. Correspondingly, step S102 stores the target data into the storage device according to the storage read-write protocol, including:

case 1: and if the storage equipment is the RAM, storing the target data into the RAM according to a RAM read-write protocol. Among them, RAM (Random Access Memory), also known as a Memory bank. When the memory bank works, information can be written (stored) or read (taken out) from any one appointed address at any time.

Preferably, considering that the read and write operations of the single-port RAM cannot be performed simultaneously, in practical applications, the RAM may be a RAM with dual ports, that is, the RAM stores the target data into the RAM according to a RAM read and write protocol, and the method includes: and storing the target data into the RAM with the dual ports according to a RAM read-write protocol. The RAM with the dual port can be a pseudo dual port or a real dual port.

The pseudo-Dual Port RAM (Simple Dual-Port RAM) comprises a group of data lines, two groups of address lines and two clocks; the two output ports share one output port; so one port is read only and the other port is write only, but the clocks for writing and reading may be different and the bit width ratio may be other than 1: 1. I.e., allowing simultaneous reading of B while writing a, and the rates may be different.

A True Dual-Port RAM (True Dual-Port RAM) having two sets of address lines and two sets of data lines, two clocks as inputs; the output has two separate data lines. Therefore, the two ports of the dual-port RAM are respectively provided with a read-write port, so that reading and writing can be carried out without interference, and mutual interference is avoided.

Case 2: and if the storage equipment is an FIFO memory, storing the target data into the FIFO memory according to an FIFO read-write protocol. The FIFO (First Input First Output queue) is a traditional sequential execution method, and the second instruction is executed after the First instruction is completed and retired.

The FIFO memory comprises 2 ports, one port being read only and the other port being write only. The FIFO memory is divided into a write-only area and a read-only area. The read operation and the write operation can be performed asynchronously, and the data written on the write area is read from the area of the read end in the order of writing (first-in first-out), similar to a buffer that absorbs the speed difference between the write end and the read end.

In an embodiment of the present invention, in order to improve the utilization efficiency of the AXI bus, the bus address of the AXI bus may be multiplexed. Specifically, step S102 stores the target data in the storage device according to the storage read-write protocol, which includes:

step one, transmitting target data to a storage controller according to a storage read-write protocol; the storage controller is connected with a plurality of alternative storage devices, and each alternative storage device is respectively connected with one external device;

and step two, determining a storage device corresponding to the external device from the plurality of candidate storage devices by using the storage controller, and storing the target data into the storage device.

For convenience of description, the above two steps will be described in combination.

A storage controller can be provided, and the storage controller is connected with a plurality of alternative storage devices, and each alternative storage device is correspondingly connected with an external device.

Therefore, based on the storage controller, when data interactive transmission is required, the storage device corresponding to the external device can be determined from the multiple candidate storage devices. Specifically, the corresponding storage device may be determined according to the specific address configuration information. The target data is then stored in the memory device, thereby implementing multiplexing of the same address segment of the AXI bus.

In particular, in the above, only the data transmission from the processor to the external device and the transmission process are described, and in practical applications, the data transmission from the external device to the processor and the transmission process are also referred to.

For convenience of understanding, different read-write processes for the RAM in data transmission processes of different trends are described below one by one.

Referring to fig. 5 and fig. 6, fig. 5 is a schematic diagram illustrating an AXI write RAM data flow in an embodiment of the present invention, and fig. 6 is a schematic diagram illustrating an AXI read RAM data flow in an embodiment of the present invention.

Specifically, an AXI bus burst read-write mode may be employed. And setting the size of a corresponding RAM according to the size of a cache space required by the peripheral for receiving and transmitting data. The data interaction between the processor and the peripheral equipment can adopt an interrupt mode or a timing read-write mode according to the characteristics of the peripheral equipment.

In the process of writing RAM by AXI, firstly, the AXI slave equipment writes address channel signal processing and data channel signal processing, and then the AXI performs write address response, write address cache processing, AXI write data cache processing and AXI write data response, so as to realize the processing of writing RAM address and data and writing response channel signal.

In the process of reading RAM by AXI, firstly, AXI slave equipment reads address channel signal processing and data channel signal processing, and then AXI carries out read address response, read address cache processing and AXI read data cache processing, so that RAM address and data reading and AXI read data response are realized.

That is to say, the data interaction method is a specific implementation of converting an AXI bus interface into an RAM interface, can support various modes and channel characteristics of the AXI bus, can adapt to the bit width of the bus, has small delay and high efficiency, can be packaged into an IP and has flexible and convenient multiplexing; based on interface conversion, a double-port RAM can be preferably adopted to realize the conversion of a bus clock and an external clock, so that the complex logic of clock conversion is reduced, and the error probability is reduced. Meanwhile, when a peripheral data read-write mode of multiplexing a bus address space is adopted, the data transmission efficiency can be improved.

Corresponding to the above method embodiment, the embodiment of the present invention further provides a data interaction device, and the data interaction device described below and the data interaction method described above may be referred to correspondingly.

Referring to fig. 2, the apparatus includes the following modules:

a data receiving module 101, configured to receive target data sent by a processor according to an AXI protocol; wherein, the processor is connected with the AXI bus;

the data unloading module 102 is configured to store the target data into the storage device according to the storage read-write protocol, so that the external device reads the target data from the storage device according to the storage read-write protocol.

The device provided by the embodiment of the invention is applied to receive the target data sent by the processor according to the AXI protocol; wherein, the processor is connected with the AXI bus; and storing the target data into the storage device according to the storage read-write protocol so that the external device can read the target data from the storage device according to the storage read-write protocol.

In a specific embodiment of the present invention, the data unloading module 102 is specifically configured to transmit the target data to the storage controller according to a storage read-write protocol; the storage controller is connected with a plurality of alternative storage devices, and each alternative storage device is respectively connected with one external device; and determining a storage device corresponding to the external device from the plurality of candidate storage devices by using the storage controller, and storing the target data into the storage device.

In a specific embodiment of the present invention, the data unloading module 102 is specifically configured to, if the storage device is a RAM, store the target data into the RAM according to a RAM read-write protocol; and if the storage equipment is an FIFO memory, storing the target data into the FIFO memory according to an FIFO read-write protocol.

In an embodiment of the present invention, the data unloading module 102 is specifically configured to store the target data into the RAM with the dual port according to a RAM read-write protocol.

In one embodiment of the present invention, the method further comprises:

the handshake determining module is used for monitoring signals generated by the processor and the external equipment before receiving the target data sent by the processor according to the AXI protocol; if the processor generates a VLAID signal and the external device generates a READY signal corresponding to the VLAID signal, the data receiving module 101 is triggered to execute a step of receiving the target data sent by the processor according to the AXI protocol.

Corresponding to the above method embodiment, the embodiment of the present invention further provides a data interaction system, and the data interaction system described below and the data interaction method described above may be referred to correspondingly.

Referring to fig. 3, the system includes the following modules:

the AXI bus is connected with the processor and is connected with the AXI interface register; the AXI interface register is connected with the storage equipment, and the external equipment is connected with the storage equipment;

In one embodiment of the present invention, the number of the AXI interface registers and the number of the memory devices are equal to or greater than 1, and each AXI interface register fixedly uses a segment of bus address space of an AXI bus.

In a specific embodiment of the present invention, between the AXI interface register and the storage device, a storage controller is further included;

the memory controller is connected to at least 2 memory devices for multiplexing a segment of a bus address space of an AXI bus.

Specifically, for convenience of description, the data interaction system will be described in detail below by taking a storage device, specifically a RAM, as an example.

Referring to fig. 4, fig. 4 is a specific schematic diagram of a data interaction system according to an embodiment of the present invention.

Among them, RISC-V Core, a BOOM processor based on RISC-V instruction set. Peripheral data can be acquired according to bus address division, timing or interrupt modes.

The AXI bus, i.e. the on-chip bus interconnection module with high performance, high bandwidth and low delay, uses the processor end as a master device and uses the peripheral (i.e. external device) end as a slave device, thereby realizing the data interaction between the processor and the peripheral data.

The system comprises an AXI2RAM (corresponding to an AXI interface register), namely a conversion module from an AXI bus interface to a RAM read-write interface, supports the channel characteristics and various read-write modes of an AXI bus, and supports configurable bus bit width.

The RAM can be a dual-port RAM, a simple dual-port (pseudo dual-port) or a true dual-port RAM can be set according to application and used as peripheral data cache to realize conversion between a peripheral clock domain and a processor bus clock domain.

RAM _ CTRL: and the control module is used for jointly processing the storage data of the multiple peripherals. According to configuration, bus address space can be multiplexed, peripheral data can be uniformly read and written according to a specific sequence, or peripheral data can be circularly processed, so that the data interaction efficiency is improved.

For the bus address allocation of the peripheral equipment, two modes can be adopted: firstly, an independent appropriate bus address space is set for the peripheral equipment, and a fixed or value-added burst read-write mode (such as peripheral equipment 3 in fig. 4) is adopted, wherein the mode is suitable for peripheral equipment with moderate data volume and frequent data interaction; secondly, a section of bus address space is allocated, data read and write (such as the peripheral 1 and the peripheral 2 in fig. 4) of a plurality of peripherals are multiplexed, all the peripheral data are uniformly read according to a specific sequence under the control of the RAM _ CTLR module, or the data of one or more peripherals are read and written according to interruption or polling.

Therefore, in the data interaction system, according to the characteristics of the AXI bus, the conversion from AXI to RAM is realized, various read-write modes and channel characteristics of the AXI bus are supported, the bus bit width can be adapted, a relatively complex AXI bus interface is converted into a common storage RAM read-write interface, the frequency conversion of a bus clock and a peripheral clock is realized by using a double-port RAM, the time delay is small, and the efficiency is high.

Corresponding to the above method embodiment, the embodiment of the present invention further provides a readable storage medium, and a readable storage medium described below and a data interaction method described above may be referred to correspondingly.

A readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the data interaction method of the above-mentioned method embodiments.

The readable storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and various other readable storage media capable of storing program codes.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

Claims

1. A method for data interaction, comprising:

2. The data interaction method of claim 1, wherein the storing the target data into a storage device according to a storage read-write protocol comprises:

3. The data interaction method of claim 1, wherein the storing the target data into a storage device according to a storage read-write protocol comprises:

4. The data interaction method of claim 3, wherein the storing the target data into the RAM according to a RAM read-write protocol comprises:

5. The data interaction method of claim 1, wherein before the receiving the target data sent by the processor according to the AXI protocol, the method further comprises:

monitoring signals generated by the processor and the external device;

6. A data interaction device, comprising:

7. A data interaction system, comprising:

8. The data interaction system as recited in claim 7, wherein the number of the AXI interface registers is the same as the number of the memory devices and is greater than 1, each of the AXI interface registers fixedly using a segment of a bus address space of the AXI bus.

9. The data interaction system of claim 7, further comprising a memory controller between the AXI interface translator and the memory device;

10. A readable storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps of the data interaction method according to any one of claims 1 to 5.