CN112003800A

CN112003800A - Method and device for exchanging and transmitting messages of ports with different bandwidths

Info

Publication number: CN112003800A
Application number: CN202010796383.3A
Authority: CN
Inventors: 赵姣; 张建波; 杨珂; 崔飞飞
Original assignee: Niuxin Semiconductor Shenzhen Co ltd
Current assignee: Niuxin Semiconductor Shenzhen Co ltd
Priority date: 2020-08-10
Filing date: 2020-08-10
Publication date: 2020-11-27
Anticipated expiration: 2040-08-10
Also published as: CN112003800B

Abstract

The embodiment of the application provides a method and a device for message exchange transmission of ports with different bandwidths. The method for exchanging and transmitting the messages of the ports with different bandwidths comprises the following steps: receiving a plurality of messages input by an input port, wherein the messages comprise message data, and caching the plurality of messages; acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message in a plurality of messages; if the bit width of the output port is smaller than the bit width of the input port, reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address; if the bit width of the output port is larger than the bit width of the input port, acquiring the storage addresses of the messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage addresses of the messages; and sending the message data with the bit width same as that of the output port to the output port so that the output port can smoothly output the message data.

Description

Method and device for exchanging and transmitting messages of ports with different bandwidths

Technical Field

The present application relates to the field of computer and communication technologies, and in particular, to a method and an apparatus for exchanging and transmitting messages at ports with different bandwidths.

Background

PCIE (peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard, and is widely used for communication between PCIE devices.

The PCIE switch chip may implement communication between PCIE devices by transmitting a message, and when the PCIE switch chip transmits a message, it is required that a bit width of an input port that receives the message is the same as a bit width of an output port that outputs the message, and if the bit width of the input port is different from the bit width of the output port, the PCIE switch chip cannot output the message, which causes message blocking, and communication between the PCIE devices fails.

Disclosure of Invention

Embodiments of the present application provide a method and an apparatus for exchanging and transmitting messages at ports with different bandwidths, which can reduce the risk of message blocking at least to a certain extent.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.

According to an aspect of the embodiments of the present application, a method for packet switching transmission of ports with different bandwidths is provided, including: receiving a plurality of messages input by an input port, wherein the messages comprise message data, and caching the messages; acquiring a storage address corresponding to each message in the plurality of messages, a bit width of an output port and a bit width of an input port; if the bit width of the output port is smaller than the bit width of the input port, reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address; if the bit width of the output port is greater than the bit width of the input port, acquiring storage addresses of a plurality of messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses of the plurality of messages; and sending the message data with the bit width same as that of the output port to the output port.

According to an aspect of the embodiments of the present application, there is provided a packet switching transmission apparatus for ports with different bandwidths, including: the receiving unit is configured to receive a plurality of messages input by the input port, wherein the messages comprise message data, and the plurality of messages are cached; the acquiring unit is configured to acquire a storage address corresponding to each message in the plurality of messages, a bit width of an output port and a bit width of an input port; a reading unit configured to read, if the bit width of the output port is smaller than the bit width of the input port, message data having the same bit width as the bit width of the output port from a storage space corresponding to the storage address; if the bit width of the output port is greater than the bit width of the input port, acquiring storage addresses of a plurality of messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses of the plurality of messages; and the sending unit is configured to send the message data with the bit width same as that of the output port to the output port.

In some embodiments of the present application, based on the foregoing scheme, the obtaining unit is configured to: before acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message in the plurality of messages, recording the storage address, the bit width of the output port and the bit width of the input port corresponding to each message in a message descriptor corresponding to the message; and acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message from the message descriptor of each message.

In some embodiments of the present application, based on the foregoing scheme, the packet includes a plurality of packet fragments, and the obtaining unit is configured to: and recording the storage address corresponding to each message segment, the bit width of the output port and the bit width of the input port in the message descriptor corresponding to the message segment.

In some embodiments of the present application, based on the foregoing scheme, the reading unit is configured to: modifying the bit width of the input port recorded in the message descriptor, wherein the modified bit width of the input port is the same as the bit width of the output port; and reading the message data with the same bit width as the modified bit width of the input port from the storage space corresponding to the storage address recorded in the message descriptor according to the modified bit width of the input port.

In some embodiments of the present application, based on the foregoing scheme, the reading unit is configured to: if the bit width of the output port is smaller than the bit width of the input port, determining the times of reading the message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage address according to the bit width of the output port and the bit width of the input port; copying the message descriptors, wherein the number of the copied message descriptors is the same as the number of times of reading the message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage address, and one message descriptor is used for reading the message data at one time; modifying the bit width of the input port recorded in each message descriptor in the copied message descriptors.

In some embodiments of the present application, based on the foregoing scheme, the reading unit is configured to: acquiring a sending sequence of a plurality of messages corresponding to the output port; and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses recorded by the message descriptors of the messages adjacent to the transmission sequence.

In some embodiments of the present application, based on the foregoing scheme, the reading unit is configured to: acquiring message characteristics of a plurality of messages corresponding to the output port, the congestion condition of the output port and a PCIE sequencing rule; and determining the sending sequence of the plurality of messages corresponding to the output port based on the message characteristics of the plurality of messages corresponding to the output port, the congestion condition of the output port and the PCIE sequencing rule.

In some embodiments of the present application, based on the foregoing scheme, the reading unit is configured to: and combining a plurality of message descriptors corresponding to a plurality of messages adjacent to the sending sequence, and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address recorded by the combined plurality of message descriptors.

In some embodiments of the present application, based on the foregoing scheme, the obtaining unit is configured to: acquiring the attribute of the message, if the message is determined to be a multicast message according to the attribute of the message, acquiring the number of output ports corresponding to the multicast message, and copying the message descriptors to obtain the message descriptors with the same number as the output ports, wherein each message descriptor corresponds to one output port; and acquiring a storage address corresponding to the message, a bit width of an output port corresponding to the message descriptor and a bit width of the input port from each message descriptor.

In the technical solutions provided in some embodiments of the present application, a plurality of messages input by an input port are received, where the messages include message data, and the plurality of messages are cached; acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message in a plurality of messages; if the bit width of the output port is smaller than the bit width of the input port, reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address; if the bit width of the output port is larger than the bit width of the input port, acquiring the storage addresses of the messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage addresses of the messages; the message data with the bit width same as that of the output port is sent to the output port, and the output port can smoothly output the message data with the bit width same as that of the output port, so that the message input by the input port can be smoothly transmitted by the output port under the condition that the bit width of the input port is different from that of the output port, and the risk of message blocking is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

FIG. 1 shows a schematic diagram of an exemplary system architecture to which aspects of embodiments of the present application may be applied;

fig. 2 schematically illustrates a flow chart of a method for different bandwidth port packet switch transmission according to an embodiment of the present application;

fig. 3 schematically shows a message transmission process according to an embodiment of the present application;

FIG. 4 is a diagram that schematically illustrates the structure of a buffer for message descriptors, in accordance with an embodiment of the present application;

fig. 5 schematically illustrates a flow chart of a scheduling method of multicast message descriptors according to an embodiment of the present application;

fig. 6 schematically illustrates a flow chart of a scheduling method of multicast message descriptors according to an embodiment of the present application;

FIG. 7 schematically illustrates a block diagram of a different bandwidth port message switching transmission device according to one embodiment of the present application;

FIG. 8 illustrates a schematic structural diagram of a computer system suitable for use in implementing the electronic device of an embodiment of the present application.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

Fig. 1 shows a schematic diagram of an exemplary system architecture to which the technical solution of the embodiments of the present application can be applied.

As shown in fig. 1, the system architecture may include a PCIE Switch chip (PCIE Switch)101, a PCIE protocol 102, and a PCIE device 103 (which may be a smart phone, a tablet, a portable computer, a desktop computer, a development device with a PCIE interface, etc.). The PCIE protocol 102 is used to provide a medium for a communication link between the PCIE Switch101 and the PCIE device 103.

It should be understood that the number of PCIE Switch101, PCIE protocol 102, PCIE devices 103 in fig. 1 is merely illustrative. There may be any number of PCIE Switch101, PCIE protocols 102, and PCIE devices 103, as desired for an implementation.

In an embodiment of the present application, the PCIE Switch101 may establish a communication connection between the PCIE devices 103, where the input port and the output port may be an input port and an output port of the PCIE Switch101, and the PCIE Switch101 may receive a plurality of messages input by the input port, where the messages include message data, and buffer the plurality of messages; acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message in a plurality of messages; if the bit width of the output port is smaller than the bit width of the input port, reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address; if the bit width of the output port is larger than the bit width of the input port, acquiring the storage addresses of the messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage addresses of the messages; the message data with the bit width same as that of the output port is sent to the output port, and the output port can smoothly output the message data with the bit width same as that of the output port, so that the message input by the input port can be smoothly transmitted by the output port under the condition that the bit width of the input port is different from that of the output port, the risk of message blocking is reduced, the utilization rate of the output port and the message data is improved, the transmission efficiency of the message is improved, bit width read-write conflict in the message transmission process is avoided, and the risk of blank transmission and loss of the message data is reduced.

It should be noted that the method for switching and transmitting packets at different bandwidth ports provided in the embodiment of the present application is generally executed by the PCIE Switch101, and accordingly, the apparatus for switching and transmitting packets at different bandwidth ports is generally disposed in the PCIE Switch 101. However, in other embodiments of the present application, the PCIE device 103 may also have a function similar to that of the PCIE Switch101, so as to execute the packet switching transmission method for ports with different bandwidths provided in the embodiments of the present application.

In an embodiment of the present application, the PCIE Switch101 can implement high-speed, real-time, and high-bandwidth communication between the PCIE devices 103, the PCIE Switch101 generally has more than 3 ports, data bit width, clock frequency, and supported protocols of the ports may be different, and the PCIE Switch101 executing the different bandwidth port packet switching transmission method of the present application may not need to consider adaptation between the input port and the output port while performing packet transmission, so that a packet can be transmitted between the input port and the output port with different bit widths.

The implementation details of the technical solution of the embodiment of the present application are set forth in detail below:

referring to fig. 2, the method for packet switching transmission on ports with different bandwidths at least includes steps S210 to S250, which are described in detail as follows:

in step S210, a plurality of messages input by the input port are received, where the messages include message data, and the plurality of messages are cached.

In an embodiment of the present application, a packet is a data unit exchanged and transmitted in a network, the packet may be a TLP (Transaction Layer Protocol), an HTTP (HyperText Transfer Protocol), or an ethernet packet, and the packet may also be other types of packets, which is not limited herein.

In an embodiment of the present application, the PCIE Switch may set a global shared storage unit for a packet, where the packet is stored in the global shared storage unit after being input by a source port, the packet is read from the global shared storage unit after the switching operation is completed, and the packet in the global shared storage unit may be deleted after the packet is read.

In an embodiment of the present application, the global shared storage unit may include a plurality of storage spaces, where storage addresses of the storage spaces are different, and each packet may be stored in one storage space, so as to implement mutual independence of the packets.

In an embodiment of the present application, the message may be from a message device, or may be from an upstream PCIE chip controller or a downstream PCIE chip controller.

In step S220, a memory address, a bit width of the output port, and a bit width of the input port corresponding to each of the plurality of messages are obtained.

In one embodiment of the present application, the bit width of the input port may be the number of data bits that can be input at one time by the input port, and the bit width of the output port may be the number of data bits that can be output at one time by the output port.

In an embodiment of the present application, a packet header of a packet may include an input port identifier of the packet and an output port identifier of the packet, the input port identifier of the packet may be obtained from the packet header, and a bit width of an input port is obtained according to the input port identifier; the output port identifier of the message can be obtained from the message header, and the bit width of the output port can be obtained according to the output port identifier.

In an embodiment of the present application, the output rate of the output port may be obtained, and the bit width of the output port is calculated according to the output rate of the output port; the input rate of the input port can be obtained, and the bit width of the input port is calculated according to the input rate of the input port.

In one embodiment of the present application, the output rate of the output port refers to the number of data bits that can be output by the output port in one clock cycle, and the input rate of the input port refers to the number of data bits that can be input by the input port in one clock cycle.

In an embodiment of the present application, the number of bits of a data pattern of the PCIE Switch, the number of data lanes of the input port, and the number of data lanes of the output port may be obtained, the bit width of the input port is calculated according to the number of bits of the data pattern and the number of data lanes of the input port, and the bit width of the output port is calculated according to the number of bits of the data pattern and the number of data lanes of the output port. If the PCIE Switch is in the 32-bit data mode, the number of data lanes of the input port is 4 data lanes (4-lane), and the bit width of the input port is 32 × 4 — 128 bits; if the PCIE Switch is in the 32-bit data mode, the number of data lanes of the output port is 16 data lanes (16-lane), and the bit width of the output port is 32 × 16 — 512 bits.

With reference to fig. 2, in step S230, if the bit width of the output port is smaller than the bit width of the input port, the message data having the same bit width as the bit width of the output port is read from the memory space corresponding to the memory address.

In an embodiment of the present application, if the bit width of the output port is smaller than the bit width of the input port, the number of times of reading the message data may be obtained according to the bit width of the output port and the bit width of the input port, and when reading data each time, the message data having the same bit width as the bit width of the output port is sequentially read from the storage space corresponding to the storage address according to the arrangement sequence of the message data in the message.

In an embodiment of the present application, a quotient obtained by dividing the bit width of the input port by the bit width of the output port may be used as the number of times of reading the message data. For example, if the bit width of the input port is 512 bits and the bit width of the output port is 128 bits, the message data can be read in the order of the message data in the message according to 512/128 ═ 4 times.

In an embodiment of the present application, if the bit width of the output port is smaller than the bit width of the input port, the memory space corresponding to the memory address of the message may be split, and the message data is read from the memory address of the split memory space, where the bit width of the read message data is the same as the bit width of the output port.

In step S240, if the bit width of the output port is greater than the bit width of the input port, the storage addresses of the multiple messages corresponding to the output port are obtained, and the message data having the same bit width as the bit width of the output port is read from the storage space corresponding to the storage addresses of the multiple messages.

In an embodiment of the present application, a sending order of a plurality of messages corresponding to an output port may be obtained, and message data having a bit width same as a bit width of the output port may be sequentially read from a storage space corresponding to storage addresses of a plurality of messages adjacent to the sending order according to the sending order of the plurality of messages.

In an embodiment of the present application, message characteristics of a plurality of messages corresponding to an output port, congestion conditions of the output port, and a PCIE ordering rule may be obtained; and determining the sending sequence of the plurality of messages corresponding to the output port based on the message characteristics of the plurality of messages corresponding to the output port, the congestion condition of the output port and the PCIE sequencing rule.

In an embodiment of the present application, the message characteristics of the message may be recorded in a message header, and the message characteristics of the message may be obtained from the message header.

In one embodiment of the present application, the message characteristic may include a timestamp of the received message, and the message characteristic may further include a position number of the message in a plurality of messages.

In one embodiment of the present application, the message may be a message fragment, and the message characteristic may include a location identifier of the message fragment in the message.

Still referring to fig. 2, in step S250, the message data having the same bit width as the bit width of the output port is transmitted to the output port.

In an embodiment of the present application, the output port may sequentially output the message data to the PCIE device according to a transmission order of sending the message data to the output port.

In an embodiment of the present application, before obtaining the storage address, the bit width of the output port, and the bit width of the input port corresponding to each message in the multiple messages in step S220 in fig. 2, the storage address, the bit width of the output port, and the bit width of the input port corresponding to each message may be recorded in a Packet Description (PD) corresponding to the message, and the storage address, the bit width of the output port, and the bit width of the input port corresponding to the message may be obtained from the message descriptor of each message.

In this embodiment, the storage address, the bit width of the output port, and the bit width of the input port corresponding to each packet are recorded in the packet descriptor corresponding to the packet, so that the storage address, the bit width of the output port, and the bit width of the input port corresponding to each packet can be conveniently obtained from the packet descriptor, and the packet can be conveniently read from the storage space corresponding to the storage address recorded in the packet descriptor.

In an embodiment of the present application, the message descriptor may be stored in a shared cache, and the message descriptor may be accessed using a mode of a virtual Output queue (voq), so that the virtual queue chain table manages access and scheduling of the message descriptor.

In an embodiment of the present application, after obtaining the message descriptor describing the memory address, in step S230 in fig. 2, if the bit width of the output port is smaller than the bit width of the input port, reading the message data having the same bit width as the bit width of the output port from the memory space corresponding to the memory address, which may include: modifying the bit width of the input port recorded in the message descriptor, wherein the modified bit width of the input port is the same as the bit width of the output port; and reading the message data with the same bit width as the modified bit width of the input port from the storage space corresponding to the storage address recorded in the message descriptor according to the modified bit width of the input port.

In this embodiment, since the bit width of the message is the same as the bit width of the input port, the bit width of the input port in the message descriptor is modified to be the same as the value of the bit width of the output port, that is, the bit width of the message recorded in the message descriptor is modified to be the same as the bit width of the output port, so that the bit width of the message data read according to the bit width of the message is the same as the bit width of the output port when reading data.

In an embodiment of the present application, an input port bit width representation value used for recording a bit width of an input port in a message descriptor may be modified, and the input port bit width representation value is modified to be the same as a bit width of an output port, where the bit width of the message is the same as the bit width of the input port, that is, the bit width of the message recorded in the message descriptor is modified to be the same as the bit width of the output port, so that message data read according to the bit width of the message can be output by the output port.

In an embodiment of the present application, if the bit width of the output port is smaller than the bit width of the input port, the number of times of reading the message data having the same bit width as the bit width of the output port from the storage space corresponding to the storage address can be determined according to the bit width of the output port and the bit width of the input port, the message descriptors are copied, the number of the copied message descriptors is the same as the number of times of reading the message data having the same bit width as the bit width of the output port from the storage space corresponding to the storage address, one message descriptor is used for reading the message data at a time, the bit width of the input port recorded in each message descriptor in the copied message descriptors can be modified, and the message data having the same bit width as the bit width of the output port can be read from the plurality of message descriptors respectively according to the arrangement order of the message data in the message, and respectively sending the message data read from the message descriptors to an output port in sequence, and outputting the read message data to the PCIE equipment, the PCIE chip or the PCIE chip controller in sequence by the output port.

In an embodiment of the present application, after obtaining the message descriptor describing the memory address, in step S230 in fig. 2, if the bit width of the output port is smaller than the bit width of the input port, reading the message data having the same bit width as the bit width of the output port from the memory space corresponding to the memory address, which may include: the message descriptor is split, the bit width of the message data stored in the storage space corresponding to the storage address recorded by the split message descriptor is the same as the bit width of the output port, the message data can be read from the storage space corresponding to the storage address recorded by the split message descriptor, and the bit width of the read message data is the same as the bit width of the output port.

In an embodiment of the present application, after obtaining the message descriptor describing the storage address, in step S240 in fig. 2, if the bit width of the output port is greater than the bit width of the input port, the method obtains the storage addresses of the multiple messages corresponding to the output port, and reads, from the storage space corresponding to the storage addresses of the multiple messages, message data having the same bit width as the bit width of the output port, and may include: acquiring a sending sequence of a plurality of messages corresponding to an output port; and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses recorded by the message descriptors of the messages adjacent to the transmission sequence.

In an embodiment of the present application, a plurality of message descriptors corresponding to a plurality of messages adjacent in a sending order may be combined, and message data having the same bit width as the bit width of the output port may be read from a storage space corresponding to a storage address recorded by the combined plurality of message descriptors.

In this embodiment, by combining the plurality of message descriptors, the bit width of the message data stored in the storage space corresponding to the storage address described in the combined plurality of message descriptors is the same as the bit width of the output port, the message data can be directly read from the storage space corresponding to the storage address described in the combined plurality of message descriptors, and the read message data is directly sent to the output port.

In one embodiment of the present application, the merging and splitting of the message descriptors may be related to a bit width of the input port and a bit width of the output port, and may be related to a ratio of the bit width of the input port to the bit width of the output port. For example, if the ratio of the bit width of the input port to the bit width of the output port is N (N >1), splitting the message descriptor into N parts; and if the ratio of the bit width of the input port to the bit width of the output port is 1/N (N >1), combining the N message descriptors into 1 part.

In an embodiment of the present application, a bit width of a message may be recorded in a message descriptor to replace a bit width of an input port of the message, merging or splitting of the message descriptor may be determined according to an actual length of the message, and a split number of the message descriptor or a number of merged message descriptors may be determined according to the actual length of the message.

In an embodiment of the present application, the PCIE Switch may set an input side, an output side, and a centralized side located between the input side and the output side for scheduling of the packet descriptors, where the packet descriptors are input from the input side, the centralized side performs scheduling on the packet descriptors, and the centralized side determines the packet descriptors output by the output side. When the PCIE Switch splits the message descriptors, splitting the message descriptors on the output side after sequencing scheduling; when the PCIE Switch combines the packet descriptors, the packet descriptors are combined on the input and output sides before the scheduling, and the centralized side performs scheduling on the combined packet descriptors.

In an embodiment of the present application, the centralized side may include a plurality of processing planes, each input port may correspond to one processing plane, and the packets in each processing plane are independently sequenced, so that the packets input by each input port are independently sequenced at the centralized side without interfering with each other.

In an embodiment of the present application, the centralized side may include a plurality of processing planes, each output port may correspond to one processing plane, and the packets in each processing plane are independently sequenced, so that the packets corresponding to each output port are independently sequenced at the centralized side without interfering with each other.

In an embodiment of the present application, the input side may include a plurality of independent processing planes, each input port may correspond to one processing plane, and messages in each processing plane are independently sequenced, so that the input ports are independent from each other and do not interfere with each other when inputting to the centralized side.

In an embodiment of the present application, referring to fig. 3, fig. 3 schematically illustrates a message transmission process according to an embodiment of the present application, where a bit width of a PORT _ H (High bit wide PORT, PORT High) in fig. 3 is greater than a bit width of a PORT _ L (Low bit wide PORT, PORT Low), and when the PORT _ L is an input PORT and the PORT _ H is an output PORT, a plurality of message fragments ls _ in0(Low slice 0, input 0-bit Low bit wide message fragment) -ls _ inN (Low slice in N, input N-bit Low message fragment) input through the PORT _ L PORT may be directly stored in sequence in ls0(Low slice 0, 0-bit Low message fragment) -lsN (Low slice N, N-bit Low bit wide message fragment) in a data Memory (data Memory), temporary storage is not needed, and register resources are saved. The packet descriptors lpd _ in0(low packet description in0, the packet descriptors of the incoming 0-bit low-bit width packet fragments) -lpd _ inN (low packet description in N, the packet descriptors of the incoming N-bit low-bit width packet fragments) arrive in order in N +1 clock cycles, but not immediately storing the message descriptor into a message descriptor Memory space (message descriptor Memory), calculating a clock cycle N +1 according to the bandwidth of a source PORT and the bandwidth of a destination PORT, merging the N +1 message descriptors into an hpd (high packet description, high bit width message descriptor), storing the hpd into the message descriptor Memory, scheduling and outputting the hpd, actually controlling the scheduling and outputting of the N +1 message segments, reading the N +1 message segments from the Memory space corresponding to the Memory address recorded by the message descriptor hpd, wherein the bit width of the read N +1 message segments meets the high bit width requirement of PORT _ H.

With reference to fig. 3, when the bit width of the PORT _ L (Low bit width PORT, PORT Low) in fig. 3 is greater than the bit width of the PORT _ H (High bit width PORT, PORT High) PORT, and the PORT _ H is used as an input PORT and the PORT _ L is used as an output PORT, the message data slice hs _ in0(High slice 0, input 0-bit High bit width message fragment) from the PORT _ H may be directly stored in hs0_0(High slice 0_0, 0-bit message data in 0-bit High bit width message fragment) -hs 0_ N (High slice 0_ N, N-bit message data in 0-bit High bit width message fragment) in the data Memory, which does not need to be temporarily stored, thereby saving register resources; the message descriptor hpd _ in0(high packet description in0, the message descriptor of the incoming 0-bit high-bit-width message fragment) is stored in the message descriptor Memory. When the packet descriptor hpd _ in0 is scheduled to be output, according to the bit width of the input PORT and the bit width of the output PORT, the hpd _ in0 is split into N +1 packet descriptors, and then lpd _ out0(low packet description out0, packet descriptors of output 0-bit low-bit-width packet fragments) -lpd _ outN (low packet description out N, packet descriptors of output N-bit low-bit-width packet fragments) are output in sequence, and the lpd _ out 0-lpd _ outN control the scheduled output of the packet data slice hs _ in0 from the PORT _ H, so that the transmission of data of a high-bit-width PORT to a low-bit-width PORT is realized, the circuit is simple to realize, no additional temporary storage is needed, and the register resource is saved.

In one embodiment of the present application, when the PORT _ L bit width is 4-lane and the PORT _ H bit width is 8-lane in fig. 3, N +1 may be 8/4 ═ 2, and N may be 1.

In one embodiment of the present application, when the PORT _ L bit width is 4-lane and the PORT _ H bit width is 16-lane in fig. 3, N +1 may be 16/4 ═ 4, and N may be 3.

In one embodiment of the application, in the clock period of the message header input, the 16-lane port can input 5 units of data at most, and the 4-lane port can input 2 units of data; in a TLP non-header input period, 4 unit data can be input into the 16-lane port, and 1 unit data can be input into the 4-lane port, which can be generated for packet data input in each clock period.

In an embodiment of the present application, a message may include a plurality of message segments, and a memory address, a bit width of an output port, and a bit width of an input port corresponding to each message segment may be recorded in a message descriptor corresponding to the message segment.

In one embodiment of the present application, the storage address in the message descriptor of each message segment may be the storage address of the message in which the message segment is located.

In one embodiment of the present application, the message descriptor may include a message characteristic, and the message characteristic may include a location identifier of the message fragment in the message. For example, a message may be divided into a Start Of Packet (SOP), a middle segment (Slice), and an End Of Packet (EOP), where the middle segment may be located between the Start Of Packet and the End Of Packet, the header may be located before the middle segment, and the End Of Packet may be located after the middle segment, and the SOP, the Slice, and the EOP may be used as position identifiers located at the beginning Of the message, the middle Of the message, and the End Of the message, respectively.

In an embodiment of the present application, the message descriptor of the middle segment may only include the storage address of the middle segment, and the message descriptor of the header or the message descriptor of the trailer records information such as message characteristics, bit width of the input port, bit width of the output port, and the like. Since the order of the header, the middle packet, and the trailer of a packet is known, if the header or trailer corresponding to the middle segment can be determined, the bit width of the input port and the bit width of the output port of the middle segment can be determined according to the packet descriptor of the header or trailer.

In this embodiment, by omitting the information in the message descriptor of the middle segment, or the message descriptor of the header or the tail of the message, the storage space occupied when the message descriptor is cached can be reduced, and resources can be saved.

In one embodiment of the present application, the message descriptor may include the time when the message entered the input port and the characteristics of the input port, which may include data bit width, clock frequency, protocol, etc.

In an embodiment of the present application, the message descriptor may include a message attribute, where the message attribute may include unicast and multicast, and if the message is determined to be a multicast message according to the attribute of the message, the number of output ports corresponding to the multicast message may be obtained, the message descriptor is copied to obtain the message descriptors having the same number as the output ports, each message descriptor corresponds to one output port, a storage address corresponding to the message, a bit width of the output port corresponding to the message descriptor, and a bit width of the input port are obtained from each message descriptor, and message data having the same bit width as the bit width of the output port corresponding to the message descriptor is read from a storage space corresponding to the storage address and sent to the output port corresponding to the message descriptor.

In this embodiment, the packet descriptor may be smaller than the bit width of the packet, and the copy packet descriptor replaces the copy packet, which may reduce the storage space required by the cache and reduce the pressure of the cache.

In one embodiment of the present application, the unicast packet may be forwarded to only 1 destination port; the multicast message can be copied and forwarded to two or more output ports; when the multicast message is copied and forwarded to a plurality of output ports, the same multicast message can be copied and forwarded at different times because of different output port flow and congestion conditions. The unicast message and the multicast message are stored in the global shared storage unit, and one copy of the unicast message and one copy of the multicast message can be stored. The unicast messages are managed and stored in a VOQ mode, and the multicast messages are managed and stored in a multicast group mode; the storage mode of the message descriptors of the unicast and multicast messages is the same as the message storage and management mode.

In an embodiment of the present application, if it is determined that the packet is a multicast packet according to the attribute of the packet, bit widths of a plurality of output ports corresponding to the multicast packet may be recorded in a packet descriptor.

In an embodiment of the present application, a set of identifiers of a plurality of output ports corresponding to a multicast packet may be recorded in a packet descriptor, the set of identifiers of the output ports may be obtained by routing query, and bit widths of the plurality of output ports corresponding to the multicast packet are obtained according to the set of identifiers of the output ports.

In one embodiment of the present application, the bit widths of the plurality of output ports may be recorded in a message descriptor corresponding to the identifications of the plurality of output ports.

In an embodiment of the present application, the order of copying the packet descriptors corresponding to the output ports may be determined according to packet characteristics, congestion conditions of the output ports, and a PCIE ordering rule.

In an embodiment of the present application, the message descriptor may set an access policy according to a bit width of the input port and a bit width of the output port, so as to accelerate message forwarding and compensate bandwidth waste caused by bit width collision.

In one embodiment of the present application, the message descriptor may be copied, and the message data may be read from the message descriptor while the read message descriptor is deleted.

In one embodiment of the present application, a multicast packet may be copied to multiple output ports simultaneously; a multicast message which can be copied to a plurality of ports in a time-sharing manner; during the process of copying a multicast packet to one or more output ports, a new copy process may not be initiated.

In an embodiment of the present application, access and scheduling of a multicast packet descriptor are managed and controlled by a multicast group number organization queue, the multicast packet belongs to a post-type PCIE TLP, and the multicast packet participates in a sorting schedule as a forwarding type packet (post, P) together with a Non-forwarding type packet (NP) and a return type packet (complexes, CPL). The multicast message scheduling meets the requirement of global sequencing; the multicast packet may be traversed by a post or Non-post or CPL type TLP that satisfies PCIE ordering rules.

In an embodiment of the present application, the packet descriptor of the multicast packet may include only the packet feature of the packet header segment of the multicast packet and the storage address of the entire multicast packet, so as to save the storage space. A Buffer (BUF) may be set for a packet descriptor of a multicast packet, fig. 4 schematically illustrates a structural schematic diagram of the Buffer of the packet descriptor according to an embodiment of the present application, for example, as shown in fig. 4, a packet feature of a packet header segment of a TLP multicast packet is stored in a PD _ SOP without TLP address; address0 is the memory address of the message segment with sequence number 0, address1 is the memory address of the message segment with sequence number 1, address2 is the memory address of the bit message segment with sequence number 2, address3 is the memory address of the message segment with sequence number 3, and address N is the memory address of the message segment with sequence number N.

In an embodiment of the present application, a Buffer (BUF) may be set for each packet descriptor of each multicast packet, and each Buffer may store one copied packet descriptor of the multicast packet.

In an embodiment of the present application, after the multicast packets are respectively sent to the output ports corresponding to the multicast packets, it may be checked whether the multicast packets are sent to all output ports corresponding to the multicast packets, and after it is determined that the multicast packets are sent to all output ports corresponding to the multicast packets, the multicast packets in the cache and the packet descriptors corresponding to the multicast packets are deleted, and the cache is released.

In the embodiment, after checking whether the multicast message is sent to all output ports corresponding to the multicast message, the cache is released, thereby avoiding missed sending of the multicast message and improving the accuracy of message transmission.

In an embodiment of the present application, if it is determined that the packet is a multicast packet according to the attribute of the packet recorded in the packet descriptor, the multicast packet descriptor may be scheduled to implement multicast packet transmission. Fig. 5 schematically shows a flowchart of a scheduling method of a multicast packet descriptor according to an embodiment of the present application, which may include steps S510 to S570 shown in fig. 5, where the scheduling method of the multicast packet descriptor may be executed by a PCIE Switch, and the execution subject may be the PCIE Switch101 in fig. 1:

in step S510, checking whether the multicast packet descriptor is valid;

in step S520, it is checked whether the valid multicast packet descriptor is scheduled;

in step S530, determining a position of a multicast message segment corresponding to the multicast message descriptor in the multicast message, and if the multicast message segment corresponding to the multicast message descriptor is an SOP and is scheduled, checking whether a scheduling output port covers an output port bitmap (bitmap) carried by the message descriptor; if the multicast message descriptor is covered, the multicast message descriptor is not stored; if the Output port bitmap carried by the message descriptor is not covered, filtering the covered Output port, updating the multicast bitmap, storing the characteristic field of the message descriptor, and storing the storage address carried by the message descriptor into a First unit of an FIFO (First-in First-out) memory;

in step S540, if the multicast packet segment corresponding to the multicast packet descriptor is an SOP and is not scheduled, storing the feature field of the multicast packet descriptor, and leaving the multicast bitmap unchanged; storing the storage address carried in the message descriptor into a first unit of the FIFO;

in step S550, if the multicast packet segment corresponding to the multicast packet descriptor is not SOP or EOP, extracting a storage address of the multicast packet segment in the packet descriptor, and storing the storage address in a unit located after the first unit in the FIFO;

in step S560, if the multicast packet segment corresponding to the multicast packet descriptor is an EOP, extracting the multicast packet segment storage address in the packet descriptor, and storing the multicast packet segment storage address in the FIFO behind the unit for storing the multicast packet segment storage address in step S550, where the packet descriptor scheduling of all multicast packet segments of the multicast packet is completed;

in step S570, when the previous round of multicast replication scheduling is completed, checking an output port bitmap which is not replicated, if the output port is not fully covered, starting from SOP, regenerating the cached multicast message descriptor feature field and multicast message storage address according to the order and format of the original multicast message descriptor, re-scheduling, noting that the fan-out bitmap carried in the generated multicast message descriptor is the bitmap after the replicated port is filtered, returning an effective result by scheduling, and filtering the replicated port again according to the scheduling result; and repeating the step S570 until the multicast fan-out bitmap is full coverage, clearing the characteristic field and the address of the cached multicast message descriptor, and releasing the message storage address.

In an embodiment of the present application, whether the multicast packet descriptor is valid may be checked by checking whether the packet descriptor includes a storage address, packet characteristics, packet attributes, and the like of the packet.

In the embodiment shown in fig. 5, the multicast packet is copied by copying the multicast packet descriptor, and after the multicast packet descriptor is scheduled and output, the output port bitmap carried in the multicast packet descriptor is checked, so that the multicast copy function is completed by the multicast packet descriptor. In the output port bitmap, each bit represents an output port, and the key value corresponding to a certain output port is 1, which indicates that a multicast message is to be copied to the output port. Multicast message descriptors which send ordering scheduling participation requests to all output ports indicated by output port bitmaps carried by the multicast message descriptors, after a scheduling result is returned, starting to read the message descriptors corresponding to the multicast message segments SOP, copying and forwarding the message to the current reproducible port, and reading the message descriptors corresponding to the message segments EOP all the time; meanwhile, comparing the output port bitmap with a scheduling result, judging whether all output ports identified by the output port bitmap are covered by the current scheduling, if so, releasing a message storage address after reading the message; otherwise, the message storage address is not released, the corresponding bitmap bit of the output port which is scheduled to be copied is filtered, and the bitmap of the output port which is not copied is reserved. When the first round of scheduling replication can not complete the replication of the output port bitmap identification, after the first round of replication is finished, the reserved multicast message descriptor, the filtered output port bitmap and the multicast message storage address are combined again according to the message segments of the original multicast message, the message descriptor is generated to continue applying for scheduling output to the output port identified by the filtered output port bitmap, and the first round of scheduling process is repeated. After the operation of copying the multicast message to all the output ports indicated by the output port bitmap is completed, the output port bitmap is full-covered, the storage address of the whole multicast message is released, and the message descriptor of the multicast message is deleted.

In an embodiment of the present application, the method for scheduling a multicast packet descriptor may also be implemented by using the flowchart shown in fig. 6, where fig. 6 schematically shows a flowchart of a method for scheduling a multicast packet descriptor according to an embodiment of the present application, the method for scheduling a multicast packet descriptor may be executed by a PCIE Switch, an execution subject may be the PCIE Switch101 in fig. 1, and the method for scheduling a multicast packet descriptor may include steps S610 to S6110, which are described in detail as follows:

in step S610, it is determined whether one multicast packet segment PD in the multicast packet PD is valid.

In an embodiment of the present application, if the multicast packet segment PD is invalid, step S6110 is executed.

In step S620, if the multicast packet segment PD is valid, it is determined whether the scheduling of the multicast packet segment PD is valid.

In step S630, if the scheduling of the multicast message segment PD is invalid, it is determined whether the multicast message segment PD corresponds to an SOP in a multicast message.

In step S640, the multicast message segment PD corresponds to the SOP in the multicast message, the storage address field of the multicast message segment in the SOP PD is extracted and stored in the first unit of the address FIFO, the output port bitmap of the multicast message is unchanged, and step S6110 is executed.

In an embodiment of the present application, if the multicast packet segment PD does not correspond to an SOP in a multicast packet, step S670 is skipped.

In step S650, if the scheduling of the multicast packet segment PD is valid, it is determined whether the scheduling of the multicast packet segment PD covers all output ports corresponding to the multicast packet.

In an embodiment of the present application, if the multicast packet segment PD is scheduled to cover all output ports corresponding to the multicast packet, step S6110 is executed.

In step S660, if the scheduling of the multicast packet segment PD does not cover all output ports corresponding to the multicast packet, it is determined whether the multicast packet segment PD corresponds to an SOP in the multicast packet.

If the multicast message segment PD does not correspond to the SOP in the multicast message, step S670 is executed, and the storage address field of the multicast message segment in the multicast message segment PD is extracted and stored in the address FIFO.

In step S680, it is determined whether the multicast packet segment PD corresponds to an EOP in the multicast packet.

In an embodiment of the present application, if the multicast packet segment PD corresponds to an EOP in a multicast packet, the multicast packet PD finishes scheduling.

In an embodiment of the present application, if the multicast packet segment PD does not correspond to the EOP in the multicast packet, step S6110 is executed.

In step S690, if the multicast message segment PD corresponds to SOP in the multicast message, a storage address field of the multicast message segment in the SOP PD is extracted and stored in the first unit of the address FIFO, the output port bitmap of the multicast message filters the scheduled output port, a message feature field in the PD is extracted, the message feature field is stored in the BUF, and step S6110 is executed.

In step S6100, steps S610 to S690 are performed on the next multicast packet segment PD of the multicast packet segment in the multicast packet.

In the embodiment of fig. 6, the packet descriptors corresponding to the plurality of packet segments of the multicast packet are determined one by one, so that the packet descriptor corresponding to each packet segment of the multicast packet can be scheduled, and the multicast packet can cover each output port corresponding to the multicast packet.

The following describes an embodiment of an apparatus of the present application, which may be used to implement the method for packet switching transmission on ports with different bandwidths in the above-mentioned embodiment of the present application. For details that are not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method for packet switching transmission of ports with different bandwidths described above.

Figure 7 schematically illustrates a block diagram of a different bandwidth port message switching transmission device according to one embodiment of the present application.

Referring to fig. 7, an apparatus 700 for packet switching transmission on ports with different bandwidths according to an embodiment of the present application includes: a receiving unit 701, an acquiring unit 702, a reading unit 703 and a transmitting unit 704.

In some embodiments of the present application, the receiving unit 701 is configured to receive a plurality of messages input by an input port, where the messages include message data, and cache the plurality of messages; the obtaining unit 702 is configured to obtain a storage address, a bit width of an output port, and a bit width of an input port corresponding to each of the plurality of messages; the reading unit 703 is configured to, if the bit width of the output port is smaller than the bit width of the input port, read the message data having the same bit width as the bit width of the output port from the storage space corresponding to the storage address; if the bit width of the output port is larger than the bit width of the input port, acquiring the storage addresses of the messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage addresses of the messages; the sending unit 704 is configured to send the message data having the same bit width as the bit width of the output port to the output port.

In some embodiments of the present application, based on the foregoing solution, the obtaining unit 702 is configured to: before acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message in a plurality of messages, recording the storage address, the bit width of the output port and the bit width of the input port corresponding to each message in a message descriptor corresponding to the message; and acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message from the message descriptor of each message.

In some embodiments of the present application, based on the foregoing scheme, the packet includes a plurality of packet fragments, and the obtaining unit 702 is configured to: and recording the storage address corresponding to each message segment, the bit width of the output port and the bit width of the input port in the message descriptor corresponding to the message segment.

In some embodiments of the present application, based on the foregoing scheme, the reading unit 703 is configured to: modifying the bit width of the input port recorded in the message descriptor, wherein the modified bit width of the input port is the same as the bit width of the output port; and reading the message data with the same bit width as the modified bit width of the input port from the storage space corresponding to the storage address recorded in the message descriptor according to the modified bit width of the input port.

In some embodiments of the present application, based on the foregoing scheme, the reading unit 703 is configured to: if the bit width of the output port is smaller than the bit width of the input port, determining the times of reading the message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage address according to the bit width of the output port and the bit width of the input port; copying the message descriptors, wherein the number of the copied message descriptors is the same as the number of times of reading the message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage address, and one message descriptor is used for reading the message data at one time; and modifying the bit width of the input port recorded in each message descriptor in the copied message descriptors.

In some embodiments of the present application, based on the foregoing scheme, the reading unit 703 is configured to: acquiring a sending sequence of a plurality of messages corresponding to an output port; and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses recorded by the message descriptors of the messages adjacent to the transmission sequence.

In some embodiments of the present application, based on the foregoing scheme, the reading unit 703 is configured to: acquiring message characteristics of a plurality of messages corresponding to the output port, the congestion condition of the output port and a PCIE sequencing rule; and determining the sending sequence of the plurality of messages corresponding to the output port based on the message characteristics of the plurality of messages corresponding to the output port, the congestion condition of the output port and the PCIE sequencing rule.

In some embodiments of the present application, based on the foregoing scheme, the reading unit 703 is configured to: combining a plurality of message descriptors corresponding to a plurality of messages adjacent in the sending sequence, and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address recorded by the combined plurality of message descriptors.

In some embodiments of the present application, based on the foregoing solution, the obtaining unit 702 is configured to: acquiring the attribute of a message, if the message is determined to be a multicast message according to the attribute of the message, acquiring the number of output ports corresponding to the multicast message, copying message descriptors to obtain the same number of message descriptors as the output ports, wherein each message descriptor corresponds to one output port; and acquiring a storage address corresponding to the message, a bit width of an output port corresponding to the message descriptor and a bit width of an input port from each message descriptor.

As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or program product. Accordingly, various aspects of the present application may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

An electronic device 80 according to this embodiment of the present application is described below with reference to fig. 8. The electronic device 80 shown in fig. 8 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown in fig. 8, the electronic device 80 is in the form of a general purpose computing device. The components of the electronic device 80 may include, but are not limited to: the at least one processing unit 81, the at least one memory unit 82, a bus 83 connecting different system components (including the memory unit 82 and the processing unit 81), and a display unit 84.

Wherein the storage unit stores program code that can be executed by the processing unit 81 such that the processing unit 81 performs the steps according to various exemplary embodiments of the present application described in the section "example methods" above in this specification.

The storage unit 82 may include readable media in the form of volatile storage units, such as a random access storage unit (RAM)821 and/or a cache storage unit 822, and may further include a read only storage unit (ROM) 823.

The storage unit 82 may also include a program/utility 824 having a set (at least one) of program modules 825, such program modules 825 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Bus 83 may be any of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 80 may also communicate with one or more external devices (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 80, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 80 to communicate with one or more other computing devices. Such communication may be through input/output (I/O) interfaces 85. Also, the electronic device 80 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet) via the network adapter 86. As shown, the network adapter 86 communicates with the other modules of the electronic device 80 via the bus 83. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 80, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to make a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) execute the method according to the embodiments of the present application.

There is also provided, in accordance with an embodiment of the present application, a computer-readable storage medium having stored thereon a program product capable of implementing the above-described method of the present specification. In some possible embodiments, various aspects of the present application may also be implemented in the form of a program product comprising program code for causing a terminal device to perform the steps according to various exemplary embodiments of the present application described in the "exemplary methods" section above of this specification, when the program product is run on the terminal device.

In some embodiments of the present application, a program product for implementing the above method of embodiments of the present application is provided, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the present application, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A method for exchanging and transmitting messages of ports with different bandwidths is characterized by comprising the following steps:

receiving a plurality of messages input by an input port, wherein the messages comprise message data, and caching the messages;

acquiring a storage address corresponding to each message in the plurality of messages, a bit width of an output port and a bit width of an input port;

if the bit width of the output port is smaller than the bit width of the input port, reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address;

if the bit width of the output port is greater than the bit width of the input port, acquiring storage addresses of a plurality of messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses of the plurality of messages;

and sending the message data with the bit width same as that of the output port to the output port.

2. The method according to claim 1, wherein before obtaining the memory address, the bit width of the output port, and the bit width of the input port corresponding to each packet in the plurality of packets, the method comprises:

recording the storage address corresponding to each message, the bit width of the output port and the bit width of the input port in a message descriptor corresponding to the message;

the obtaining of the storage address, the bit width of the output port and the bit width of the input port corresponding to each message in the plurality of messages includes:

and acquiring a storage address, a bit width of an output port and a bit width of an input port corresponding to each message from the message descriptor of each message.

3. The method according to claim 2, wherein the packet includes a plurality of packet fragments, and the recording a storage address, a bit width of an output port, and an input port corresponding to each packet in a packet descriptor corresponding to the packet includes:

and recording the storage address corresponding to each message segment, the bit width of the output port and the bit width of the input port in the message descriptor corresponding to the message segment.

4. The method according to claim 2, wherein the reading, from the memory space corresponding to the memory address, the packet data having the same bit width as the bit width of the output port includes:

modifying the bit width of the input port recorded in the message descriptor, wherein the modified bit width of the input port is the same as the bit width of the output port;

and reading the message data with the same bit width as the modified bit width of the input port from the storage space corresponding to the storage address recorded in the message descriptor according to the modified bit width of the input port.

5. The method according to claim 4, wherein if the bit width of the output port is smaller than the bit width of the input port, determining the number of times of reading the message data having the same bit width as the bit width of the output port from the memory space corresponding to the memory address according to the bit width of the output port and the bit width of the input port;

copying the message descriptors, wherein the number of the copied message descriptors is the same as the number of times of reading the message data with the same bit width as the bit width of the output port from the storage space corresponding to the storage address, and one message descriptor is used for reading the message data at one time;

the modifying the bit width of the input port recorded in the message descriptor includes:

modifying the bit width of the input port recorded in each message descriptor in the copied message descriptors.

6. The method according to claim 2, wherein the reading, from the memory space corresponding to the memory addresses of the plurality of packets, packet data having a bit width same as a bit width of the output port includes:

acquiring a sending sequence of a plurality of messages corresponding to the output port;

and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses recorded by the message descriptors of the messages adjacent to the transmission sequence.

7. The method according to claim 6, wherein the obtaining the sending order of the plurality of packets corresponding to the output port comprises:

acquiring message characteristics of a plurality of messages corresponding to the output port, the congestion condition of the output port and a PCIE sequencing rule;

and determining the sending sequence of the plurality of messages corresponding to the output port based on the message characteristics of the plurality of messages corresponding to the output port, the congestion condition of the output port and the PCIE sequencing rule.

8. The method according to claim 6, wherein reading the packet data having the same bit width as the bit width of the output port from the memory space corresponding to the memory address recorded in the packet descriptors of the packets adjacent to the transmission order comprises:

and combining a plurality of message descriptors corresponding to a plurality of messages adjacent to the sending sequence, and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage address recorded by the combined plurality of message descriptors.

9. The method according to claim 2, wherein the attributes of the packets are obtained, and if the packets are determined to be multicast packets according to the attributes of the packets, the number of output ports corresponding to the multicast packets is obtained, and the packet descriptors are copied to obtain the same number of packet descriptors as the output ports, where each packet descriptor corresponds to one output port;

the obtaining of the bit width of the storage address, the output port and the input port corresponding to each message in the plurality of messages includes:

and acquiring a storage address corresponding to the message, a bit width of an output port corresponding to the message descriptor and a bit width of the input port from each message descriptor.

10. A device for exchanging and transmitting messages of ports with different bandwidths is characterized by comprising:

the receiving unit is configured to receive a plurality of messages input by the input port, wherein the messages comprise message data, and the plurality of messages are cached;

the acquiring unit is configured to acquire a storage address corresponding to each message in the plurality of messages, a bit width of an output port and a bit width of an input port;

a reading unit configured to read, if the bit width of the output port is smaller than the bit width of the input port, message data having the same bit width as the bit width of the output port from a storage space corresponding to the storage address; if the bit width of the output port is greater than the bit width of the input port, acquiring storage addresses of a plurality of messages corresponding to the output port, and reading message data with the same bit width as the bit width of the output port from a storage space corresponding to the storage addresses of the plurality of messages;

and the sending unit is configured to send the message data with the bit width same as that of the output port to the output port.