CN113986792A

CN113986792A - Data bit width conversion method and communication equipment

Info

Publication number: CN113986792A
Application number: CN202111248769.1A
Authority: CN
Inventors: 王彬; 林晖; 何磊; 张志强
Original assignee: New H3C Security Technologies Co Ltd
Current assignee: New H3C Security Technologies Co Ltd
Priority date: 2021-10-26
Filing date: 2021-10-26
Publication date: 2022-01-28
Anticipated expiration: 2041-10-26
Also published as: CN113986792B

Abstract

The application provides a data bit width conversion method and communication equipment, wherein the method comprises the following steps: determining the minimum input bit width according to the bit widths of the multiple receiving ports and the bit width of the cache unit; splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of each cache subunit is the minimum input bit width; determining the write operation timing sequence of each receiving port to the plurality of cache subunits; and when each receiving port receives data, storing the received data into the storage address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port. In the application, the input and output bit width conversion of the ports of different types is realized by splitting the cache unit and setting the control time sequences of the ports of different types, so that the bit width conversion efficiency of data is improved, and the resource waste is reduced.

Description

Data bit width conversion method and communication equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to a data bit width conversion method and a communications device.

Background

In a communication system including various communication devices, various input/output interfaces are often involved, and the bit width requirements of data between the various interfaces are different, so that bit width conversion between the various interfaces is required.

With the development of communication technology, the transmission of high-speed signals is more and more commonly used in design, and higher requirements are put forward on data bit width conversion, however, the existing bit width conversion device needs to be provided with more buffers, which results in resource waste.

Disclosure of Invention

The application aims to provide a data bit width conversion method and communication equipment so as to improve the data bit width conversion efficiency and reduce resource waste.

A first aspect of the present application provides a data bit width conversion method, which is applied to a receiving module, where the receiving module includes a plurality of receiving ports and a cache unit, and bit widths of at least two receiving ports in the plurality of receiving ports are different, and the method includes:

determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the cache unit;

splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of each cache subunit is the minimum input bit width;

determining the write operation timing sequence of each receiving port to the plurality of cache subunits;

and when each receiving port receives data, storing the received data into the storage address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port.

A second aspect of the present application provides a data bit width conversion method, which is applied to a sending module, where the sending module includes a buffer unit and multiple sending ports, and bit widths of the multiple sending ports are the same, and the method includes:

splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of each cache subunit is the same as that of the sending port;

determining the read operation timing sequence of each sending port to the plurality of cache subunits;

determining a storage address and a target sending port of data to be sent in the cache unit;

and sending the data in the storage address according to the reading operation time sequence corresponding to the target sending port.

A third aspect of the present application provides a data bit width conversion method, which is applied to a data bit width conversion device, where the data bit width conversion device includes multiple receiving ports, a buffer unit, and multiple sending ports, bit widths of at least two receiving ports in the multiple receiving ports are different, and bit widths of the multiple sending ports are the same, and the method includes:

determining the minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the cache unit; splitting the cache unit into a plurality of first cache subunits with the same bit width, wherein the bit width of each first cache subunit is the minimum input bit width; determining the write operation timing sequence of each receiving port to the plurality of cache subunits;

splitting the cache unit into a plurality of second cache subunits with the same bit width, wherein the bit width of the second cache subunits is the same as that of the sending port; determining the read operation timing sequence of each sending port to the plurality of second cache subunits;

when each receiving port receives data, storing the received data into the target storage address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port;

determining a target sending port of the data in the target storage address;

and sending the data in the target storage address according to the read operation time sequence corresponding to the target sending port.

A fourth aspect of the present application provides a receiving module, comprising:

the buffer unit comprises a plurality of receiving ports and a buffer unit, wherein at least two receiving ports in the plurality of receiving ports have different bit widths;

a determining unit, configured to determine a minimum input bit width according to the bit widths of the multiple receiving ports and the bit width of the cache unit; splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of each cache subunit is the minimum input bit width; determining the write operation timing sequence of each receiving port to the plurality of cache subunits;

and the receiving unit is used for storing the received data into the storage address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port when each receiving port receives the data.

A fifth aspect of the present application provides a transmitting module, including:

the system comprises a cache unit and a plurality of sending ports, wherein the bit widths of the sending ports are the same;

the determining unit is used for splitting the cache unit into a plurality of cache subunits with the same bit width, and the bit width of each cache subunit is the same as that of the sending port; determining the read operation timing sequence of each sending port to the plurality of cache subunits;

the sending unit is used for determining a storage address of data to be sent in the cache unit and a target sending port; and sending the data in the storage address according to the reading operation time sequence corresponding to the target sending port.

A sixth aspect of the present application provides a shift width input/output device, including:

the system comprises a plurality of receiving ports, a cache unit and a plurality of sending ports, wherein bit widths of at least two receiving ports in the plurality of receiving ports are different, and the bit widths of the plurality of sending ports are the same;

a determining module, configured to determine a minimum input bit width according to the bit widths of the multiple receiving ports and the bit width of the cache unit; splitting the cache unit into a plurality of first cache subunits with the same bit width, wherein the bit width of each first cache subunit is the minimum input bit width; determining the write operation timing sequence of each receiving port to the plurality of cache subunits;

the determining module is further configured to split the cache unit into a plurality of second cache subunits with the same bit width, where the bit width of the second cache subunit is the same as the bit width of the sending port; determining the read operation timing sequence of each sending port to the plurality of second cache subunits;

the receiving module is used for storing the received data into the target storage address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port when each receiving port receives the data;

the sending module is used for determining a target sending port of the data in the target storage address; and sending the data in the target storage address according to the read operation time sequence corresponding to the target sending port.

A seventh aspect of the present application provides a communication apparatus comprising the variable bandwidth input-output device described in the sixth aspect.

Compared with the prior art, the data bit width conversion method and the communication device provided by the application split the cache unit into the plurality of cache subunits with the same bit width, the receiving port stores the received data into the storage address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port, and the sending port sends the data in the storage address according to the corresponding read operation time sequence. In the application, the input and output bit width conversion of the ports of different types is realized by splitting the cache unit and setting the control time sequences of the ports of different types, so that the bit width conversion efficiency of data is improved, and the resource waste is reduced.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a schematic structural diagram of a conventional communication device;

fig. 2 is a schematic diagram of a conventional message input/output device;

FIG. 3 is a schematic diagram of a specific receiving module provided in the present application;

FIG. 4 illustrates one of the write operation timings for the receive port provided herein;

FIG. 5 illustrates a second timing sequence of a write operation of the receive port provided herein;

FIG. 6 is a flow chart illustrating a data bit width conversion method provided in the present application;

FIG. 7 is a schematic diagram of a specific sending module provided herein;

FIG. 8 illustrates a read operation timing sequence for a transmit port provided herein;

FIG. 9 is a flow chart illustrating another data bit width conversion method provided herein;

FIG. 10 is a schematic diagram of a specific variable bandwidth input-output device provided by the present application;

fig. 11 shows a flowchart of another data bit width conversion method provided in the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which this application belongs.

In addition, the terms "first" and "second", etc. are used to distinguish different objects, rather than to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of a conventional communication device, and as shown in fig. 1, the communication device includes a panel port (i.e., an input interface of the communication device), an FPGA (field programmable gate array), and a backplane port (i.e., an interconnection interface of the communication device). As shown in FIG. 1, the panel port has 10 input interfaces, and supports multi-rate, some 25G, some 10G, and some 5G/1G; the backplane port supports 4 sets of interconnect interfaces, each set supporting 10G. Serdes is an acronym for Serializer/Deserializer, which is a time division multiplexing, point-to-point serial communication technique.

The FPGA implements interface conversion in the communication device: in the uplink direction, after receiving the message in the panel port direction, certain processing is carried out, and then the message is forwarded to the back panel port according to the forwarding specification; and in the downlink direction, receiving the message in the direction of the back panel port and forwarding the message to the panel port. The direction that the upstream panel port receives the packet and forwards the packet to the back panel port is discussed in the application, and the direction that the downstream back panel port forwards the packet to the panel port is processed similarly, which is not described in detail.

For the messages received by the panel port, in general, a complete message needs to be formed first, and then the message is analyzed and forwarded to the corresponding backplane port according to the analysis result.

Fig. 2 is a schematic diagram of a conventional message input/output device.

In fig. 2, there are three types of MAC (physical layer interface) inputs. The input bit width of the low-rate MAC (receiving port 0-7) is 32 bit widths, the input bit width of the medium-rate MAC (receiving port 8) is 256bit widths, and the input bit width of the high-rate MAC (receiving port 9) is 512 bit widths.

Firstly, after each MAC receives external input, asynchronous transition is carried out, and an interface clock is synchronized to an internal master clock; then, reading out the data in the receiving FIFO (first-in first-out buffer memory) and carrying out bit width conversion; finally, the data is written into the receive packet level FIFO. Receiving the packet-level FIFO requires that a plurality of packets can be loaded, consuming relatively more storage resources.

And the scheduling sending module reads the data in the receiving packet-level FIFO according to a polling mode and distributes the data to each sending port in the sending module.

And the sending module stores the message into the packet-level FIFO firstly, plays a role of absorbing burst, is convenient for bit width conversion and clock domain conversion later, and finally sends the message to a sending port for sending after the bit width conversion and the asynchronous conversion.

The above prior art has the following disadvantages:

1) two levels of large message caches are required, and resource sharing is not achieved. For example, in the case of no traffic in the 25G packet receiving direction, the first level packet buffer does not play a role in absorbing bursts.

2) The input needs to be firstly subjected to bit width conversion and then to other functional processing, and the resource waste is more.

3) The output is distributed first and then processed with variable bit width, and for the functional module with variable bit width, the consumed logic resources are relatively large.

In view of the above, embodiments of the present application provide a data bit width conversion method, a receiving module, a sending module, a variable bandwidth input/output device, and a communication apparatus, which are described below with reference to the accompanying drawings.

The receiving module provided by the application is used for the data receiving side of the variable-width input/output device, and comprises:

the device comprises a plurality of receiving ports and a cache unit, wherein at least two receiving ports in the plurality of receiving ports have different bit widths, and each receiving port corresponds to a receiving cache;

Please refer to fig. 3, which shows a schematic diagram of a specific receiving module provided in the present application, wherein the receiving ports are MAC _ RX 0-9, which have 10 receiving ports, wherein the bit widths of MAC _ RX 0-7 are 32 bit widths, the bit width of MAC _ RX8 is 256bit widths, and the bit width of MAC _ RX9 is 512 bit widths. The bit width of the cache unit is 512 bit width, that is, each storage address corresponds to 512 bit width data. Each receiving port also corresponds to a receiving buffer (FIFO), as shown in fig. 3, MAC _ RX 0-9 corresponds to receiving buffers 0-9, and the data received by each receiving port is stored in the receiving buffer first, and then waits for the write operation timing to arrive and then written into the buffer unit.

If the minimum input bit width of the MAC _ RX 0-9 is 32 bit width, the buffer unit needs to be split according to the 32 bit width, 512/32 is 16, and the buffer unit is split into 16 blocks of buffer subunits with 32 bit width, and the 16 buffer subunits are respectively 0 th RAM to 15 th RAM.

And then determining the write operation time sequence of each receiving port to the 0 th RAM to the 15 th RAM, wherein the constraint condition of the operation time sequence is to ensure that no packet is lost. Fig. 4 shows the write operation timing of the 0 th to 7 th receiving ports provided in the present application. Fig. 5 shows the write operation timing of the 8 th receiving port and the 9 th receiving port provided in the present application. In fig. 4 and 5, -0 is the 0 th receiving port, -1 is the 1 st receiving port, and so on. The write operation timing for each receive port is determined in fig. 4 and 5.

Setting a timer from T0 to T15, determining 16 timings, dividing the 16 timings into odd timings (e.g., T1, T3, etc.) and even timings (e.g., T0, T2, etc.), operating the odd-numbered line RAM (e.g., 1 st, 3 rd, 5 th block RAM) at the odd timings by the first 8 receiving ports, and operating the even-numbered line RAM (e.g., 2 nd, 4 th, 6 th block RAM) at the even timings. Each receiving port can complete a conversion operation with a bit width of 32-512 bits by 16 time sequences and one period, and the write bit width is realized.

The present application operates by dividing the RAM into odd and even rows because there is a receive port 9 that does not require a variable bit width for bit width 512 and a receive port 8 that requires a variable bit width for bit width 256. Dividing the RAM into odd and even rows to operate may free the RAM from timing for use by receive ports 8 and 9. The two ports, i.e., the receive port 8 and the receive port 9, operate the even-numbered line RAM at the odd timing and the odd-numbered line RAM at the even timing, and can operate 256 bits at most at a time.

As shown in FIG. 5, the 8 th receiving port (256 bits wide) occupies the RAM write bus in the first four timings, and the 9 th receiving port (512 bits wide) occupies the RAM write bus in the last four timings. The last 8 sequences are the repetition periods of the first 8 sequences.

Fig. 6 shows a flowchart of a data bit width conversion method provided in the present application, where the method is applied to the receiving module provided in the foregoing embodiment, and the method includes:

s101, determining a minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the cache unit;

s102, splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of each cache subunit is the minimum input bit width;

s103, determining the write operation time sequence of each receiving port to the plurality of cache subunits;

and S104, when each receiving port receives the data, storing the received data into the memory address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port.

According to the receiving module and the data bit width conversion method applied to the receiving module, the same cache unit is operated by port skip time sequence writing, multiple bit widths are converted into one bit width at the same time, compared with the prior art, the receiving module does not need to be provided with one cache unit for each port, the same cache unit is operated by multiple ports in time sequence, and the cache utilization rate is improved.

The application provides a sending module for a data sending side of a variable bit width input/output device, the sending module comprising:

Please refer to fig. 7, which illustrates a schematic diagram of a specific transmitting module provided in the present application, wherein the transmitting ports are MAC _ TX 0-3, and there are 4 transmitting ports, and bit widths of MAC _ TX 0-3 are all 128 bits wide. The bit width of the cache unit is 512 bit width, that is, each storage address corresponds to 512 bit width data. As shown in fig. 7, each transmitting port waits for the read operation timing to re-read the data in the buffer unit for transmission.

If the transmission bit width of the MAC _ TX 0-3 is 128 bits wide, the buffer unit is split according to the 128 bits wide, 512/128 is 4, the buffer unit is split into 4 blocks of buffer subunits with 128 bits wide, and the 4 blocks of buffer subunits are respectively the 0 th block RAM to the 3 rd block RAM.

And then determining the read operation time sequence of each sending port to the 0 th RAM to the 3 rd RAM, wherein the constraint condition of the operation time sequence is to ensure that no packet is lost. Fig. 8 shows the read operation timing of the 0 th to 3 rd transmitting ports provided in the present application. In fig. 8, -0 is the 0 th transmit port, -1 is the 1 st transmit port, -2 is the 2 nd transmit port, and-3 is the 3 rd transmit port. The read operation timing for each transmit port is determined in fig. 8.

Setting a timer T0-T3, and determining 4 time sequences, wherein the specific time sequences shown in FIG. 8 are as follows:

in the 0 th time sequence, the read address of the 0 th RAM is distributed to the 0 th sending port, the read address of the 1 st RAM is distributed to the 3 rd sending port, the read address of the 2 nd RAM is distributed to the 2 nd sending port, and the read address of the 3 rd RAM is distributed to the 1 st sending port;

in the 1 st time sequence, the read address of the 0 th RAM is distributed to the 1 st sending port, the read address of the 1 st RAM is distributed to the 0 th sending port, the read address of the 2 nd RAM is distributed to the 3 rd sending port, and the read address of the 3 rd RAM is distributed to the 2 nd sending port;

in the 2 nd time sequence, the read address of the 0 th RAM is distributed to the 2 nd sending port, the read address of the 1 st RAM is distributed to the 1 st sending port, the read address of the 2 nd RAM is distributed to the 0 th sending port, and the read address of the 3 rd RAM is distributed to the 3 rd sending port;

in the 3 rd time sequence, the read address of the 0 th RAM is distributed to the 3 rd sending port, the read address of the 1 st RAM is distributed to the 2 nd sending port, the read address of the 2 nd RAM is distributed to the 1 st sending port, and the read address of the 3 rd RAM is distributed to the 0 th sending port.

The sending module realizes the change of the sending side bit width from 512 to 128 naturally through accurate time sequence control, and does not need a special bit width conversion module. In the prior art, 4 sets of 512-bit wide data are read out, and four 512-to-128 modules are used to implement bit width conversion.

Fig. 9 shows a flowchart of a data bit width conversion method provided in the present application, where the method is applied to the sending module provided in the foregoing embodiment, and the method includes:

s201, splitting the cache unit into a plurality of cache subunits with the same bit width, wherein the bit width of each cache subunit is the same as that of the sending port;

s202, determining the read operation time sequence of each sending port to the plurality of cache subunits;

s203, determining a storage address and a target sending port of data to be sent in the cache unit;

and S204, sending the data in the storage address according to the reading operation time sequence corresponding to the target sending port.

According to the sending module and the data bit width conversion method applied to the sending module, the same cache unit is read in a port skip time sequence, bit width conversion is achieved, compared with the prior art, the bit width conversion is achieved without a special module, and resources are greatly saved.

The application also provides a variable-width input/output device, which comprises the receiving module and the sending module in the embodiment of the application; wherein, the receiving module and the sending module share one buffer unit.

Please refer to fig. 10, which shows a schematic diagram of a specific variable bandwidth input/output device provided in the present application. Since the receiving module and the sending module share one buffer unit, for the receiving module, the buffer unit is split according to 32-bit width, and 512/32 is 16, which is split into 16 buffer sub-units with 32-bit width; for the sending module, the buffer unit is split according to 128-bit width, and 512/128 is 4, and the buffer unit is split into 4 blocks of 128-bit width buffer subunits.

In some embodiments of the present application, as shown in fig. 10, the variable bit width input/output apparatus further includes:

and the scheduling module is used for scheduling the storage address and the sending port of the data between the receiving module and the sending module. In fig. 10, 100 and 200 are information storage units required by the scheduling module.

and the address management module is used for recovering and initializing the storage address of the data. In fig. 10, 300 and 400 are information storage units required by the address management module.

The operation principle of the variable width input-output device shown in fig. 10 is as follows:

the total number of the receiving ports is 10, each receiving port operates the buffer unit according to respective write time sequence, independently applies for respective address pointer queues, and stores the received MAC data into the corresponding memory address of the applied buffer unit. After each message reception is completed, the storage address information corresponding to the message is written into the information storage unit 100, and the transmission port information corresponding to the message is also written into the information storage unit 100.

The scheduling module schedules the information in the information storage unit 100 and stores the information in the information storage unit 200 according to the information of the transmission port.

And the sending module reads out the packet information in the 4 sending port information storage units 200, acquires the storage address of the packet in the cache unit, and reads the storage address of the cache unit to obtain the sending packet according to the corresponding reading operation time sequence of 0-3 four sending ports. The four transmit ports read out each time are exactly 128 bits wide of data each.

The sending module releases the storage address to the information storage unit 300 after completing the message sending.

The address management module completes the initialization of the address pointer and distributes the storage address to the information storage unit 400; in addition, if there is a memory address in the information storage unit 300 that has been released, it is also necessary to read and store the address into the information storage unit 400.

Fig. 11 shows a flowchart of a data bit width conversion method provided in the present application, where the method is applied to the variable bit width input/output device provided in the foregoing embodiment, and the method includes:

s301, determining a minimum input bit width according to the bit widths of the plurality of receiving ports and the bit width of the cache unit; splitting the cache unit into a plurality of first cache subunits with the same bit width, wherein the bit width of each first cache subunit is the minimum input bit width; determining the write operation timing sequence of each receiving port to the plurality of cache subunits;

s302, splitting the cache unit into a plurality of second cache subunits with the same bit width, wherein the bit width of the second cache subunits is the same as that of the sending port; determining the read operation timing sequence of each sending port to the plurality of second cache subunits;

s303, when each receiving port receives data, storing the received data into the target storage address of the cache unit applied by the receiving port according to the write operation time sequence corresponding to the receiving port;

s304, determining a target sending port of the data in the target storage address;

s305, sending the data in the target storage address according to the read operation time sequence corresponding to the target sending port.

The bit width changing input and output device and the data bit width conversion method applied to the bit width changing input and output device have the advantages that cache unit sharing is achieved to the greatest extent, and resource waste is avoided. The output and the input do not need a special bit width conversion module to carry out bit width conversion, thereby greatly saving resources.

The embodiment of the present application further provides a communication device, which includes the variable bandwidth input/output device in the above embodiment of the present application.

Finally, it should be noted that: the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present disclosure, and the present disclosure should be construed as being covered by the claims and the specification.

Claims

1. A data bit width conversion method is applied to a receiving module, the receiving module comprises a plurality of receiving ports and a cache unit, and bit widths of at least two receiving ports in the plurality of receiving ports are different, and the method comprises the following steps:

2. A data bit width conversion method is applied to a sending module, the sending module comprises a buffer unit and a plurality of sending ports, and bit widths of the plurality of sending ports are the same, and the method is characterized by comprising the following steps:

3. A data bit width conversion method is applied to a variable width input/output device, the variable width input/output device comprises a plurality of receiving ports, a buffer unit and a plurality of sending ports, bit widths of at least two receiving ports in the plurality of receiving ports are different, and bit widths of the plurality of sending ports are the same, and the method comprises the following steps:

determining a target sending port of the data in the target storage address;

4. A receiving module, comprising:

5. A transmit module, comprising:

6. A variable bandwidth input-output device, comprising:

the receiving module of claim 4;

the transmit module of claim 5;

wherein, the receiving module and the sending module share one buffer unit.

7. The variable width input-output device according to claim 6, further comprising:

and the scheduling module is used for scheduling the storage address and the sending port of the data between the receiving module and the sending module.

8. The variable width input-output device according to claim 6 or 7, further comprising:

and the address management module is used for recovering and initializing the storage address of the data.

9. A communication apparatus comprising the variable bandwidth input output device according to any one of claims 6 to 8.