CN113972308A - 电子基板以及电子装置 - Google Patents

电子基板以及电子装置 Download PDF

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Publication number
CN113972308A
CN113972308A CN202110189431.7A CN202110189431A CN113972308A CN 113972308 A CN113972308 A CN 113972308A CN 202110189431 A CN202110189431 A CN 202110189431A CN 113972308 A CN113972308 A CN 113972308A
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China
Prior art keywords
electronic
substrate
electronic device
layer
bonding pad
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Pending
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CN202110189431.7A
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English (en)
Inventor
粘觉元
宋朝钦
谢佳宏
刘美丞
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Innolux Corp
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Innolux Display Corp
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Priority to US17/363,018 priority Critical patent/US11830833B2/en
Priority to EP21185075.5A priority patent/EP3944347A1/en
Publication of CN113972308A publication Critical patent/CN113972308A/zh
Priority to US18/489,871 priority patent/US20240047393A1/en
Pending legal-status Critical Current

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Abstract

本揭露提供一种电子基板以及电子装置。电子基板包括基底、凸出部以及接合垫。凸出部以及接合垫设置在基底上。接合垫不与凸出部的边界重叠。

Description

电子基板以及电子装置
技术领域
本揭露涉及一种电子基板以及包括此电子基板的电子装置。
背景技术
电子基板和/或电子装置在出厂前，须通过一连串的信赖性(reliability)测试。其中，焊接有发光二极管(light emitting diode，LED)的基底在进行冷热冲击测试时，容易因发光二极管与基底(如玻璃)之间的热膨胀系数(coefficient of thermalexpansion，CTE)不匹配，而导致基底龟裂或发光二极管剥离，造成暗点的产生。
发明内容
本揭露提供一种电子基板以及电子装置，其有助于提升信赖性。
根据本揭露的一个实施例，电子基板包括基底、凸出部以及接合垫。凸出部以及接合垫设置在基底上。接合垫不与凸出部的边界重叠。
根据本揭露的另一个实施例，电子装置包括上述的电子基板以及电子元件。电子元件与接合垫电性连接。
为让本揭露的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是根据本揭露的第一实施例的电子装置的局部剖面示意图；
图2是图1中电子基板的局部上视示意图；
图3是根据本揭露的第二实施例的电子装置的局部剖面示意图；
图4是根据本揭露的第三实施例的电子装置的局部上视示意图；
图5是根据本揭露的第四实施例的电子装置的局部剖面示意图。
具体实施方式
通过参考以下的详细描述并同时结合附图可以理解本揭露。须注意的是，为了使读者能容易了解及附图的简洁，本揭露中的多张附图只绘出电子装置/显示装置的一部分，且附图中的特定元件并非依照实际比例绘图。此外，图中各元件的数量及尺寸仅作为示意，并非用来限制本揭露的范围。举例来说，为了清楚起见，各膜层、区域或结构的相对尺寸、厚度及位置可能缩小或放大。
本揭露通篇说明书与后附的权利要求中会使用某些词汇来指称特定元件。本领域技术人员应理解，电子设备制造商可能会以不同的名称来指称相同的元件。本文并不意在区分那些功能相同但名称不同的元件。在下文说明书与权利要求中，“具有”与“包括”等词为开放式词语，因此其应被解释为“包括但不限定为…”之意。
本文中所提到的方向用语，例如：“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向。因此，使用的方向用语是用来说明，而并非用来限制本揭露。应了解到，当元件或膜层被称为设置在另一个元件或膜层“上”或“连接”另一个元件或膜层时，所述元件或膜层可以直接在所述另一元件或膜层上或直接连接到所述另一元件或膜层，或者两者之间存在有***的元件或膜层(非直接情况)。相反地，当元件或膜层被称为“直接”在另一个元件或膜层“上”或“直接连接”另一个元件或膜层时，两者之间不存在有***的元件或膜层。
本文中所提到的术语“大约”、“等于”、“相等”、“相同”、“实质上”或“大致上”通常代表落在给定数值或范围的10％范围内，或代表落在给定数值或范围的5％、3％、2％、1％或0.5％范围内。此外，用语“给定范围为第一数值至第二数值”、“给定范围落在第一数值至第二数值的范围内”表示所述给定范围包含第一数值、第二数值以及它们之间的其它数值。
在本揭露一些实施例中，关于接合、连接的用语例如“连接”、“互连”等，除非特别定义，否则可指两个结构直接接触，或者亦可指两个结构并非直接接触，其中有其它结构设于此两个结构之间。关于接合、连接的用语亦可包括两个结构都可移动，或者两个结构都固定的情况。此外，用语“电性连接”、“耦接”包含任何直接及间接的电性连接手段。
在下述实施例中，相同或相似的元件将采用相同或相似的标号，且将省略其赘述。此外，不同实施例中的特征只要不违背发明精神或相冲突，均可任意混合搭配使用，且依本说明书或权利要求所作的简单的等效变化与修饰，皆仍属本揭露涵盖的范围内。另外，本说明书或权利要求中提及的“第一”、“第二”等用语仅用以命名不同的元件或区别不同实施例或范围，而并非用来限制元件数量上的上限或下限，也并非用以限定元件的制造顺序或设置顺序。
本揭露的电子装置可包括显示装置、天线装置、感测装置、发光装置、或拼接装置，但不以此为限。电子装置可包括可弯折或可挠式电子装置。电子装置可例如包括液晶(liquid crystal)层或发光二极管。发光二极管可例如包括有机发光二极管(organiclight emitting diode，OLED)、次毫米发光二极管(mini LED)、微发光二极管(micro LED)或量子点发光二极管(quantum dot LED，可包括QLED、QDLED)、荧光(fluorescence)、磷光(phosphor)或其他适合的材料、或上述组合，但不以此为限。下文将以显示装置做为电子装置以说明本揭露内容，但本揭露不以此为限。
本揭露的显示装置可以是任何种类的显示装置，如自发光显示装置或非自发光显示装置。自发光显示装置可包括发光二极管、光转换层或其他适合的材料、或上述组合，但不以此为限。发光二极管可例如包括有机发光二极管(organic light emitting diode，OLED)、次毫米发光二极管(mini LED)、微发光二极管(micro LED)或量子点发光二极管(quantum dot LED，可包括QLED、QDLED)，但不以此为限。光转换层可包括波长转换材料和/或光过滤材料，光转换层可例如包括荧光(fluorescence)、磷光(phosphor)、量子点(Quantum Dot，QD)、其他合适的材料或上述的组合，但不以此为限。非自发光显示装置可包括液晶显示装置，但不以此为限。
图1是根据本揭露的第一实施例的电子装置的局部剖面示意图。图2是图1中电子基板的局部上视示意图。为简化图示，图2仅以两点链线、虚线以及一点链线分别标示出图1中凸出部、第一导电层以及接垫定义层的边缘，并省略示出出其他元件及膜层。图2中的剖线A-A’的剖面可参照图1。
请参照图1及图2，电子装置1可包括基板10以及电子元件12。例如，基板10可为电子基板。电子基板(基板10)可包括基底100、凸出部101以及接合垫102，但不以此为限。
基底100可用于承载凸出部101以及接合垫102。举例来说，基底100的材质可包括玻璃，但不以此为限。在一些实施例中，基底100可为刚性基底或柔性基底。在一些实施例中，基底100的材质可包括玻璃、塑胶、聚碳酸酯(polycarbonate，PC)、聚酰亚胺(polyimide，PI)、聚对苯二甲酸乙二酯(polyethylene terephthalate，PET)、石英、蓝宝石(sapphire)、陶瓷、或上述的组合，即基底100可为单层板或复合板，但不以此为限。
凸出部101设置在基底100上。举例来说，凸出部101可由平坦层形成。在一些实施例中，平坦层可为有机绝缘层，但不以此为限。在一些实施例中，凸出部101可由单层有机绝缘层形成。在另一些实施例中，凸出部101可由多层有机绝缘层堆叠而成。在一些实施例中，凸出部101可为有机绝缘层、无机绝缘层、或其组合。
接合垫102设置在基底100上，且可用以与电子元件12接合，但不以此为限。举例来说，电子元件12可为发光二极管。发光二极管可例如包括次毫米发光二极管(mini LED)、微发光二极管(micro LED)或量子点发光二极管(quantum dot LED，可包括QLED、QDLED)，但不以此为限。此外，电子元件12可包括接垫120。在一些实施例中，电子装置1还可包括导电接着层13(例如锡层)。接垫120可通过导电接着层13而焊接至接合垫102，使得电子元件12与接合垫102电性连接，但不以此为限。在一些实施例中，接合垫102可包括双层堆叠结构。举例来说，接合垫102可包括依序堆叠在基底100上的第一导电层102-1以及第二导电层102-2。第一导电层102-1和第二导电层可为金属层或金属合金层。具体而言，第一导电层102-1可包括铜层，第二导电层102-2可包括镍层，但不以此为限。相较于第一导电层102-1，第二导电层102-2可具有与导电接着层13更高的接着力，以提升电子元件12对于接合垫102的接着力，但不以此为限。第一导电层102-1和第二导电层102-2可具有相同或不同的厚度。在其他实施例中，在适当材质选择下，接合垫102也可由单层导电层构成。
在一些实施例中，接合垫102例如是在凸出部101之后设置在基底100上。举例来说，电子基板10还可包括绝缘层(如第四绝缘层107)。绝缘层(如第四绝缘层107)设置在凸出部101上，且接合垫102可设置在绝缘层(如第四绝缘层107)上。
由于电子元件12与基底100之间的热膨胀系数不匹配，在电子装置1进行冷热冲击测试时，电子元件12与基底100之间可能会因热涨冷缩而产生应力。在焊接点不平的情况下，例如接合垫102的表面不平(例如铜层的表面不平)的情况下，电子元件12与基底100之间容易产生较大的应力，导致基底100龟裂或电子元件12剥离。
根据观察，电子元件12与基底100之间产生最大应力的位置可能发生在凸出部101的边界B(即凸出部101开始爬升的边界)，即基底100容易在凸出部101的边界B破裂，其中裂纹始于凸出部101的边界B并终止于基底100中。
在本揭露的实施例中，通过接合垫102不与凸出部101的边界B重叠，如此，接合垫102不与可能产生最大应力的位置(即，凸出部101的边界B)重叠，以降低电子元件12与基底100之间所产生的应力或提升焊接点的平整度(例如接合垫102的表面的平整度或设置铜层的表面的平整度)，藉此降低基底100龟裂或电子元件12剥离的机率。依据一些实施例，接合垫102与凸出部101的边界B有间隙G，例如接合垫102与边界B在电子装置1的厚度方向DT上不重叠。在一些实施例中，考量到目前制程精度(如曝光精度)以及电子装置1的小尺寸需求，接合垫102与边界B之间的间隙G可落在5μm至100μm的范围内，即5μm≦G≦100μm，但不以此为限。在其他实施例中，接合垫102与边界B之间的间隙G可为0，即，接合垫102与边界B可切齐或大致上切齐。依据一些实施例，间隙G可落在0μm至300μm的范围内。依据一些实施例，间隙G可落在0μm至200μm的范围内。依据一些实施例，间隙G可为大于0。依据一些实施例，间隙G可落在5μm至200μm的范围内。依据一些实施例，间隙G可落在5μm至100μm的范围内。依据一些实施例，间隙G可落在5μm至50μm的范围内。依据一些实施例，间隙G可落在5μm至10μm的范围内。依据一些实施例，上述间隙G可为接合垫102的第一导电层102-1与凸出部101之间的间隙。依据一些实施例，上述间隙G可为第二导电层102-2与凸出部101之间的间隙。
反观在接合垫102与凸出部101的边界B重叠的情况下(图未显示)，具体而言，有部分的接合垫102在厚度方向DT上与部分的凸出部101重叠。如图1所示，凸出部101在边缘处可具有坡度。例如，接合垫102设置在凸出部101的边界B上且顺着凸出部101的坡度而形成。如此，因为顺着凸出部101的坡度而形成，接合垫102的上述重叠部分有不平整的表面，使得电子元件12与基底100之间容易产生较大的应力，导致基底100龟裂或电子元件12剥离。
基底龟裂率指的是电子元件因基底龟裂而剥离或无法正常运作的颗数与同一块基底上总电子元件数的比率。电子元件是否剥离或是否可正常运作(即，电子元件是否可被点亮)可由光学显微镜(optical microscope，OM)观察。以基底为玻璃为例，根据实验结果可知，相比于接合垫与凸出部的边界重叠的设计，在一些实施例中，接合垫不与凸出部的边界重叠的设计可将基底龟裂率从11.5％降至2％。此外，根据模拟结果可知，相比于接合垫与凸出部的边界重叠的设计，在一些实施例中，接合垫不与凸出部的边界重叠的设计可将最大应力从2905MPa降至752MPa。因此，在一些实施例中，通过接合垫102不与凸出部101的边界B重叠的设计有助于提升电子装置1的信赖性。
根据不同的需求，如图1所示，电子基板10还可包括其他元件或膜层。举例来说，电子基板10还可包括驱动元件103、第一绝缘层104、第二绝缘层105、第三绝缘层106、第四绝缘层107以及接垫定义层108。
请参照图1，驱动元件103可设置在基底100上且例如包括栅极(未示出)、通道层CH、源极(未示出)以及漏极DE。驱动元件103例如可为薄膜晶体管，可为顶栅极薄膜晶体管或为底栅极薄膜晶体管，但不以此为限。以驱动元件103为底栅极薄膜晶体管为例，栅极设置在基底100上。栅极的材质可包括金属、合金或其组合，但不以此为限。第一绝缘层104设置在栅极以及基底100上。第一绝缘层104可包括无机绝缘层，例如氧化硅(SiOx)或氮化硅(SiNx)，但不以此为限。通道层CH设置在第一绝缘层104上且位于栅极的上方。通道层CH的材质可包括非晶硅、多晶硅或金属氧化物，但不以此为限。第二绝缘层105设置在通道层CH以及第一绝缘层104上。第二绝缘层105可包括无机绝缘层，例如氧化硅(SiOx)或氮化硅(SiNx)，但不以此为限。第二绝缘层105具有开口A1。开口A1暴露出局部的通道层CH。源极以及漏极DE设置在第二绝缘层105上且通过不同的开口A1而与通道层CH接触。源极以及漏极DE的材质可包括金属、合金或其组合，但不以此为限。第三绝缘层106设置在第二绝缘层105、源极以及漏极DE上。第三绝缘层106可包括无机绝缘层，例如氧化硅(SiOx)或氮化硅(SiNx)，但不以此为限。第三绝缘层106具有开口A2。开口A2暴露出局部的漏极DE。凸出部101设置在第三绝缘层106上。第四绝缘层107设置在凸出部101以及第三绝缘层106上。第四绝缘层107可包括无机绝缘层，例如氧化硅(SiOx)或氮化硅(SiNx)，但不以此为限。第四绝缘层107具有开口A3。开口A3与开口A2可连接且暴露出局部的漏极DE。
继续参照图1，接合垫102可包括第一导电层102-1以及第二导电层102-2。第一导电层102-1可设置在第四绝缘层107上，其中至少一个接合垫102的第一导电层102-1可通过开口A2以及开口A3而与漏极DE接触。接垫定义层108设置在第四绝缘层107上且覆盖各接合垫102的第一导电层102-1的部分E102-1。第二导电层102-2可设置在第一导电层102-1上且可覆盖接垫定义层108的部分E108。依据一些实施例，如图1所示，以电子元件12的同一侧而言，相较于第二导电层102-2的边缘E2，第一导电层102-1的边缘E1可较为靠近凸出部101的边界B。如此，接垫定义层108的一部分可覆盖第一导电层102-1的一部分，例如部分E102-1。依据一些实施例(图未显示)，以电子元件12的同一侧而言，相较于第二导电层102-2的边缘E2，第一导电层102-1的边缘E1可较为远离凸出部101的边界B。
应理解，虽然图1仅示出出一个电子元件12，但电子基板10上可依需求而设置任意数量的电子元件12。此外，电子元件12的种类可依需求而改变，而不限于发光二极管。在电子元件12为发光二极管的架构下，电子装置1可例如为发光装置、显示装置(例如非自发光显示装置)或拼接式显示装置，但不以此为限。
图3是根据本揭露的第二实施例的电子装置的局部剖面示意图。请参照图3，电子装置1A与图1中电子装置1的主要差异说明如下。电子装置1A包括电子基板10A、电子元件12、导电接着层13以及电路板14。电子基板10A例如可为集成有主动元件(例如薄膜晶体管)以及被动元件(例如电容或电阻)的晶片。举例来说，电子基板10A可包括驱动电路，但不以此为限。图3示意性示出出电子基板10A具有与图1中电子基板10类似的结构，差异在于电子基板10A进一步包括设置在基底100与第三绝缘层106之间的电路层109。为清楚表示电路层109，图3省略示出出电子基板10A的部分膜层及元件，被省略的部分膜层及元件请参照图1。
电子基板10A与电子元件12接合至电路板14的同一侧上，且电子基板10A与电子元件12通过电路板14而电性连接。举例来说，电路板14可包括线路基板140、接合垫141以及保护层142。
线路基板140可包括交替堆叠的多个金属层(未示出)以及多个绝缘层(未示出)。接合垫141设置在线路基板140上，且可用以与电子元件12以及电子基板10A接合，但不以此为限。举例来说，电子元件12的接垫120以及电子基板10A的接合垫102可通过导电接着层13(例如锡层)而焊接至接合垫141，使得电子元件12与接合垫102电性连接，但不以此为限。在一些实施例中，接合垫141可包括双层堆叠结构。举例来说，接合垫141可包括依序堆叠在线路基板140上的第一导电层141-1(例如铜层)以及第二导电层141-2(例如镍层)，其中相较于第一导电层141-1，第二导电层141-2可具有与导电接着层13更高的接着力，以提升电子元件12以及电子基板10A对于接合垫141的接着力，但不以此为限。在其他实施例中，在适当材质选择下，接合垫141也可由单层导电层构成。
保护层142设置在线路基板140以及局部的第一导电层141-1上。详细而言，保护层142具有多个开口A4。多个开口A4分别暴露出第一导电层141-1待设置第二导电层141-2的区域，以利第二导电层141-2设置在第一导电层141-1上。保护层142的材质可包括阻焊剂(solder resist)或光致抗蚀剂(photoresist)，但不以此为限。
在本实施例中，也可通过接合垫102不与凸出部101的边界重叠的设计来提升电子装置1A的信赖性，具体说明请参照前述，于此不再重述。
应理解，虽然图3仅示出出一个电子元件12以及一个电子基板10A，但电路板14上可依需求而设置任意数量的电子元件12以及任意数量的电子基板10A。此外，电子元件12的种类可依需求而改变，而不限于发光二极管。另外，电子基板10A的具体结构也可依需求而改变，而不限于图3所示出者。在电子元件12为发光二极管的架构下，电子装置1A可例如为显示装置(例如非自发光显示装置)或拼接式显示装置，但不以此为限。
图4是根据本揭露的第三实施例的电子装置的局部上视示意图。请参照图4，电子装置1B例如为拼接式显示装置。举例来说，电子装置1B可由四个图1所示的电子装置1拼接而成，但电子装置1B中电子装置1的数量可依需求改变。在图4中，每一个电子装置1例如包括一个电子基板10(参照图1)，四个电子装置1包括四个电子基板10，且四个电子基板10拼接在一起而形成拼接式显示装置。在其他实施例中，在图3中电子基板10A不至于影响显示品质的情况下，例如当电子基板10A的尺寸远小于电子装置1B的尺寸，或电子基板10A的尺寸甚小的情况下，电子装置1B也可由多个图3所示的电子装置1A拼接而成。
图5是根据本揭露的第四实施例的电子装置的局部剖面示意图。请参照图5，电子装置1C例如为非自发光显示装置。举例来说，电子装置1C可包括图1所示的电子装置1以及显示面板DP。在电子装置1C中，电子装置1例如作为背光模块。电子装置1中的电子元件12例如为发光二极管，且显示面板DP设置在来自发光二极管的光束L的传递路径上。在其他实施例中，电子装置1C中的电子装置1也可替换成图3的电子装置1A。
综上所述，在本揭露的实施例中，通过接合垫不与凸出部的边界重叠的设计，以降低电子元件与基底之间所产生的应力或提升焊接点的平整度，藉此降低基底龟裂或电子元件剥离的机率，从而有助于提升电子装置的信赖性。
以上各实施例仅用以说明本揭露的技术方案，而非对其限制；尽管参照前述各实施例对本揭露进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本揭露各实施例技术方案的范围。
虽然本揭露的实施例及其优点已揭示如上，但应该了解的是，任何所属技术领域中技术人员，在不脱离本揭露的精神和范围内，当可作更改、替代与润饰，且各实施例间的特征可任意互相混合替换而成其他新实施例。此外，本揭露的保护范围并未局限于说明书内所述特定实施例中的制程、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中技术人员可从本揭露揭示内容中理解现行或未来所发展出的制程、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大抵相同功能或获得大抵相同结果皆可根据本揭露使用。因此，本揭露的保护范围包括上述制程、机器、制造、物质组成、装置、方法及步骤。另外，每一权利要求构成个别的实施例，且本揭露的保护范围也包括各个权利要求及实施例的组合。本揭露的保护范围当视随附的权利要求所界定的为准。

Claims (10)

1.一种电子基板，其特征在于，包括：
基底；
凸出部，设置在所述基底上；以及
接合垫，设置在所述基底上；
其中所述接合垫不与所述凸出部的边界重叠。
2.根据权利要求1所述的电子基板，其特征在于，所述接合垫与所述边界之间的间隙落在5μm至100μm的范围内。
3.根据权利要求1所述的电子基板，其特征在于，所述凸出部由平坦层形成。
4.根据权利要求3所述的电子基板，其特征在于，所述平坦层为有机绝缘层。
5.根据权利要求3所述的电子基板，其特征在于，还包括：
绝缘层设置在所述凸出部上，
其中所述接合垫设置在所述绝缘层上。
6.一种电子装置，其特征在于，包括：
如权利要求1所述的电子基板；以及
电子元件，与所述电子基板的所述接合垫电性连接。
7.根据权利要求6所述的电子装置，其特征在于，所述电子装置为发光装置。
8.根据权利要求6所述的电子装置，其特征在于，所述电子元件为发光二极管。
9.根据权利要求8所述的电子装置，其特征在于，还包括：
显示面板，设置在来自所述发光二极管的光束的传递路径上。
10.根据权利要求6所述的电子装置，其特征在于，所述电子装置包括多个所述电子基板，且多个所述电子基板拼接在一起。
CN202110189431.7A 2020-07-24 2021-02-19 电子基板以及电子装置 Pending CN113972308A (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020028533A1 (en) * 2000-06-03 2002-03-07 Wei-Sen Tang Flip-chip package structure and method of fabricating the same
US20070235217A1 (en) * 2006-03-29 2007-10-11 Workman Derek B Devices with microjetted polymer standoffs
US20100271792A1 (en) * 2009-04-27 2010-10-28 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
CN103066184A (zh) * 2011-10-24 2013-04-24 新光电气工业株式会社 配线基板、发光装置、以及配线基板的制造方法
DE102013201952A1 (de) * 2013-02-06 2014-08-21 Osram Gmbh Halbleiter-Leuchtmodul mit lichtdurchlässiger Vergussmasse
CN109216285A (zh) * 2017-07-05 2019-01-15 英属开曼群岛商錼创科技股份有限公司 显示面板
CN113628976A (zh) * 2020-05-07 2021-11-09 台湾积体电路制造股份有限公司 半导体装置的形成方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020028533A1 (en) * 2000-06-03 2002-03-07 Wei-Sen Tang Flip-chip package structure and method of fabricating the same
US20070235217A1 (en) * 2006-03-29 2007-10-11 Workman Derek B Devices with microjetted polymer standoffs
US20100271792A1 (en) * 2009-04-27 2010-10-28 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
CN103066184A (zh) * 2011-10-24 2013-04-24 新光电气工业株式会社 配线基板、发光装置、以及配线基板的制造方法
DE102013201952A1 (de) * 2013-02-06 2014-08-21 Osram Gmbh Halbleiter-Leuchtmodul mit lichtdurchlässiger Vergussmasse
CN109216285A (zh) * 2017-07-05 2019-01-15 英属开曼群岛商錼创科技股份有限公司 显示面板
CN113628976A (zh) * 2020-05-07 2021-11-09 台湾积体电路制造股份有限公司 半导体装置的形成方法

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