CN113628976A - 半导体装置的形成方法 - Google Patents
半导体装置的形成方法 Download PDFInfo
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- CN113628976A CN113628976A CN202110378733.9A CN202110378733A CN113628976A CN 113628976 A CN113628976 A CN 113628976A CN 202110378733 A CN202110378733 A CN 202110378733A CN 113628976 A CN113628976 A CN 113628976A
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- conductive
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- conductive pad
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Abstract
一种半导体装置的形成方法,包括:提供基板;形成掩膜层于基板的表面之上,掩膜层具有开口位于表面的部分之上;沉积导电层于表面的部分及掩膜层之上;移除掩膜层及掩膜层之上的导电层,在移除掩膜层及掩膜层之上的导电层之后,在表面的部分之上余留的导电层形成导电垫,且导电垫的宽度朝着基板增加;以及通过焊料层接合装置至导电垫,导电垫埋藏于焊料层中。
Description
技术领域
本发明实施例涉及一种半导体装置的制造方法,且特别涉及一种封装结构的形成方法。
背景技术
半导体集成电路(integrated circuit,IC)工业经历了快速成长。集成电路材料及设计的技术进步产生了几个世代的集成电路。每一世代具有相较于上一代更小及更复杂的电路。然而,这些进步增加了处理和制造集成电路的复杂度。
在集成电路发展的过程中,当几何尺寸(亦即使用制造制程可创造的最小的元件(或线)减少,增加了功能密度(亦即每一芯片面积的内连装置数目)。这样按比例缩小的制程通常通过提高生产效率及降低相关成本来提供好处。
然而,由于部件尺寸持续减少,制造制程变得更难以进行。因此,形成越来越小的可靠的半导体元件为一挑战。接合半导体元件至其他元件亦为挑战。
发明内容
本发明实施例包括一种半导体装置的形成方法,包括:提供基板;形成掩膜层于基板的表面之上,其中掩膜层具有开口位于表面的部分之上;沉积导电层于表面的部分及掩膜层之上;移除掩膜层及掩膜层之上的导电层,其中在移除掩膜层及掩膜层之上的导电层之后,在表面的部分之上余留的导电层形成导电垫,且导电垫的宽度朝着基板增加;以及通过焊料层接合装置至导电垫,导电垫埋藏于焊料层中。
附图说明
以下将配合所附图式详述本发明实施例。应注意的是,各种特征部件并未按照比例绘制且仅用以说明例示。事实上,元件的尺寸可能经放大或缩小,以清楚地表现出本发明实施例的技术特征。
图1A-图1G是根据一些实施例绘示出形成半导体装置制程各阶段的剖面图。
图1A-1是根据一些实施例绘示出图1A的基板、绝缘层、及导电线的上视图。
图1A-2是根据一些实施例绘示出图1A的基板、绝缘层、及导电线的上视图。
图1B-1是根据一些实施例绘示出图1B的上视图。
图1E-1是根据一些实施例绘示出图1E的上视图。
图1E-2是根据一些实施例绘示出图1E的上视图。
图1F-1是根据一些实施例绘示出图1F的底视图。
图1F-2是根据一些实施例绘示出图1F的底视图。
图1G-1是根据一些实施例绘示出图1G的上视图。
图1G-2是根据一些实施例绘示出图1G的上视图。
图2是根据一些实施例绘示出半导体装置的剖面图。
图3A-图3F是根据一些实施例绘示出形成半导体装置制程各阶段的剖面图。
图4A-图4F是根据一些实施例绘示出形成半导体装置制程各阶段的剖面图。
图5是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图6是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图7是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图8是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图9是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图10是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图11是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图12是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图13是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
图14是根据一些实施例绘示出基板、绝缘层、及导电线突出部分的变化的上视图。
其中,附图标记说明如下:
100,200,300,400:半导体装置
110:基板
112:表面
112a:部分
114:突出部分
114a:柱状结构
116:凹槽
116a:底表面
117:基座
118:台座
118a:顶表面
118b:侧壁
118p:周围部分
120:导电线
124:侧壁
126:侧壁
128:侧壁
129a,129b,129c,129d:角落
130:掩膜层
132:开口
132a:内壁
132u:上部
132w:下部
134:凹槽
136:顶表面
140:导电层
141a,141b:顶表面
142:导电垫
142a:顶表面
142b:侧壁
150:装置
152:底表面
154:突出部分
154a:柱状结构
160:导电垫
170:焊料层
310:导电结构
A:绝缘层
B:边界
D1,D2:距离
E1:端点部分
W1,W2:宽度
G:边缘部分
T1,T2,T3,T3’,T4,T5,T6,T7:厚度
θ1:角度
I-I’:剖面线
R1,R2:区域
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本案的不同特征。以下的公开内容叙述各个构件及其排列方式的特定范例,以简化说明。当然,这些特定的范例并非用以限定。例如,若是本发明实施例叙述了一第一特征部件形成于一第二特征部件之上或上方,即表示其可能包含上述第一特征部件与上述第二特征部件是直接接触的实施例,亦可能包含了有附加特征部件形成于上述第一特征部件与上述第二特征部件之间,而使上述第一特征部件与第二特征部件可能未直接接触的实施例。此外,本发明实施例可在各范例重复使用标号及/或文字。这样的重复是为了简洁及清楚起见,而并非表示所讨论的各实施例及/或形态之间的关系。
此外,其中可能用到与空间相对用词,例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词,这些空间相对用词是为了便于描述图示中一个(些)元件或特征与另一个(些)元件或特征之间的关系,这些空间相对用词包括使用中或操作中的装置的不同方位,以及图式中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位),则其中所使用的空间相对形容词也将依转向后的方位来解释。应理解的是,可在这些实施例所述的阶段之前、之中、及/或之后提供额外的操作,且此方法的其他实施例可取代或消除一些操作。
描述了一些本发明实施例。可在这些实施例所述的阶段之前、之中、及/或之后提供额外的操作。不同的实施例中可取代或消除所述的一些阶段。额外的部件可加入半导体装置结构。不同的实施例中可取代或消除下述的一些部件。即使一些实施例以特定顺序进行操作,这些操作亦可以另一合逻辑的顺序进行。
图1A-图1G是根据一些实施例绘示出形成半导体装置制程各阶段的剖面图。根据一些实施例,图1A-1为图1A的基板、绝缘层、及导电线的上视图。根据一些实施例,图1A为沿图1A-1中剖面线I-I’所绘示半导体装置的剖面图。根据一些实施例,如图1A及图1A-1所绘示,提供了基板110。根据一些实施例,基板110具有表面112及突出部分114。根据一些实施例,突出部分114从表面112突出。根据一些实施例,突出部分114邻近表面112的部分112a。根据一些实施例,突出部分114包围表面112的部分112a。
根据一些实施例,如图1A及图1A-1所绘示,突出部分114包括彼此相隔的柱状结构114a。根据一些实施例,柱状结构114a彼此以相同距离D1相隔。
基板110包括例如半导体基板。在一些实施例中,基板110以元素半导体材料包括单晶、多晶、或非晶结构的硅或锗。在一些其他实施例中,在一些其他实施例中,基板110以化合物半导体,例如碳化硅(silicon carbide)、砷化镓(gallium arsenide)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)、合金半导体例如SiGe、或GaAsP、或上述的组合制成。基板110亦可包括多层半导体、绝缘体上覆半导体(semiconductor on insulator,SOI)(例如绝缘体上覆硅或绝缘体上覆锗)、或上述的组合。
在一些实施例中,基板110包括各种装置零件。在一些实施例中,各种装置零件形成于基板110之中及/或之上。为了简洁明了的目的,未绘示各种装置零件于图中。各种装置零件的范例包括主动装置、被动装置、其他合适的零件、或上述的组合。主动零件可包括晶体管或二极管(未绘示)。被动零件包括电阻、电容、或其他合适的被动零件。
例如,晶体管可为金属氧化物半导体场效晶体管(metal oxide semiconductorfield effect transistors,MOSFET)、互补式金属氧化物半导体(complementary metaloxide semiconductor,CMOS)晶体管、双极接面晶体管(bipolar junction transistors,BJT)、高压晶体管、高频晶体管、p通道及/或n通道场效晶体管(PFETs/NFETs)等等。进行各种制程例如产线前段(front-end-of-line,FEOL)半导体制造制程以形成各种装置零件。产线前段半导体制造制程可包括沉积、蚀刻、布植、微影、退火、平坦化、一或多道其他适用的制程、或上述的组合。
在一些实施例中,形成隔离部件(未绘示)于基板110之中。隔离部件用以定义主动区及电性隔离主动区中基板110之中及/或之上的各装置零件。在一些实施例中,隔离部件包括浅沟槽隔离(shallow trench isolation,STI)部件、硅局部氧化(local oxidationof silicon,LOCOS)部件、其他合适的隔离部件、或上述的组合。
根据一些实施例,如图1A及图1A-1所绘示,绝缘层A形成于基板110之上。根据一些实施例,绝缘层A以氧化物(例如氧化硅(silicon oxide))、氟掺杂硅酸盐玻璃(fluorine-doped silicate glass,FSG)、低介电常数介电材料、聚酰亚胺(polyimide)、氮化硅(silicon nitride)、未掺杂硅酸盐玻璃(un-doped silicate glass,USG)、及/或其他合适的绝缘材料制成。绝缘层A可以原子层沉积(atomic layer deposition,ALD)制程、化学气相沉积(chemical vapor deposition,CVD)、物理气相沉积(physical vapor deposition,PVD)制程、热氧化制程、或其他合适的制程形成。
根据一些实施例,如图1A及图1A-1所绘示,形成导电线120于绝缘层A(或基板110)之上。根据一些实施例,突出部分114包围导电线120的端点部分E1。根据一些实施例,导电线120以导电材料例如金属(例如钨(tungsten)、铜(copper)、或铝(aluminum))、上述的合金制成。根据一些实施例,使用电镀镀覆制程及蚀刻制程形成导电线120。
突出部分114可具有不同变化,例如图1A-2的突出部分114。根据一些实施例,图1A-2为图1A的基板、绝缘层、及导电线的上视图。根据一些实施例,图1A为沿图1A-2中剖面线I-I’所绘示的半导体装置的剖面图。根据一些实施例,如图1A及图1A-2中所绘示,突出部分114为连续条状结构。根据一些实施例,突出部分114连续包围导电线120的端点部分E1。
根据一些实施例,图1B-1为图1B的半导体装置的上视图。根据一些实施例,图1B为沿图1B-1中剖面线I-I’所绘示的半导体装置的剖面图。
根据一些实施例,如图1B及图1B-1中所绘示,掩膜层130形成于绝缘层A(或基板110的表面112)以及一部分的导电线120之上。根据一些实施例,掩膜层130覆盖整个突出部分114。根据一些实施例,掩膜层130具有开口132于表面112的部分112a之上。
根据一些实施例,开口132露出导电线120的端点部分E1以及于部分112a之上的绝缘层A。根据一些实施例,开口132具有内壁132a。在一些实施例中,开口132的宽度W1朝基板110增加。根据一些实施例,开口132的上部132u的宽度W1朝基板110持续增加。
根据一些实施例,邻近基板110的掩膜层130具有凹槽134。根据一些实施例,凹槽134从开口132的内壁132a凹蚀。根据一些实施例,凹槽134连续包围开口132露出的导电线120的端点部分E1。
根据一些实施例,开口132的下部132w的宽度W1朝基板110持续增加。根据一些实施例,掩膜层130具有开口132的内壁132a与凹槽134之间的边缘部分G。根据一些实施例,边缘部分G包围开口132所露出的导电线120的部分。
根据一些实施例,掩膜层130为光阻层。根据一些实施例,掩膜层130以负光阻材料制成。负光阻材料能聚合,且在暴露于辐射例如紫外线辐射时变得无法溶解。
形成掩膜层130包括形成负光阻材料层于绝缘层A之上;选择性地暴露负光阻材料层于辐射中,导致聚合作用在基板110的某些区域之上发生,这些区域为在后续制程中预计保护的区域,且以溶剂移除负光阻材料层的未曝光部分,其对于负光阻材料层的聚合部分的影响最小。
由于掩膜层130由负光阻材料制成,其能聚合,且在暴露于辐射时变得无法溶解,在进行微影制程之后,远离基板110的掩膜层130(亦即靠近辐射的掩膜层130)比靠近基板110的掩膜层130(亦即远离辐射的掩膜层130)宽。
在一些实施例中,负光阻材料添加了添加剂以增加掩膜层130的上半部的光吸收系数。因此,根据一些实施例,掩膜层130的上半部的光吸收系数大于掩膜层130的下半部的光吸收系数。因此,根据一些实施例,添加剂有助于形成凹槽134。可使用适合的添加剂添加于负光阻材料中,合适的曝光能量的曝光制程、及合适的显影制程形成凹槽134。
根据一些实施例,如图1C所绘示,形成导电层140于表面112、导电线120、及掩膜层130之上。根据一些实施例,导电层140覆盖掩膜层130的顶表面136、开口132的内壁132a、及凹槽134的内壁134a。
根据一些实施例,导电层140为单层结构。在一些其他实施例中,导电层140为多层结构。根据一些实施例,导电层140以金属(例如金、锡、铜、或银)、或上述之合金制成。
根据一些实施例,使用沉积制程例如非等向性沉积制程形成导电层140。根据一些实施例,导电层140在大抵垂直表面(例如开口132的内壁132a)上的沉积速率小于导电层140在大抵水平表面(例如导电线120及掩膜层130的顶表面122及136)上的沉积速率。根据一些实施例,由于凹槽134从内壁132a内凹,凹槽134中导电层140的沉积速率小于内壁132a上导电层140的沉积速率。
根据一些实施例,凹槽134的内壁134a上的导电层140比开口132的内壁132a上的导电层140薄。根据一些实施例,内壁132a上的导电层140比导电线120(或表面112的部分112a)上的导电层140薄。根据一些实施例,导电线120(或表面112的部分112a)上的导电层140比掩膜层130的顶表面136上的导电层140薄。
根据一些实施例,沉积制程包括物理气相沉积制程。根据一些实施例,由于使用物理沉积制程形成导电线120上的导电层140,且被掩膜层130包围,导电线120上的导电层140具有弯曲的顶表面141a。
根据一些实施例,物理气相沉积在掩膜层130中产生热,掩膜层130变形,且掩膜层130的顶表面136变成弯曲的顶表面。根据一些实施例,在弯曲的顶表面136上的导电层140亦具有弯曲的顶表面141b。
根据一些实施例,如图1D中所绘示,移除了内壁132a、凹槽134、及绝缘层A上的导电层140。根据一些实施例,在移除制程之后,余留在导电线120上的导电层140形成了导电垫142。
根据一些实施例,导电垫142具有弯曲顶表面142a。在一些实施例中,导电垫142的宽度W2朝基板110增加。根据一些实施例,宽度W2朝基板110持续增加。根据一些实施例,移除制程包括蚀刻制程,例如湿蚀刻制程。
根据一些实施例,图1E-1为图1E的半导体装置的上视图。根据一些实施例,图1E为绘示出图1E-1中半导体装置沿剖面线I-I’的剖面图。如图1E及图1E-1中所绘示,移除了掩膜层130及掩膜层130上的导电层140。根据一些实施例,如图1E-1中所绘示,柱状结构114a包围导电垫142。
根据一些实施例,由于凹槽134的内壁134a上的导电层140比开口132的内壁132a上的导电层140薄(如图1C中所绘示),在去除内壁132a上的导电层140时倾向完全移除内壁134a上的导电层140(如图1D中所绘示),其有助于完全移除掩膜层130。因此,根据一些实施例,形成凹槽134改善了掩膜层130的移除制程的良率。
根据一些实施例,由于以剥离制程(亦即图1B-图1E的步骤)形成导电垫142,形成导电垫142并未受包围导电垫142的突出部分114影响。相反地,根据一些实施例,若以电镀制程形成导电垫142,电镀制程时用以传导电流的种晶层在突出部分114上的阶梯覆盖均匀度较差,导致种晶层的高电阻及电镀失效。
此外,根据一些实施例,若形成导电垫142包括:形成停止层于基板110之上;沉积导电层于停止层之上;对导电层进行微影制程及蚀刻制程;以及蚀刻余留的导电层所露出的停止层,停止层的蚀刻制程可能损害突出部分114。
根据一些实施例,如图1E中所绘示,突出部分114的厚度T1大于导电线120的厚度T2。根据一些实施例,突出部分114的厚度T1大于导电垫142的最大厚度T3。根据一些实施例,最大厚度T3在约2500nm至约5500nm的范围。根据一些实施例,导电垫142的侧壁142b及导电线120的顶表面122之间的角度θ1在约45°至约75°的范围。
根据一些实施例,侧壁142b为斜面。根据一些实施例,侧壁142b及弯曲顶表面142a之间为边界B。根据一些实施例,边界B之下的导电垫142具有厚度T3’。在一些实施例中,厚度T3’与最大厚度T3的比例在约0.1至约0.7的范围。
根据一些其他实施例,图1E-2为图1E的半导体装置的上视图。根据一些实施例,图1E为图1E-2中所绘示的半导体装置沿剖面线I-I’的剖面图。在一些其他实施例中,如图1E及图1E-2中所绘示,突出部分114连续围绕导电垫142。
根据一些实施例,如图1F中所绘示,提供了装置150。装置150包括芯片、封装、主动装置、被动装置、发光装置、或其他合适的装置。根据一些实施例,发光装置包括发射激光光束的激光二极管(未绘示)。根据一些实施例,装置150具有底表面152及突出部分154。根据一些实施例,突出部分154突出于底表面152。
根据一些实施例,图1F-1为图1F的装置150的底视图。根据一些实施例,图1F为图1F-1中所绘示的装置150沿剖面线I-I’的剖面图。在一些实施例中,如图1F及图1F-1中所绘示,突出部分154包括柱状结构154a。
根据一些实施例,柱状结构154a彼此相隔。根据一些实施例,柱状结构154a彼此以相同距离D2相隔。根据一些实施例,图1A-1的柱状结构114a之间的距离D1与距离D2大抵相等。
根据一些实施例,本发明实施例中用语“大抵相等”指的是“在10%之内”。例如,根据一些实施例,用语“大抵相等”指的是距离D1及D2之间的差异在距离D1及D2的平均的10%之内。差异可能来自于制造制程。
根据一些实施例,如图1F中所绘示,形成导电垫160于装置150的底表面152上。根据一些实施例,导电垫160电性连接至装置150的激光二极管。根据一些实施例,导电垫160以导电材料例如金属(例如铜、铝、金、或银)、或其合金制成。
根据一些实施例,如图1F及图1F-1所绘示,形成焊料层170于导电垫160之上。根据一些实施例,导电垫160位于装置150及焊料层170之间。根据一些实施例,焊料层170以导电材料例如合金材料包括锡、铜、银、锑、铟、锌、及/或铅制成。根据一些实施例,如图1F-1所绘示,突出部分154(或柱状结构154a)包围导电垫160及焊料层170。
根据一些实施例,图1F-2为图1F的装置150的底视图。根据一些实施例,图1F为图1F-2中所绘示的装置150沿剖面线I-I’的剖面图。在一些实施例中,如图1F及图1F-2中所绘示,突出部分154为连续条状结构。根据一些实施例,突出部分154连续围绕导电垫160和焊料层170。
根据一些实施例,如图1G中所绘示,装置150通过导电垫160及焊料层170接合至导电垫142。根据一些实施例,在此步骤中,形成了半导体装置100。根据一些实施例,接合装置150至导电垫142时,突出部分154接合至突出部分114(或绝缘层A)。
根据一些实施例,配置突出部分114及154支撑装置150,以保持装置150的水平,避免装置150受焊料层170的影响。在一些其他实施例中,绝缘层A未形成于突出部分114之上,且突出部分154与突出部分114直接接触。
根据一些实施例,突出部分154对齐突出部分114。根据一些实施例,若突出部分154包括柱状结构154a(如图1F-1所绘示),突出部分114包括柱状结构114a(如图1A-1所绘示)。根据一些实施例,若突出部分154包括连续条状结构(如图1F-2中所绘示),突出部分114包括连续条状结构(如图1A-2中所绘示)。
根据一些实施例,突出部分154包围导电垫142。根据一些实施例,焊料层170覆盖弯曲顶表面142a。根据一些实施例,导电垫142部分延伸入焊料层170之中。在一些实施例中,导电垫142的上部埋藏于焊料层170之中。因此,根据一些实施例,改善了导电垫142及焊料层170之间的粘结性。
根据一些实施例,如图1G-1中所绘示,突出部分114及154具有相同形状。根据一些实施例,如图1G-1中所绘示,突出部分154包括柱状结构154a,以及突出部分114包括柱状结构114a。根据一些实施例,柱状结构154a分别与其下相对应的柱状结构114a对齐。
根据一些实施例,如图1G-1中所绘示,柱状结构154a与其下相对应的柱状结构114a具有相同的形状,例如矩形、圆形、椭圆形、三角形、或另一多边形。
根据一些实施例,图1G-2为图1G的半导体装置的上视图。根据一些实施例,图1G为图1G-2中所绘示的半导体装置沿剖面线I-I’的剖面图。在一些实施例中,如图1G及图1G-2中所绘示,突出部分154包括连续条状结构,以及突出部分114包括连续条状结构。
根据一些实施例,突出部分154的连续条状结构与突出部分114的连续条状结构对齐。根据一些实施例,如图1G-2中所绘示,突出部分154的连续条状结构与突出部分114的连续条状结构具有相同的形状,例如U型。
根据一些实施例,图2为半导体装置200的剖面图。根据一些实施例,如图2中所绘示,半导体装置200类似于图1G中的半导体装置100,除了半导体装置200不具有半导体装置100的突出部分114及154之外。根据一些实施例,半导体装置200的形成制程与半导体装置100的形成制程相似或相同。
根据一些实施例,图3A-图3F为形成半导体装置制程各阶段的剖面图。根据一些实施例,如图3A中所绘示,提供了基板110。根据一些实施例,基板110具有区域R1及R2。
根据一些实施例,区域R1中基板110的厚度T4与区域R2中基板110的厚度T5不同。根据一些实施例,厚度T4小于厚度T5。
根据一些实施例,基板110具有表面112。根据一些实施例,表面112具有凹槽116。根据一些实施例,凹槽116在区域R1之中。根据一些实施例,如图3A所绘示,形成绝缘层A于表面112之上及凹槽116之中。
根据一些实施例,如图3A所绘示,形成导电结构310于凹槽116的底表面116a上的绝缘层A之上。导电结构310包括导电线,其与图1G的导电线120或其他合适的导电结构相似或相同。
根据一些实施例,导电结构310以导电材料例如金属(例如钨、铜、或铝)或其合金制成。根据一些实施例,使用电镀镀覆制程及蚀刻制程形成导电结构310。
根据一些实施例,如图3B中所绘示,形成掩膜层130于绝缘层A之上。根据一些实施例,掩膜层130具有开口132。根据一些实施例,开口132位于导电结构310之上。根据一些实施例,掩膜层130覆盖凹槽116的内壁116b。
根据一些实施例,内壁116b亦可称为区域R1及R2之间的边界。根据一些实施例,掩膜层130延伸跨越区域R1及R2之间的边界。
在一些实施例中,开口132的宽度W1朝基板110增加。根据一些实施例,开口132的上部132u的宽度W1朝基板110持续增加。
根据一些实施例,覆盖内壁116b的掩膜层130具有凹槽134。根据一些实施例,凹槽134从开口132的内壁132a凹蚀。根据一些实施例,凹槽134在凹槽116之中。根据一些实施例,凹槽134靠近凹槽116的底表面116a。
根据一些实施例,开口132的下部132w的宽度W1持续朝基板110增加。根据一些实施例,掩膜层130具有在开口132的内壁132a与凹槽134之间的边缘部分G。根据一些实施例,边缘部分G包围开口132露出的导电结构310。
根据一些实施例,如图3C中所绘示,沉积导电层140于导电结构310、底表面116a、及掩膜层130之上。根据一些实施例,导电层140覆盖掩膜层130的顶表面136、开口132的内壁132a、及凹槽134的内壁134a。
根据一些实施例,内壁134上的导电层140比开口132的内壁132a上的导电层140薄。根据一些实施例,内壁132a上的导电层140比导电结构310上的导电层140薄。根据一些实施例,导电结构310上的导电层140比掩膜层130的顶表面136上的导电层140薄。
根据一些实施例,导电层140的沉积制程包括物理气相沉积制程。根据一些实施例,由于使用物理气相沉积制程形成导电层140于导电结构310之上,且导电层140被掩膜层130围绕,导电结构310上的导电层140具有弯曲的顶表面141a。
根据一些实施例,由于物理气相沉积制程在掩膜层130中产生热,掩膜层130变形,且掩膜层130的顶表面136变成弯曲的顶表面。根据一些实施例,弯曲的顶表面136上的导电层140亦具有弯曲的顶表面141b。
根据一些实施例,如图3D中所绘示,移除内壁132a、凹槽134、及绝缘层A上的导电层140。根据一些实施例,在移除制程之后,余留在导电结构310上的导电层140形成了导电垫142。
根据一些实施例,导电垫142具有弯曲顶表面142a。在一些实施例中,导电垫142的宽度W2朝基板110增加。根据一些实施例,宽度W2朝基板110持续增加。根据一些实施例,移除制程包括蚀刻制程,例如湿蚀刻制程。
根据一些实施例,如图3E所绘示,提供了装置150。装置150包括芯片、封装、主动装置、被动装置、发光装置、或其他合适的装置。根据一些实施例,发光装置包括发射激光光束的激光二极管(未绘示)。根据一些实施例,装置150具有底表面152。
根据一些实施例,如图3E中所绘示,形成导电垫160于装置150的底表面152上。根据一些实施例,导电垫160电性连接于装置150。根据一些实施例,如图3E中所绘示,形成焊料层170于导电垫160之上。根据一些实施例,导电垫160位于装置150及焊料层170之间。
根据一些实施例,如图3F中所绘示,装置150通过导电垫160及焊料层170接合至导电垫142。根据一些实施例,导电垫142部分延伸入焊料层170中。根据一些实施例,焊料层170部分位于凹槽116中。根据一些实施例,在这个步骤,形成半导体装置300。
根据一些实施例,图4A-图4F为形成半导体装置制程各阶段的剖面图。根据一些实施例,如图4A中所绘示,提供了基板110。根据一些实施例,基板110具有区域R1及R2。
根据一些实施例,区域R1中基板110的厚度T6与区域R2中基板110的厚度T7不同。根据一些实施例,厚度T6大于厚度T7。
根据一些实施例,基板110具有基座117及台座118。根据一些实施例,台座118位于基座117之上。根据一些实施例,基座117比台座118宽。根据一些实施例,基座117位于区域R1及R2之中。根据一些实施例,台座118位于区域R1中。
根据一些实施例,如图4A中所绘示,形成绝缘层A于基板110之上。根据一些实施例,如图4A中所绘示,形成导电结构310于台座118的顶表面118a上的绝缘层A之上。导电结构310包括导电线,其与图1G的导电线120或其他合适的导电结构相似或相同。
根据一些实施例,如图4B中所绘示,形成掩膜层130于基座117和台座118之上。根据一些实施例,掩膜层130具有开口132。根据一些实施例,开口132位于台座118的顶表面118a上。根据一些实施例,掩膜层130覆盖台座118的顶表面118a的周围部分118p。
根据一些实施例,覆盖台座118的掩膜层130比覆盖基座117的掩膜层130薄。根据一些实施例,掩膜层130覆盖台座118的侧壁118b。根据一些实施例,侧壁118b亦称为区域R1及R2之间的边界。
根据一些实施例,如图4C中所绘示,沉积导电层140于导电结构310、顶表面118a、及掩膜层130之上。根据一些实施例,导电层140覆盖掩膜层130的顶表面136、开口132的内壁132a、及凹槽134的内壁134a。
根据一些实施例,内壁134a上的导电层140比开口132的内壁132a上的导电层140薄。根据一些实施例,内壁132a上的导电层140比导电结构310上的导电层140薄。根据一些实施例,导电结构310上的导电层140比掩膜层130的顶表面136上的导电层140薄。
根据一些实施例,导电层140的沉积制程包括物理气相沉积制程。根据一些实施例,由于使用物理气相沉积制程形成导电层140于导电结构310之上,且导电层140被掩膜层130围绕,导电结构310上的导电层140具有弯曲的顶表面141a。
根据一些实施例,由于物理气相沉积制程在掩膜层130中产生热,掩膜层130变形,且掩膜层130的顶表面136变成弯曲的顶表面。根据一些实施例,弯曲的顶表面136上的导电层140亦具有弯曲的顶表面141b。
根据一些实施例,如图4D中所绘示,移除内壁132a、凹槽134、及绝缘层A上的导电层140。根据一些实施例,在移除制程之后,余留在导电结构310上的导电层140形成了导电垫142。
根据一些实施例,导电垫142具有弯曲顶表面142a。在一些实施例中,导电垫142的宽度W2朝基板110增加。根据一些实施例,宽度W2朝基板110持续增加。根据一些实施例,移除制程包括蚀刻制程,例如湿蚀刻制程。
根据一些实施例,如图4E所绘示,提供了装置150。装置150包括芯片、封装、主动装置、被动装置、发光装置、或其他合适的装置。根据一些实施例,发光装置包括发射激光光束的激光二极管(未绘示)。根据一些实施例,装置150具有底表面152。
根据一些实施例,如图4E中所绘示,形成导电垫160于装置150的底表面152上。根据一些实施例,导电垫160电性连接于装置150。根据一些实施例,如图4E中所绘示,形成焊料层170于导电垫160之上。根据一些实施例,导电垫160位于装置150及焊料层170之间。
根据一些实施例,如图4F中所绘示,装置150通过导电垫160及焊料层170接合至导电垫142。根据一些实施例,导电垫142部分延伸入焊料层170中。根据一些实施例,在这个步骤,形成半导体装置400。
本发明实施例可做许多变化及/或修改。例如,在不同实施例中,图1A、图1A-1、及图1A-2的突出部分114的形状、轮廓、及/或分布可不同。根据一些实施例,图5-图14为突出部分114不同变化的上视图。
根据一些实施例,如图5中所绘示,图5的突出部分114与图1A-1的突出部分114相似,除了图5的突出部分114包围整个导电线120。根据一些实施例,突出部分114包括彼此相隔的柱状结构114a。
根据一些实施例,如图6中所绘示,图6的突出部分114与图1A-1的突出部分114相似,除了图6的突出部分114具有L型。根据一些实施例,突出部分114邻近导电线120的侧壁124及126。根据一些实施例,突出部分114包括彼此相隔的柱状结构114a。根据一些实施例,柱状结构114a沿侧壁124及126布置。
根据一些实施例,如图7中所绘示,图7的突出部分114与图1A-1的突出部分114相似,除了图7的突出部分114仅邻近导电线120的两侧壁124及128。根据一些实施例,突出部分114包括彼此相隔的柱状结构114a。根据一些实施例,柱状结构114a沿侧壁124及128布置。
根据一些实施例,如图8中所绘示,图8的突出部分114与图1A-1的突出部分114相似,除了图8的突出部分114仅邻近导电线120的一侧壁124。根据一些实施例,突出部分114包括彼此相隔的柱状结构114a。根据一些实施例,柱状结构114a沿侧壁124布置。
根据一些实施例,如图9中所绘示,图9的突出部分114与图1A-1的突出部分114相似,除了图9的突出部分114邻近导电线120的角落129a、129b、129c、及129d。根据一些实施例,突出部分114包括彼此相隔的柱状结构114a。
根据一些实施例,如图10中所绘示,图10的突出部分114与图1A-2的突出部分114相似,除了图10的突出部分114连续包围整个导电线120。
根据一些实施例,如图11中所绘示,图11的突出部分114与图1A-2的突出部分114相似,除了图11的突出部分114具有L型。根据一些实施例,突出部分114邻近导电线120的侧壁124及126。
根据一些实施例,如图12中所绘示,图12的突出部分114与图1A-2的突出部分114相似,除了图12的突出部分114邻近导电线120的角落129a及129c。根据一些实施例,图12的突出部分114包围角落129a及129c。
根据一些实施例,如图13中所绘示,图13的突出部分114与图1A-2的突出部分114相似,除了图13的突出部分114仅邻近导电线120的两侧壁124及128。
根据一些实施例,如图14中所绘示,图14的突出部分114与图1A-2的突出部分114相似,除了图14的突出部分114仅邻近导电线120的一侧壁124。
应注意的是,图2-图14中与图1A-图1G中相同命名或标示的元件具有相似或相同的材料、结构(包括相对尺寸、角度、形状、厚度、宽度、等等)、及形成方法。因此,此处不重复详细描述。
根据一些实施例,提供了半导体装置及其形成方法。方法(用以形成半导体装置)使用剥离制程以形成被突出部分包围的导电垫,以避免形成导电垫受到突出部分的影响。
根据一些实施例,提供了一种半导体装置的形成方法。此方法包括提供基板。此方法包括形成掩膜层于基板的表面之上。掩膜层具有开口位于表面的部分之上。此方法包括沉积导电层于表面及掩膜层之上。此方法包括移除掩膜层及掩膜层之上的导电层。在移除掩膜层及掩膜层之上的导电层之后,余留的导电层形成导电垫。导电垫的宽度朝着基板增加。此方法包括通过焊料层接合装置至导电垫。导电垫埋藏于焊料层中。在一实施例中,导电层覆盖掩膜层的顶表面及开口的内壁,且此方法更包括在沉积导电层于表面的部分及掩膜层之上之后且在移除掩膜层及掩膜层上的导电层之前,移除内壁上的导电层。在一实施例中,内壁上的导电层比表面的部分上的导电层薄,且表面的部分上的导电层比掩膜层的顶表面上的导电层薄。在一实施例中,掩膜层以负光阻材料制成。在一实施例中,开口的宽度朝向基板增加。在一实施例中,导电垫具有弯曲顶表面。在一实施例中,基板具有从表面突出的第一突出部分,第一突出部分邻近表面的部分,且掩膜层覆盖整个第一突出部分。在一实施例中,第一突出部分包围表面的部分。在一实施例中,第一突出部分包括彼此相隔的柱状结构。在一实施例中,装置具有底表面及从底表面突出的第二突出部分。在一实施例中,半导体装置的形成方法更包括在接合装置至导电垫时,接合第二突出部分至第一突出部分。
根据一些实施例,提供了一种半导体装置的形成方法。此方法包括提供基板,其具有第一区域及第二区域。第一区域中的基板及第二区域中的基板具有不同的厚度。此方法包括形成掩膜层于基板的表面上。掩膜层延伸跨越第一区域及第二区域之间的边界,且掩膜层具有开口于第一区域中的表面之上。此方法包括沉积导电层于掩膜层之上以及开口之下的表面。此方法包括移除掩膜层及掩膜层之上的导电层,其中在移除掩膜层及掩膜层之上的导电层之后,余留在表面上的导电层形成第一导电垫。此方法包括接合装置至第一导电垫。在一实施例中,此方法更包括在接合装置至第一导电垫前,形成第二导电垫于装置的底表面之上,以及形成焊料层于第二导电垫之上,装置通过第二导电垫及焊料层接合至第一导电垫,且第一导电垫部分延伸入焊料层。在一实施例中,第一导电垫具有弯曲顶表面,且焊料层覆盖弯曲顶表面。在一实施例中,在第一区域中表面具有第一凹槽,开口位于第一凹槽的底表面上,掩膜层覆盖第一凹槽的第一内壁,导电层位于底表面及掩膜层之上,且形成第一导电垫于底表面之上。在一实施例中,覆盖第一凹槽的第一内壁的掩膜层具有第二凹槽,第二凹槽从掩膜层的开口的第二内壁凹蚀,导电层进一步沉积于第二凹槽的第三内壁之上,且第二凹槽的第三内壁上的导电层比开口的第二内壁上的导电层薄。在一实施例中,基板具有基座和基座之上的台座,基座在第一区域及第二区域之中,台座在第一区域之中,掩膜层位于基座和台座之上,掩膜层覆盖台座的侧壁,开口在台座之上,导电层沉积于台座及掩膜层之上,且导电垫位于台座之上。在一实施例中,台座上的掩膜层比基座上的掩膜层薄。
根据一些实施例,提供了一种半导体装置。半导体装置包括具有表面的基板。半导体装置包括第一导电垫位于表面的部分之上。第一导电垫具有弯曲的顶表面,且第一导电垫的宽度朝基板增加。半导体装置包括装置于第一导电垫之上。半导体装置包括焊料层在装置及第一导电垫之间。焊料层覆盖弯曲的顶表面,且第一导电垫埋藏于焊料层之中。在一实施例中,基板具有第一区域及第二区域,第一区域中的基板及第二区域中的基板具有不同厚度,且导电垫在第一区域之中。
前述内文概述了许多实施例的特征部件,使本技术领域中具有通常知识者可以从各个方面更佳地了解本发明实施例。本技术领域中具有通常知识者应可理解,且可轻易地以本发明实施例为基础来设计或修饰其他制程及结构,并以此达到相同的目的及/或达到与在此介绍的实施例相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未背离本发明实施例的发明精神与范围。在不背离本发明实施例的发明精神与范围的前提下,可对本发明实施例进行各种改变、置换或修改,因此本发明的保护范围当视后附的权利要求所界定者为准。另外,虽然本发明已以数个优选实施例公开如上,然其并非用以限定本发明,且并非所有优点都已于此详加说明。
Claims (1)
1.一种半导体装置的形成方法,包括:
提供一基板;
形成一掩膜层于该基板的一表面之上,其中该掩膜层具有一开口位于该表面的一部分之上;
沉积一导电层于该表面的该部分及该掩膜层之上;
移除该掩膜层及该掩膜层之上的导电层,其中在移除该掩膜层及该掩膜层之上的导电层之后,在该表面的该部分之上余留的该导电层形成一导电垫,且该导电垫的一宽度朝着该基板增加;以及
通过一焊料层接合一装置至该导电垫,其中该导电垫埋藏于该焊料层中。
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US20230068503A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip structure and method for forming the same |
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US20230068503A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip structure and method for forming the same |
US11688708B2 (en) * | 2021-08-30 | 2023-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip structure and method for forming the same |
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