CN113937098A - Electrostatic protection chip for rapid charging management system and preparation method thereof - Google Patents
Electrostatic protection chip for rapid charging management system and preparation method thereof Download PDFInfo
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- CN113937098A CN113937098A CN202111107691.1A CN202111107691A CN113937098A CN 113937098 A CN113937098 A CN 113937098A CN 202111107691 A CN202111107691 A CN 202111107691A CN 113937098 A CN113937098 A CN 113937098A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 75
- 239000007924 injection Substances 0.000 claims abstract description 75
- 239000002184 metal Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000002513 implantation Methods 0.000 claims description 68
- 238000011049 filling Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims 2
- 230000002829 reductive effect Effects 0.000 description 11
- 230000002457 bidirectional effect Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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Abstract
The invention discloses an electrostatic protection chip for a rapid charging management system, which comprises a substrate, a first epitaxial layer formed on the substrate, a first injection region on the first epitaxial layer, a second injection region on the first injection region and a second epitaxial layer on the second injection region, a first groove extending from the second epitaxial layer to the first epitaxial layer, a second groove positioned between the first grooves, a silicon oxide layer filled in the first groove, a third epitaxial layer filled in the second groove, a third injection region formed in the third epitaxial layer, a fourth injection region in the second epitaxial layer, a first dielectric layer, a second dielectric layer, a first contact hole and a second contact hole positioned between the first dielectric layer and the second dielectric layer, a first metal layer on the first dielectric layer and in the first contact hole, and a second metal layer on the second dielectric layer and in the second contact hole. The invention also provides a preparation method of the electrostatic protection chip for the rapid charging management system, which improves the discharge density and reduces the manufacturing cost of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor chip manufacturing processes, and particularly relates to an electrostatic protection chip for a rapid charging management system and a preparation method thereof.
Background
As semiconductor devices increasingly tend to be miniaturized, high density, and multifunctional, electronic devices are increasingly susceptible to voltage surges, even fatal damage. Transient current spikes can be induced by various voltage surges from static discharge to lightning, and Transient Voltage Suppressors (TVS) are generally used to protect sensitive circuits from surges. Based on different applications, the transient voltage suppressor can play a circuit protection role by changing the surge discharge path and the clamping voltage of the transient voltage suppressor.
The low-capacitance TVS structure is suitable for a protection device of a high-frequency circuit because it can reduce the interference of parasitic capacitance to the circuit and reduce the attenuation of signals of the high-frequency circuit. TVS is largely used as a circuit protection device in a quick charge power supply management system, the quick charge power supply management system is very sensitive to signal attenuation and interference of parasitic capacitance, and a low-capacitance TVS chip is very important for improving the quick charge power supply management system. Generally, in order to improve the reverse characteristic of TVS, a guard ring structure and a metal field plate structure are adopted, but both structures easily introduce a large additional capacitance and increase the device area, resulting in a reduction in the operating performance of the device.
Disclosure of Invention
In view of the above, the present invention provides an electrostatic protection chip for a fast charge management system, which reduces device parasitic capacitance, improves discharge density, and improves device performance, and a method for manufacturing the electrostatic protection chip, so as to solve the above technical problems.
In a first aspect, the present invention provides an electrostatic protection chip for a fast charge management system, including:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type formed on the substrate;
the epitaxial wafer comprises a first epitaxial layer, a second epitaxial layer and a first epitaxial layer, wherein the first epitaxial layer is formed on the upper surface of the first epitaxial layer;
the second epitaxial layer is arranged in the first epitaxial layer, the first epitaxial layer is arranged in the first epitaxial layer, the second epitaxial layer is arranged in the second epitaxial layer, the second epitaxial layer is arranged in the first epitaxial layer, the second epitaxial layer is arranged in the second epitaxial layer, and the junction depth of the second trench is smaller than that of the first trench;
a third implanted region of the first conductivity type formed in the third epitaxial layer, a fourth implanted region of the first conductivity type formed in the second epitaxial layer between the first trenches;
forming first dielectric layers arranged at intervals on the upper surfaces of the second epitaxial layer, the silicon oxide layer, the third epitaxial layer and part of the third injection region, and forming second dielectric layers arranged at intervals on the upper surfaces of part of the third injection region, the third epitaxial layer, the second epitaxial layer and part of the fourth injection region;
and forming a first contact hole between the first dielectric layer and the second dielectric layer and a second contact hole between the second dielectric layer, wherein a first metal layer is formed in the first contact hole and the upper surface of the first dielectric layer, a second metal layer is formed in the upper surface of the second dielectric layer and the second contact hole, and the first metal layers are symmetrically arranged relative to the second metal layer.
In a second aspect, the present invention further provides a method for manufacturing an electrostatic protection chip for a fast charge management system, including the following steps:
providing a substrate of a first conductive type, and forming a first epitaxial layer of a second conductive type on the substrate;
forming a first injection region of a second conductive type and a second injection region of the first conductive type on the upper surface of the first injection region on the first epitaxial layer, and forming a second epitaxial layer of the first conductive type on the upper surface of the second injection region;
photoetching the second epitaxial layer to form first trenches arranged at intervals, and filling silicon oxide into the first trenches to form a silicon oxide layer;
etching the upper surface of the second epitaxial layer between the first trenches to form a second trench which penetrates through the second epitaxial layer, the second injection region and the first injection region and extends into the first epitaxial layer, wherein the junction depth of the second trench is smaller than that of the first trench;
filling second conductive type ions into the second groove to form a third epitaxial layer;
respectively performing first conductive type ion implantation in the third epitaxial layer and the second epitaxial layer between the first trenches to form a third implantation region and a fourth implantation region;
growing a medium on the upper surface of the second epitaxial layer, respectively removing the corresponding medium on the upper surfaces of the third injection region and the fourth injection region to form a first contact hole and a second contact hole, retaining the medium on the upper surfaces of the second epitaxial layer, the silicon oxide layer, the third epitaxial layer and part of the third injection region to form first medium layers arranged at intervals, and retaining part of the medium on the upper surfaces of the third injection region, the third epitaxial layer, the second epitaxial layer and part of the fourth injection region to form second medium layers arranged at intervals;
and filling metal into the first contact hole and the upper surface of the first dielectric layer to form a first metal layer, filling metal into the upper surface of the second dielectric layer and the second contact hole to form a second metal layer, wherein the first metal layer is symmetrically arranged relative to the second metal layer.
Compared with the prior art, the invention provides the electrostatic protection chip for the quick charge management system and the preparation method thereof, and the electrostatic protection chip has the following beneficial effects:
the first epitaxial layer with the conductivity type different from that of the substrate is formed on the substrate, the first injection region and the second injection region with the conductivity type different from that of the substrate are sequentially prepared on the upper surface of the first epitaxial layer, and the first injection region and the second injection region form a PN junction, so that the voltage resistance of the device can be enhanced. And forming a second epitaxial layer with the same conductivity type as the second injection region on the upper surface of the second injection region, wherein the second epitaxial layer can protect the first injection region and the second injection region, reduce etching damage and reduce leakage current in the device. The second epitaxial layer and the upper surface of the second epitaxial layer form a third injection region and a fourth injection region respectively, the third injection region and the third epitaxial layer are different in conduction type to form a PN junction, the upper surface of the third injection region forms a corresponding first metal layer, the upper surface of the fourth injection region forms a corresponding second metal layer, and the first metal layer and the second metal layer are located on the upper surface of the substrate to simplify the device preparation process. The device is integrated by using a simple process, the parallel connection of the multi-path bidirectional protection circuit can be realized, the parasitic capacitance of the device can be reduced by the isolation groove, and the protection requirement of the high-frequency device in the quick charging power supply management system is met. The second groove is filled with the third epitaxial layer and ion implantation is carried out to form the PN junction, so that the interface quality of the PN junction is ensured, the electric leakage of the device is reduced, the discharge structure adopts a groove form, the discharge density is improved, and the manufacturing cost of the device is also reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a flowchart of a method for manufacturing an esd protection chip for a fast charge management system according to an embodiment of the present invention;
fig. 2 to 9 are diagrams illustrating a manufacturing process of an esd protection chip for a fast charge management system according to an embodiment of the present invention;
FIG. 10 is a schematic circuit diagram of an ESD protection chip for a rapid charge management system according to an embodiment of the present invention;
fig. 11 is an equivalent circuit diagram of an esd protection chip for a fast charge management system according to an embodiment of the present invention.
The main element symbols are as follows:
10-a substrate; 11-a first epitaxial layer; 12-a first implanted region; 13-a second implanted region; 14-a second epitaxial layer; 15-a first trench; 16-a second trench; 17-a silicon oxide layer; 18-a third epitaxial layer; 20-a third implanted region; 21-a fourth implanted region; 22-a first dielectric layer; 23-a second dielectric layer; 24-a first contact hole; 25-a second contact hole; 30-a first metal layer; 40-a second metal layer; 50-a first diode; 60-second diode.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, 2 to 9, the present invention further provides a method for manufacturing an electrostatic protection chip for a fast charge management system, including the following steps:
s1: providing a substrate 10 of a first conductivity type, and forming a first epitaxial layer 11 of a second conductivity type on the substrate 10;
referring to fig. 2, in the embodiment, the first conductive type is P-type, the second conductive type is N-type, the P-type ions are boron, the N-type ions are phosphorus, and the substrate 10 is made of silicon, so that the manufacturing cost is low and the implementation is convenient. The first epitaxial layer 11 is prepared by adopting an epitaxial growth technology, the first epitaxial layer 11 and the substrate 10 can form PN junctions due to different conduction types, the epitaxial layer is formed by the extension growth of a new single crystal layer according to the crystal phase of the substrate, the silicon epitaxial growth is formed by growing a layer of crystal with the same crystal direction as the substrate and with good lattice structure integrity and different resistivity and thickness on a silicon single crystal substrate with a certain crystal direction, and the epitaxial layer can play a supporting role.
S2: forming a first implantation region 12 of a second conductivity type and a second implantation region 13 of the first conductivity type on the first epitaxial layer 11, wherein the second implantation region 13 is located on the upper surface of the first implantation region 12, and a second epitaxial layer 14 of the first conductivity type is formed on the upper surface of the second implantation region 13;
referring to fig. 3, in the present embodiment, the conductivity types of the first implantation region 12 and the second implantation region 13 are different, so that a PN junction can be formed, the doping concentrations and thicknesses of the first implantation region 12 and the second implantation region 13 can be the same or different, preferably, the thicknesses of the first implantation region 12 and the second implantation region 13 are greater than 5 μm, and the thicknesses of the second epitaxial layer 14 and the first epitaxial layer 11 are greater than 5 μm. Second conductive type ions are implanted into the upper surface of the first epitaxial layer 11 and are subjected to thermal annealing to form a first implanted region 12, the preparation process of the second implanted region 13 is the same as that of the first implanted region 12, then a second epitaxial layer 14 is formed on the upper surface of the second implanted region 13, the second epitaxial layer 14 and the second implanted region 13 are of the same conductive type, and the thickness of the second epitaxial layer 14 is larger than that of the second implanted region 13.
It should be noted that, by adjusting the ion dose of the first implantation region 12 and the second implantation region 13, the PN junction breakdown voltage, that is, the protection voltage of the device, may be affected if there is no protection of the second epitaxial layer 14, the implantation region is directly in contact with the metal layer, it needs a very high doping concentration to form ohmic contact with the metal layer, the ohmic contact is formed by a metal electrode and a silicon wafer, otherwise, the resistance greatly affects the performance of the device, the high doping concentration also affects the adjustment of the device breakdown voltage, the damage of the first implantation region 12 and the second implantation region 13 under the protection of the second epitaxial layer 14 can be reduced, meanwhile, the PN junction breakdown occurs inside the epitaxial layer and can reduce the leakage current, and the working performance of the device is improved to a certain extent.
S3: photoetching first trenches 15 which are arranged at intervals and extend from the second epitaxial layer 14 to the first epitaxial layer 11, and filling silicon oxide into the first trenches 15 to form a silicon oxide layer 17;
referring to fig. 4 and 5, in the present embodiment, photoresist is coated on the second epitaxial layer 14 at intervals, and the first trenches 15 are formed by performing photolithography on the second epitaxial layer 14 through the second implantation region 13, the first implantation region 12, and the first epitaxial layer 11, and etching, wherein the number of the first trenches 15 is preferably two for each group, and the distance between the two first trenches 15 in each group is greater than the width of the first trenches 15. The bottom of the first trench 15 is located in the first epitaxial layer 11, so that the second injection region 13, the first injection region 12, the second epitaxial layer 14 and the first epitaxial layer 11 can be isolated by the first trench 15, and silicon oxide filled in the first trench 15 can be used as an isolation trench, thereby reducing the leakage current of the device.
S4: etching the upper surface of the second epitaxial layer 14 located between the first trenches 15 to form second trenches 16 which penetrate through the second epitaxial layer 14, the second implantation regions 13 and the first implantation regions 12 and extend into the first epitaxial layer 11, wherein the junction depth of the second trenches 16 is smaller than that of the first trenches 15;
referring to fig. 6, in this embodiment, a photoresist is first coated on the upper surfaces of the second epitaxial layer 14 and the silicon oxide layer 17, the second epitaxial layer 14 between the first trenches 15 is exposed, a dry etching technique is adopted, a second trench 16 is formed from the upper surface of the second epitaxial layer 14, the second implantation region 13, the first implantation region 12 and the first epitaxial layer 11, the junction depth of the second trench 16 is smaller than that of the first trench 15, and the width of the second trench 16 is larger than that of the first trench 15, so that the device has a bidirectional characteristic, and a subsequent preparation process is facilitated.
S5: filling second conductive type ions into the second trench 16 to form a third epitaxial layer 18;
referring to fig. 7, in this embodiment, the second trenches 16 are filled with second conductivity type ions, that is, N-type ions, to form the third epitaxial layer 18, the doping concentration of the third epitaxial layer 18 is greater than that of the first epitaxial layer 11, and the third epitaxial layer 18 is located between the two first trenches 15, so that the uniform circulation of current inside the device can be ensured, and the working stability of the device is improved.
S6: respectively implanting ions of the first conductivity type into the second epitaxial layer 14 between the first trenches 15 and the third epitaxial layer 18 to form a third implanted region 20 and a fourth implanted region 21;
referring to fig. 8, in the present embodiment, photolithography is performed in the third epitaxial layer 18 and the second epitaxial layer 14, a third implantation region 20 is formed in the third epitaxial layer 18 by etching, a fourth implantation region 21 is formed in the second epitaxial layer 14 by etching, the third implantation region 20 and the fourth implantation region 21 are formed by etching at the same time, the doping concentrations of the third implantation region 20 and the fourth implantation region 21 are greater than that of the second implantation region 13, PN junctions can be formed between the third implantation region 20 and the third epitaxial layer 18 with different conductivity types, the conductivity type of the fourth implantation region 21 is the same as that of the second epitaxial layer 14, and the PN junction depth is increased, so that the voltage withstanding performance of the device is also increased. The third implantation regions 20 are symmetrically arranged with respect to the fourth implantation region 21, and the projection area of the fourth implantation region 21 in the direction perpendicular to the substrate 10 is larger than that of the third implantation region 20, so that the subsequent contact area between metal and semiconductor is facilitated to reduce the on-resistance and the on-loss of the device.
S7: performing dielectric growth on the upper surface of the second epitaxial layer 14, respectively removing the corresponding dielectrics on the upper surfaces of the third implantation region 20 and the fourth implantation region 21 to form a first contact hole 24 and a second contact hole 25, retaining the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 18 and part of the dielectrics on the upper surface of the third implantation region 20 to form first dielectric layers 22 arranged at intervals, and retaining part of the dielectrics on the upper surfaces of the third implantation region 20, the third epitaxial layer 18, the second epitaxial layer 14 and part of the fourth implantation region 21 to form second dielectric layers 23 arranged at intervals;
referring to fig. 9, in the present embodiment, first, a dielectric growth is performed on the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 20, the third implantation region 20, and the fourth implantation region 21, the dielectrics on the upper surfaces of the third implantation region 20 and the fourth implantation region 21 are removed to form a first contact hole 24 and a second contact hole 25, the dielectrics on the upper surfaces of the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 18, and a part of the third implantation region 20 are retained to form a first dielectric layer 22, and the dielectrics on the upper surfaces of the third implantation region 20, the third epitaxial layer 18, the silicon oxide layer 17, the second epitaxial layer 14, and a part of the fourth implantation region 21 are retained to form a second dielectric layer 23, the first contact hole 24 is located between the first dielectric layer 22 and the second dielectric layer 23, the second contact hole 25 is located between the two second dielectric layers 23, and the size of the second contact hole 25 is larger than that of the first contact hole 24. And forming a first dielectric layer 22, a second dielectric layer 23, a first contact hole 24 and a second contact hole 25 by adopting dry etching, wherein the first contact hole 24 is symmetrically arranged relative to the second contact hole 25.
S8: filling metal into the first contact hole 24 and the upper surface of the first dielectric layer 22 to form a first metal layer 30, filling metal into the upper surface of the second dielectric layer 23 and the second contact hole 25 to form a second metal layer 40, wherein the first metal layer 30 is symmetrically arranged relative to the second metal layer 40.
Referring to fig. 9 again, in this embodiment, a magnetron sputtering technique is used to fill metal into the first dielectric layer 22, the second dielectric layer 23, the first contact hole 24, and the second contact hole 25, and then a dry etching technique is used to remove a portion of the metal on the second dielectric layer 23, the first metal layer 30 is L-shaped, the second metal layer 40 is T-shaped, the first metal layer 30 is symmetrically disposed with respect to the second metal layer 40, the first metal layer 30 and the second metal layer 40 are both located on the upper surface of the substrate 10, the first metal layer 30 and the second metal layer 40 can be used as two electrodes of a device to be connected into a circuit, the second metal layer 40 is a position for protecting a current leakage circuit, and the device can implement bidirectional protection.
It should be noted that, in the preparation process of the device, parallel connection of multiple bidirectional protection circuits can be realized only by using simple process integration, the parasitic capacitance of the device is reduced by the first trench 15, i.e., the isolation trench, so that the protection requirement of a high-frequency device in a rapid charging power management system can be met, the second trench 16, i.e., the deep trench, fills the N-type epitaxy, and forms a PN junction by ion implantation in the N-type epitaxy layer, so that the interface quality of the PN junction is ensured, and the leakage of the device is reduced. The discharge structure adopts a groove form, so that the discharge density is improved, and the manufacturing cost of the device is also reduced.
Referring again to fig. 9, the present invention also provides an esd chip for a fast charge management system, including:
a substrate 10 of a first conductivity type;
a first epitaxial layer 11 of a second conductivity type formed on the substrate 10;
a first implantation region 12 of the second conductivity type formed on the upper surface of the first epitaxial layer 11, a second implantation region 13 of the first conductivity type formed on the first implantation region 12, and a second epitaxial layer 14 of the first conductivity type formed on the upper surface of the second implantation region 13;
a third implanted region 20 of the first conductivity type formed in said third epitaxial layer 18, a fourth implanted region 21 of the first conductivity type formed in said second epitaxial layer 14 between said first trenches 15;
first dielectric layers 22 formed on the upper surfaces of the second epitaxial layer 14, the silicon oxide layer 17, the third epitaxial layer 18 and a part of the third implantation region 20 at intervals, and second dielectric layers 23 formed on the upper surfaces of a part of the third implantation region 20, the third epitaxial layer 18, the second epitaxial layer 14 and a part of the fourth implantation region 21 at intervals;
forming a first contact hole 24 between the first dielectric layer 22 and the second dielectric layer 23 and a second contact hole 25 between the second dielectric layer 23, forming a first metal layer 30 in the first contact hole 24 and on the upper surface of the first dielectric layer 22, forming a second metal layer 40 in the upper surface of the second dielectric layer 23 and in the second contact hole 25, and symmetrically arranging the first metal layer 30 with respect to the second metal layer 40.
In this embodiment, the first conductive type is P-type, the second conductive type is N-type, and the first trench 15 extends into the first epitaxial layer 11 along the upper surface of the second epitaxial layer 14 to implement isolation, thereby reducing leakage current. The first epitaxial layer 11 may form a PN junction with a different conductivity type from the substrate 10. The second trench 16 is located between the two first trenches 15, the junction depth of the second trench 16 is smaller than that of the first trenches 15, the second trench 16 is filled with the third epitaxial layer 18, the first trench 15 is filled with the silicon oxide layer 17, the first trench 15 is an isolation trench, and the second trench 16 can realize bidirectional protection of the device. The doping concentration of the third epitaxial layer 18 is greater than that of the first epitaxial layer 11, the second epitaxial layer 14 can protect the second injection region 13 and the first injection region 12 from being damaged by etching, meanwhile, breakdown of PN junctions formed by different conduction types of the first injection region 12 and the second injection region 13 occurs in the epitaxial layers of the device, leakage current can be reduced, and the voltage resistance of the device is also improved. The third injection region 20 and the fourth injection region 21 are of the same conductivity type and are prepared and formed at the same time, the third injection region 20 is symmetrically arranged relative to the fourth injection region 21, the third injection region 20 and the third epitaxial layer 18 form a PN junction, the fourth injection region 21 and the second epitaxial layer 14 are of the same conductivity type, the doping concentrations of the third injection region 20 and the fourth injection region 21 are greater than that of the second injection region 13, and the current path and the current uniform distribution in the device can be increased.
Referring to fig. 10 and fig. 11, it should be noted that, when a device is connected to a circuit, the first metal layer 30 is connected to a voltage input terminal, the first metal layer 30 on the other side can be connected to another voltage input terminal, the second metal layer 40 can be connected to a voltage output terminal, a current path where the third injection region 20, the third epitaxial layer, the first epitaxial layer 11, the first injection region 12, the second injection region 13, the second epitaxial layer 14, and the fourth injection region 21 are located, that is, P-N-P, can be used as an electrostatic protection circuit, and the second metal layer 40 is a position where a protection leakage current circuit is connected, so that the device can implement two-way protection. The third implantation region 20 and the third epitaxial layer 18 form a first diode 50, i.e., a P-N junction hook, the first epitaxial layer 11, the first implantation region 12, the second implantation region 13, the second epitaxial layer 14 and the fourth implantation region 21 form a second diode 60, i.e., an N-P structure, similar to a bidirectional TVS, and the first metal layer 30 and the second metal layer 40 are both located on the upper surface of the substrate 10, so that multi-path bidirectional protection can be realized, and the application range of the device is improved.
The invention provides an electrostatic protection chip for a rapid charging management system and a preparation method thereof, wherein a first epitaxial layer 11 with a different conductive type from a substrate is formed on the substrate 10, a first injection region 12 and a second injection region 13 with different conductive types are sequentially prepared on the upper surface of the first epitaxial layer 11, and the first injection region 12 and the second injection region 13 form a PN junction to enhance the voltage resistance of a device. A second epitaxial layer 14 with the same conductivity type as the second implantation region 13 is formed on the upper surface of the second implantation region 13, and the second epitaxial layer 14 can protect the first implantation region 12 and the second implantation region 13 and reduce etching damage, and can also reduce leakage current in the device. A first trench 15 is formed by extending the second epitaxial layer 14 into the first epitaxial layer 11, a silicon oxide layer 17 is filled in the first trench 15, the first trench can be used as an isolation trench and a plurality of current paths are formed, a second trench 16 is formed between the two first trenches 15, the junction depth of the second trench 16 is smaller than that of the first trench 15, a third epitaxial layer 18 with doping concentration larger than that of the first epitaxial layer 11 is filled in the second trench 16, a third injection region 20 and a fourth injection region 21 are respectively formed on the upper surfaces of the third epitaxial layer 18 and the second epitaxial layer 14, the third injection region 20 and the third epitaxial layer 18 form a PN junction with different conduction types, a corresponding first metal layer 30 is formed on the upper surface of the third injection region 20, a corresponding second metal layer 40 is formed on the upper surface of the fourth injection region 21, and the first metal layer 30 and the second metal layer 40 are located on the upper surface of the substrate 10, so that the device manufacturing process can be simplified. The device is integrated by using a simple process, the parallel connection of the multi-path bidirectional protection circuit can be realized, the parasitic capacitance of the device can be reduced by the isolation groove, and the protection requirement of the high-frequency device in the quick charging power supply management system is met. The second groove 16 is filled with the third epitaxial layer 18 and ion implantation is carried out to form a PN junction, so that the interface quality of the PN junction is ensured, the electric leakage of the device is reduced, the discharge structure adopts a groove form, the discharge density is improved, and the manufacturing cost of the device is also reduced.
In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (10)
1. An electrostatic protection chip for a rapid charge management system, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type formed on the substrate;
the epitaxial wafer comprises a first epitaxial layer, a second epitaxial layer and a first epitaxial layer, wherein the first epitaxial layer is formed on the upper surface of the first epitaxial layer;
the second epitaxial layer is arranged in the first epitaxial layer, the first epitaxial layer is arranged in the first epitaxial layer, the second epitaxial layer is arranged in the second epitaxial layer, the second epitaxial layer is arranged in the first epitaxial layer, the second epitaxial layer is arranged in the second epitaxial layer, and the junction depth of the second trench is smaller than that of the first trench;
a third implanted region of the first conductivity type formed in the third epitaxial layer, a fourth implanted region of the first conductivity type formed in the second epitaxial layer between the first trenches;
forming first dielectric layers arranged at intervals on the upper surfaces of the second epitaxial layer, the silicon oxide layer, the third epitaxial layer and part of the third injection region, and forming second dielectric layers arranged at intervals on the upper surfaces of part of the third injection region, the third epitaxial layer, the second epitaxial layer and part of the fourth injection region;
and forming a first contact hole between the first dielectric layer and the second dielectric layer and a second contact hole between the second dielectric layer, wherein a first metal layer is formed in the first contact hole and the upper surface of the first dielectric layer, a second metal layer is formed in the upper surface of the second dielectric layer and the second contact hole, and the first metal layers are symmetrically arranged relative to the second metal layer.
2. The ESD chip for rapid charge management system according to claim 1, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the width of the first trench is smaller than the width of the second trench.
3. The ESD chip of claim 1, wherein the junction depths of the first and second implanted regions are the same, and the doping concentration of the first implanted region is the same as the doping concentration of the second implanted region.
4. The esd protection chip for rapid charge management system of claim 1, wherein the doping concentration of the third epitaxial layer is greater than the doping concentration of the first epitaxial layer.
5. The ESD chip of claim 1, wherein the third implant region has an ion concentration greater than the second implant region.
6. The esd-protection chip for rapid charge management system according to claim 1, wherein the first contact hole has a smaller size than the second contact hole.
7. A preparation method of an electrostatic protection chip for a quick charge management system is characterized by comprising the following steps:
providing a substrate of a first conductive type, and forming a first epitaxial layer of a second conductive type on the substrate;
forming a first injection region of a second conductive type and a second injection region of the first conductive type on the upper surface of the first injection region on the first epitaxial layer, and forming a second epitaxial layer of the first conductive type on the upper surface of the second injection region;
photoetching the second epitaxial layer to form first trenches arranged at intervals, and filling silicon oxide into the first trenches to form a silicon oxide layer;
etching the upper surface of the second epitaxial layer between the first trenches to form a second trench which penetrates through the second epitaxial layer, the second injection region and the first injection region and extends into the first epitaxial layer, wherein the junction depth of the second trench is smaller than that of the first trench;
filling second conductive type ions into the second groove to form a third epitaxial layer;
respectively performing first conductive type ion implantation in the third epitaxial layer and the second epitaxial layer between the first trenches to form a third implantation region and a fourth implantation region;
growing a medium on the upper surface of the second epitaxial layer, respectively removing the corresponding medium on the upper surfaces of the third injection region and the fourth injection region to form a first contact hole and a second contact hole, retaining the medium on the upper surfaces of the second epitaxial layer, the silicon oxide layer, the third epitaxial layer and part of the third injection region to form first medium layers arranged at intervals, and retaining part of the medium on the upper surfaces of the third injection region, the third epitaxial layer, the second epitaxial layer and part of the fourth injection region to form second medium layers arranged at intervals;
and filling metal into the first contact hole and the upper surface of the first dielectric layer to form a first metal layer, filling metal into the upper surface of the second dielectric layer and the second contact hole to form a second metal layer, wherein the first metal layer is symmetrically arranged relative to the second metal layer.
8. The method of manufacturing an electrostatic protection chip for a rapid charge management system according to claim 7, wherein the thickness of the first epitaxial layer and the second epitaxial layer is greater than 5 μm.
9. The method for manufacturing an electrostatic protection chip for a rapid charging management system according to claim 7, wherein the first trench and the second trench are manufactured by dry etching, and the first metal layer and the second metal layer are manufactured by magnetron sputtering.
10. The method as claimed in claim 7, wherein a projected area of the third implantation region in a direction perpendicular to the substrate is smaller than a projected area of the fourth implantation region in a direction perpendicular to the substrate.
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| CN114695557A (en) * | 2022-03-31 | 2022-07-01 | 南通万亨新能源科技有限公司 | VDMOS device for lithium battery charging management and preparation method thereof |
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