CN112054020A - Low-capacitance electrostatic protection chip device and preparation method thereof - Google Patents
Low-capacitance electrostatic protection chip device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 183
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 89
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 89
- 238000002347 injection Methods 0.000 claims abstract description 31
- 239000007924 injection Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 150000002500 ions Chemical class 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- -1 oxygen ions Chemical class 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000011049 filling Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 32
- 238000002513 implantation Methods 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 22
- 239000007789 gas Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a low-capacitance electrostatic protection chip device and a preparation method thereof, wherein the device comprises an N-type substrate, a P-type ion injection region, an N-type injection region, a metal layer and a silicon dioxide layer, and the device preparation steps comprise the steps of preparing a silicon oxide layer by adopting a thermal oxidation method, forming a groove by dry etching, filling silicon dioxide in the groove, removing the silicon dioxide layer between the two grooves, injecting P-type ions to form the P-type ion injection region, forming junction depth by thermal diffusion, injecting N-type ions to form the N-type ion injection region, injecting oxygen ions to form the oxygen ion injection region, forming the silicon dioxide layer by thermal annealing and the like. The invention can adjust the breakdown voltage by simply controlling the junction depth and the N-type injection region distance, reduces the interface defect by the injection and thermal diffusion process, has simple process, reduces the manufacturing cost, reduces the PN junction area, reduces the parasitic capacitance, improves the switching speed of the device, and is more suitable for being applied in a high-frequency environment.
Description
Technical Field
The invention belongs to the technical field of semiconductor chip manufacturing processes, and particularly relates to a low-capacitance electrostatic protection chip device and a preparation method thereof.
Background
Electrostatic discharge (ESD) and other transient voltages that occur randomly in the form of some voltage surge are present in a variety of electronic devices. As semiconductor devices increasingly tend to be miniaturized, high density, and multifunctional, electronic devices are increasingly susceptible to voltage surges, even fatal damage.
The power device protection chip is a solid semiconductor device specially designed for protecting sensitive semiconductor devices from transient voltage surge damage, and has the advantages of small clamping coefficient, small volume, fast response, small leakage current, high reliability and the like, so that the power device protection chip is widely applied to voltage transient and surge protection. Based on different applications, the power device protection chip can play a circuit protection role by changing a surge discharge path and the clamping voltage of the power device protection chip. The low-capacitance power device protection chip can reduce the interference of parasitic capacitance to a circuit and reduce the attenuation of high-frequency circuit signals, and is suitable for a protection device of a high-frequency circuit.
The structure schematic diagram of a current commonly used large-current protection chip is shown in fig. 1, and the chip has the limitations of high parasitic capacitance and inflexible breakdown voltage adjustment.
Disclosure of Invention
Aiming at the problems of high parasitic capacitance and limitation that breakdown voltage cannot be flexibly adjusted in the prior art, the invention provides a low-capacitance electrostatic protection chip device and a preparation method thereof.
One of the objectives of the present application is to provide a low capacitance electrostatic protection chip device, which is specifically characterized as follows: a low-capacitance electrostatic protection chip device comprises a silicon dioxide layer, an N-type substrate, a P-type ion implantation area, an N-type implantation area and a metal layer; the silicon dioxide layers are distributed discontinuously and comprise a first silicon dioxide layer, a second silicon dioxide layer, a third silicon dioxide layer and a fourth silicon dioxide layer, the N-type substrate is arranged at the bottom of the device, the P-type ion implantation area is convex and is positioned in the middle of the device, the second silicon dioxide layer is positioned on the upper convex surface of the P-type ion implantation area, the first silicon dioxide layer is positioned on the upper concave surface of the P-type ion implantation area, the N-type injection region is positioned on the upper surface of the silicon dioxide layer A, the silicon dioxide layer B is positioned on the outer sides of two ends of the P-type ion injection region, a third silicon dioxide layer is distributed at the upper end of the fourth silicon dioxide layer and on one side far away from the P-type ion implantation area, the metal layer is symmetrically distributed on the upper surface of the device, the lower surface of the metal layer is connected with the third silicon dioxide layer, the fourth silicon dioxide layer and the upper surface of the N-type injection region, and one end, close to the middle of the device, of the metal layer is connected with the second silicon dioxide layer.
Furthermore, the upper surface of the N-type implantation region is flush with the upper convex surface of the P-type ion implantation region, and the upper surface of the second silicon dioxide layer (and the upper surface of the third silicon dioxide layer) is flush.
Furthermore, the junction depth of the P-type ion implantation area is smaller than the depth of the silicon dioxide layer IV.
Furthermore, the depth of the fourth silicon dioxide layer is 0.5-5um, and the width of the fourth silicon dioxide layer is 0.3-1 um.
Furthermore, the total width of the upper surface of the P-type ion implantation area is 1-3 um.
Another objective of the present application is to provide a method for manufacturing the low-capacitance electrostatic protection chip device, including the following steps:
(1) preparing a silicon oxide layer on the surface of the N-type silicon substrate by adopting a thermal oxidation method, wherein the thermal oxidation temperature is 900-;
(2) forming a groove by dry etching;
(3) filling silicon dioxide in the groove prepared in the step (2) by adopting a low-pressure chemical vapor deposition method;
(4) using the photoresist as a mask, and removing the silicon dioxide layer between the two grooves by anisotropic etching, wherein the main etching gas is F-based gas;
(5) injecting P-type ions into the region where the silicon dioxide layer is removed in the step (4) to form a P-type ion injection region;
(6) performing thermal diffusion to form junction depth in the P-type ion implantation region after thermal process;
(7) firstly, preparing a silicon dioxide layer by adopting a low-pressure chemical vapor deposition method, wherein the growth thickness of the silicon dioxide layer is 2000-;
(8) implanting oxygen ions under the N-type implantation region with an implantation energy of 300-1000KeV and an implantation concentration of 1E17/cm or more to form an oxygen ion implantation region2；
(9) Performing thermal annealing to form a silicon dioxide layer under the N-type injection region, wherein the annealing temperature is 1000-1200 ℃, and the annealing time is 30-300 s;
(10) and preparing a front metal layer to obtain the low-capacitance electrostatic protection chip device, wherein the front metal layer is made of aluminum-silicon-copper alloy and has the thickness of 0.5-5 um.
Further, the dry etching in the step (2) is anisotropic etching, and the etching is divided into two steps, wherein in the first step, the silicon dioxide layer is etched by adopting F-based gas, and in the second step, the silicon substrate is etched by adopting Cl-based or Br-based gas.
Further, the P-type ions implanted in the step (5) are boron, the implantation energy is 30-300KeV, and the implantation dose is 1E13-5E14/cm2。
Further, the heat diffusion in the step (6) is performed in N2The diffusion is carried out in the atmosphere at 1050-.
Further, in the step (7), the anisotropic etching main etching gas is F-based gas, the implanted N-type ions are phosphorus or arsenic, and the implantation dosage is 1E15-1E16/cm2And the implantation energy is 50-200 KeV.
Compared with the prior art, the invention has the beneficial effects that:
in the invention, the breakdown voltage can be adjusted by simply controlling the junction depth and the distance of the N-type injection region in the Si body of the N/P interface of the low-capacitance electrostatic protection chip device, the process is simple, the manufacturing cost is reduced, the injection and thermal diffusion processes reduce the interface defects, the leakage current is reduced, and the device performance is improved; meanwhile, the two layers of the P-type injection region and the N-type injection region are in direct contact with the isolation groove, and the bottom of the PN junction is isolated by the silicon dioxide layer, so that the area of the PN junction is reduced, the parasitic capacitance is reduced, the switching speed of a device is increased, and the device is more suitable for being applied in a high-frequency environment.
Drawings
Fig. 1 is a schematic structural diagram of a current protection chip;
FIG. 2 is an equivalent circuit diagram of a low capacitance ESD chip device shown in example 1;
FIG. 3 is a view showing a low capacitance electrostatic discharge protection chip device according to embodiment 1;
FIG. 4 is a schematic diagram of the preparation of step (1) in example 2;
FIG. 5 is a schematic view of the preparation of step (2) in example 2;
FIG. 6 is a schematic view of the preparation of step (3) in example 2;
FIG. 7 is a schematic view of the preparation of step (4) in example 2;
FIG. 8 is a schematic view of the preparation of step (5) in example 2;
FIG. 9 is a schematic view of the preparation of step (6) in example 2;
FIG. 10 is a schematic view of the preparation of step (7) in example 2;
FIG. 11 is a schematic view of the preparation of step (8) in example 2;
FIG. 12 is a schematic view of the preparation of step (9) in example 2.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
The embodiment provides a low-capacitance electrostatic protection chip device, an equivalent circuit diagram is shown as 2, and the structure of the device is shown as fig. 3. The low-capacitance electrostatic protection chip device comprises a silicon dioxide layer, an N-type substrate, a P-type ion implantation area, an N-type implantation area and a metal layer; the silicon dioxide layers are distributed discontinuously and comprise a first silicon dioxide layer, a second silicon dioxide layer, a third silicon dioxide layer and a fourth silicon dioxide layer, the N-type substrate is arranged at the bottom of the device, the P-type ion implantation area is convex and is positioned in the middle of the device, the second silicon dioxide layer is positioned on the upper convex surface of the P-type ion implantation area, the first silicon dioxide layer is positioned on the upper concave surface of the P-type ion implantation area, the N-type injection region is positioned on the upper surface of the silicon dioxide layer A, the silicon dioxide layer B is positioned on the outer sides of two ends of the P-type ion injection region, a third silicon dioxide layer is distributed at the upper end of the fourth silicon dioxide layer and on one side far away from the P-type ion implantation area, the metal layer is symmetrically distributed on the upper surface of the device, the lower surface of the metal layer is connected with the third silicon dioxide layer, the fourth silicon dioxide layer and the upper surface of the N-type injection region, and one end, close to the middle of the device, of the metal layer is connected with the second silicon dioxide layer.
Particularly, the upper surface of the N-type injection region is flush with the upper convex surface of the P-type ion injection region, and the upper surfaces of the second silicon dioxide layer and the third silicon dioxide layer are flush.
Particularly, the junction depth of the P-type ion implantation area is less than that of the fourth silicon dioxide layer, the depth of the fourth silicon dioxide layer is 0.5-5um, the width of the fourth silicon dioxide layer is 0.3-1um, and the total width of the upper surface of the P-type ion implantation area is 1-3 um.
Example 2
A preparation method of a low-capacitance electrostatic protection chip device specifically comprises the following steps:
(1) preparing a silicon oxide layer on the surface of the N-type silicon substrate by adopting a thermal oxidation method, wherein the thermal oxidation temperature is 900-;
(2) forming a groove by adopting anisotropic etching, wherein the etching is mainly divided into two steps, the first step adopts carbon tetrafluoride gas to etch a silicon dioxide layer, and the second step adopts chlorine gas to etch a silicon substrate; the depth of the groove is 0.5-5um, and the width of the groove is 0.3-1 um;
(3) filling silicon dioxide in the groove prepared in the step (2) by adopting a low-pressure chemical vapor deposition method, wherein the filling thickness is approximately equal to the width of the groove, so that the groove is completely filled, the deposition temperature is 600-;
(4) the photoresist is used as a mask, the silicon dioxide layer between the two grooves is removed by anisotropic etching, and the main etching gas is carbon tetrafluoride, so that the Si material below is not damaged;
(5) implanting boron into the region where the silicon dioxide layer is removed in the step (4) to form a P-type ion implantation region, wherein the implantation energy is 30-300KeV, and the implantation dose is 1E13-5E14/cm2；
(6) Performing thermal diffusion to form junction depth in the P-type ion implantation region after thermal process, wherein the thermal diffusion is performed in N2The diffusion is carried out in the atmosphere, the diffusion temperature is 1050-;
(7) firstly, preparing a silicon dioxide layer by adopting a low-pressure chemical vapor deposition method, wherein the deposition temperature is 600-; then, an N-type injection window is manufactured by utilizing an anisotropic etching method, then, element phosphorus is injected to form an N-type ion injection area, the main etching gas of the anisotropic etching is carbon tetrafluoride, and the injection dosage is 1E15-1E16/cm2The implantation energy is 50-200 KeV;
(8) implanting oxygen ions under the N-type implantation region with an implantation energy of 300-1000KeV and an implantation concentration of 1E17/cm or more to form an oxygen ion implantation region2；
(9) Performing thermal annealing to form a silicon dioxide layer under the N-type injection region, wherein the annealing temperature is 1000-1200 ℃, and the annealing time is 30-300 s;
(10) and preparing a front metal layer to obtain the low-capacitance electrostatic protection chip device, wherein the front metal layer is made of aluminum-silicon-copper alloy and has the thickness of 0.5-5 um.
Example 3
A preparation method of a low-capacitance electrostatic protection chip device specifically comprises the following steps:
(1) preparing a silicon oxide layer on the surface of the N-type silicon substrate by adopting a thermal oxidation method, wherein the thermal oxidation temperature is 900-;
(2) forming a groove by adopting anisotropic etching, wherein the etching is mainly divided into two steps, the first step adopts nitrogen trifluoride gas to etch a silicon dioxide layer, and the second step adopts hydrogen bromide gas to etch a silicon substrate; the depth of the groove is 0.5-5um, and the width of the groove is 0.3-1 um;
(3) filling silicon dioxide in the groove prepared in the step (2) by adopting a low-pressure chemical vapor deposition method, wherein the filling thickness is approximately equal to the width of the groove, so that the groove is completely filled, the deposition temperature is 600-;
(4) the photoresist is used as a mask, the silicon dioxide layer between the two grooves is removed by anisotropic etching, and the main etching gas is nitrogen trifluoride, so that the Si material below is not damaged;
(5) implanting boron into the region where the silicon dioxide layer is removed in the step (4) to form a P-type ion implantation region, wherein the implantation energy is 30-300KeV, and the implantation dose is 1E13-5E14/cm2；
(6) Performing thermal diffusion to form junction depth in the P-type ion implantation region after thermal process, wherein the thermal diffusion is performed in N2The diffusion is carried out in the atmosphere, the diffusion temperature is 1050-;
(7) firstly, preparing a silicon dioxide layer by adopting a low-pressure chemical vapor deposition method, wherein the deposition temperature is 600-2The implantation energy is 50-200 KeV;
(8) implanting oxygen ions under the N-type implantation region with an implantation energy of 300-1000KeV and an implantation concentration of 1E17/cm or more to form an oxygen ion implantation region2；
(9) Performing thermal annealing to form a silicon dioxide layer under the N-type injection region, wherein the annealing temperature is 1000-1200 ℃, and the annealing time is 30-300 s;
(10) and preparing a front metal layer to obtain the low-capacitance electrostatic protection chip device, wherein the front metal layer is made of aluminum-silicon-copper alloy and has the thickness of 0.5-5 um.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
Claims (10)
1. A low-capacitance electrostatic protection chip device is characterized by comprising a silicon dioxide layer, an N-type substrate, a P-type ion implantation area, an N-type implantation area and a metal layer; the silicon dioxide layers are distributed discontinuously and comprise a first silicon dioxide layer, a second silicon dioxide layer, a third silicon dioxide layer and a fourth silicon dioxide layer, the N-type substrate is arranged at the bottom of the device, the P-type ion implantation area is convex and is positioned in the middle of the device, the second silicon dioxide layer is positioned on the upper convex surface of the P-type ion implantation area, the first silicon dioxide layer is positioned on the upper concave surface of the P-type ion implantation area, the N-type injection region is positioned on the upper surface of the silicon dioxide layer A, the silicon dioxide layer B is positioned on the outer sides of two ends of the P-type ion injection region, a third silicon dioxide layer is distributed at the upper end of the fourth silicon dioxide layer and on one side far away from the P-type ion implantation area, the metal layer is symmetrically distributed on the upper surface of the device, the lower surface of the metal layer is connected with the third silicon dioxide layer, the fourth silicon dioxide layer and the upper surface of the N-type injection region, and one end, close to the middle of the device, of the metal layer is connected with the second silicon dioxide layer.
2. The device as claimed in claim 1, wherein the upper surface of the N-type implanted region is flush with the upper convex surface of the P-type ion implanted region, and the upper surfaces of the second and third silicon dioxide layers are flush.
3. The device of claim 1, wherein the junction depth of the P-type ion implantation region is less than the depth of the fourth silicon dioxide layer.
4. The device of claim 1, wherein the silicon dioxide layer four has a depth of 0.5-5um and a width of 0.3-1 um.
5. The device of claim 1, wherein the total width of the upper surface of the P-type ion implantation region is 1-3 um.
6. A method for preparing the low-capacitance electrostatic protection chip device of any one of claims 1 to 5, comprising the following steps:
(1) preparing a silicon oxide layer on the surface of the N-type silicon substrate by adopting a thermal oxidation method, wherein the thermal oxidation temperature is 900-;
(2) forming a groove by dry etching;
(3) filling silicon dioxide in the groove prepared in the step (2) by adopting a low-pressure chemical vapor deposition method;
(4) using the photoresist as a mask, and removing the silicon dioxide layer between the two grooves by anisotropic etching;
(5) injecting P-type ions into the region where the silicon dioxide layer is removed in the step (4) to form a P-type ion injection region;
(6) performing thermal diffusion to form junction depth in the P-type ion implantation region after thermal process;
(7) firstly, preparing a silicon dioxide layer by adopting a low-pressure chemical vapor deposition method, wherein the growth thickness of the silicon dioxide layer is 2000-;
(8) implanting oxygen ions under the N-type implantation region with an implantation energy of 300-1000KeV and an implantation concentration of 1E17/cm or more to form an oxygen ion implantation region2；
(9) Performing thermal annealing to form a silicon dioxide layer under the N-type injection region, wherein the annealing temperature is 1000-1200 ℃, and the annealing time is 30-300 s;
(10) and preparing a front metal layer to obtain the low-capacitance electrostatic protection chip device, wherein the front metal layer is made of aluminum-silicon-copper alloy and has the thickness of 0.5-5 um.
7. The production method according to claim 6, wherein the dry etching in the step (2) is anisotropic etching, and the etching is performed in two steps, wherein in the first step, the silicon dioxide layer is etched by using F-based gas, and in the second step, the silicon substrate is etched by using Cl-based or Br-based gas.
8. The method of claim 6, wherein the P-type ions implanted in step (5) are boron, the implantation energy is 30-300KeV, and the implantation dose is 1E13-5E14/cm2。
9. The method according to claim 6, wherein the thermal diffusion in N in step (6)2The diffusion is carried out in the atmosphere, the diffusion temperature is 1050-.
10. The manufacturing method according to claim 6, wherein the anisotropic etching main etching gas in the step (7) is an F-based gas, the implanted N-type ions are phosphorus or arsenic, and the implantation dose is 1E15-1E16/cm2And the implantation energy is 50-200 KeV.
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| EP0622850B1 (en) * | 1993-04-30 | 1999-04-21 | International Business Machines Corporation | Process for making an electrostatic discharge protect diode for silicon-on-insulator technology |
| US9305916B1 (en) * | 2014-12-30 | 2016-04-05 | Hong Kong Applied Science and Technology Research Institute Company, Limited | ESD power clamp for silicon-on-insulator (SOI) and FinFET processes lacking parasitic ESD diode |
| CN108933130A (en) * | 2017-05-23 | 2018-12-04 | 恩智浦美国有限公司 | Suitable for static discharge（ESD）The semiconductor device of protection |
| CN109309008A (en) * | 2018-10-26 | 2019-02-05 | 深圳市鹏朗贸易有限责任公司 | A kind of power device and preparation method thereof |
| CN111584480A (en) * | 2020-04-17 | 2020-08-25 | 深圳方正微电子有限公司 | Semiconductor device and method for manufacturing the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113937098A (en) * | 2021-09-22 | 2022-01-14 | 深圳市金誉半导体股份有限公司 | Electrostatic protection chip for rapid charging management system and preparation method thereof |
| CN113937098B (en) * | 2021-09-22 | 2023-03-24 | 深圳市金誉半导体股份有限公司 | Electrostatic protection chip for rapid charging management system and preparation method thereof |
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| CN112054020B (en) | 2021-06-01 |
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Denomination of invention: A low-capacitance electrostatic protection chip device and preparation method thereof Effective date of registration: 20220729 Granted publication date: 20210601 Pledgee: Shenzhen small and medium sized small loan Co.,Ltd. Pledgor: Shenzhen Jinyu Semiconductor Co.,Ltd. Registration number: Y2022440020147 |