CN109192724B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN109192724B CN109192724B CN201811085662.8A CN201811085662A CN109192724B CN 109192724 B CN109192724 B CN 109192724B CN 201811085662 A CN201811085662 A CN 201811085662A CN 109192724 B CN109192724 B CN 109192724B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 28
- 239000002184 metal Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000001312 dry etching Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 230000007547 defect Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 320
- 238000005530 etching Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000000927 vapour-phase epitaxy Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000003749 cleanliness Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004943 liquid phase epitaxy Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000000348 solid-phase epitaxy Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: a substrate of a first conductivity type; a first epitaxial layer of a first conductivity type formed on an upper surface of the substrate; a second epitaxial layer of the first conductivity type formed on a portion of an upper surface of the first epitaxial layer; a third epitaxial layer of the second conductivity type formed on an upper surface of the second epitaxial layer; a fourth epitaxial layer of the first conductivity type formed on the upper surface of the third epitaxial layer; a first dielectric layer; a first doped region of a second conductivity type; the fifth epitaxial layer of the first conductivity type is formed on the upper surface of the first doped region; a second dielectric layer; a front metal layer electrically connected to the fourth epitaxial layer and the fifth epitaxial layer; a back side metal layer electrically connected to the substrate. The semiconductor device has the characteristics of two-way, low capacitance and less defects.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
Electrostatic discharge (ESD) and other transient voltages that occur randomly in the form of voltage surges are commonly found in a variety of electronic devices. As semiconductor devices increasingly tend to be miniaturized, high density, and multifunctional, electronic devices are increasingly susceptible to voltage surges, even fatal damage. Transient current spikes can be induced from electrostatic discharge to various voltage surges such as lightning. Traditional surge protection product is through setting up the slot in order to obtain bigger effective junction area, and the electric capacity is usually at tens, even hundreds pF, and the attenuation to high frequency signal is very big, can not satisfy present information transmission demand, and produces the defect easily, and manufacturing cost is higher.
Disclosure of Invention
The technical problem to be solved by the invention is how to provide a semiconductor device with low capacitance, small defects and low manufacturing cost and a manufacturing method thereof.
In order to solve the above problems, the present invention provides a semiconductor device comprising: first, the
A substrate of a conductivity type;
a first epitaxial layer of a first conductivity type formed on an upper surface of the substrate;
the second epitaxial layer of the first conductivity type is formed on part of the upper surface of the first epitaxial layer and comprises a first sub-epitaxial layer and a second sub-epitaxial layer;
the third epitaxial layer of the second conduction type comprises a third sub-epitaxial layer formed on the upper surface of the first sub-epitaxial layer and a fourth sub-epitaxial layer formed on the upper surface of the second sub-epitaxial layer;
a fourth epitaxial layer of the first conductivity type, including a fifth sub-epitaxial layer formed on the upper surface of the third sub-epitaxial layer and a sixth sub-epitaxial layer formed on the upper surface of the fourth sub-epitaxial layer;
the first dielectric layer covers the side surfaces of the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer and the upper surface of the fourth epitaxial layer;
a first doped region of a second conductivity type extending downward from an upper surface of the first epitaxial layer between the first sub-epitaxial layer and the second sub-epitaxial layer;
the fifth epitaxial layer of the first conductivity type is formed on the upper surface of the first doped region;
the second dielectric layer covers the upper surface of the fifth epitaxial layer;
the front metal layer comprises a first sub-metal layer electrically connected with the fourth epitaxial layer and a second sub-metal layer electrically connected with the fifth epitaxial layer;
and the back metal layer is electrically connected with the lower surface of the substrate.
The semiconductor device has a structure that three groups of diodes are connected in parallel, so that the parasitic capacitance of the semiconductor device in a high-frequency circuit is greatly reduced; three groups of diodes connected in parallel are formed by forming the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer and the fifth epitaxial layer, so that the semiconductor device has fewer defects, small leakage current and low manufacturing cost. Thus, the performance and reliability of the semiconductor device are improved.
Further, the semiconductor device further includes:
and the contact holes comprise a first contact hole which is formed in the first dielectric layer and is used for filling the first sub-metal layer and a second contact hole which is formed in the second dielectric layer and is used for filling the second sub-metal layer.
Further, the semiconductor device further includes:
and the second doped region of the first conductivity type comprises a first sub-doped region extending downwards from the upper surface of the fourth epitaxial layer and a second sub-doped region extending downwards from the upper surface of the fifth epitaxial layer.
Further, the second doping region is aligned with the contact hole to form an ohmic contact to reduce on-resistance.
Furthermore, the first dielectric layer and the second dielectric layer are made of silicon oxide.
Further, the doping concentration of the first epitaxial layer is smaller than that of the substrate, so that the conductivity of the first epitaxial layer is inferior to that of the substrate.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
step S10: providing a substrate of a first conductive type, and forming a first epitaxial layer of the first conductive type on the upper surface of the substrate;
step S20: forming a second epitaxial layer of the first conductivity type on part of the upper surface of the first epitaxial layer, wherein the second epitaxial layer comprises a first sub-epitaxial layer and a second sub-epitaxial layer; forming a third epitaxial layer of the second conductivity type on the upper surface of the second epitaxial layer, wherein the third epitaxial layer comprises a third sub-epitaxial layer formed on the upper surface of the first sub-epitaxial layer and a fourth sub-epitaxial layer formed on the upper surface of the second sub-epitaxial layer; forming a fourth epitaxial layer of the first conductivity type on the upper surface of the third epitaxial layer, wherein the fourth epitaxial layer comprises a fifth sub-epitaxial layer formed on the upper surface of the third sub-epitaxial layer and a sixth sub-epitaxial layer formed on the upper surface of the fourth sub-epitaxial layer;
step S30: forming a first dielectric layer covering the side surfaces of the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer and the upper surface of the fourth epitaxial layer;
step S40: a first doping region of a second conduction type is formed by extending downwards from the upper surface of the first epitaxial layer between the first sub-epitaxial layer and the second sub-epitaxial layer;
step S50: forming a fifth epitaxial layer of the first conductivity type on the upper surface of the first doped region;
step S60: forming a second dielectric layer covering the upper surface of the fifth epitaxial layer;
step S70: forming a front metal layer, wherein the front metal layer comprises a first sub-metal layer electrically connected with the fourth epitaxial layer and a second sub-metal layer electrically connected with the fifth epitaxial layer; and forming a back metal layer which is electrically connected with the lower surface of the substrate.
The semiconductor device has a structure that three groups of diodes are connected in parallel, so that the parasitic capacitance of the semiconductor device in a high-frequency circuit is greatly reduced; three groups of diodes connected in parallel are formed by forming the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer and the fifth epitaxial layer, so that the semiconductor device has fewer defects, small leakage current and low manufacturing cost. Thus, the performance and reliability of the semiconductor device are improved.
Further, after step S60, the method further includes the following steps:
step S61: and forming contact holes, wherein the contact holes comprise a first contact hole formed in the first medium layer and used for filling the first sub-metal layer and a second contact hole formed in the second medium layer and used for filling the second sub-metal layer.
Further, after step S61, the method further includes the following steps:
step S62: and forming a second doped region of the first conductivity type, wherein the second doped region comprises a first sub-doped region extending downwards from the upper surface of the fourth epitaxial layer and a second sub-doped region extending downwards from the upper surface of the fifth epitaxial layer.
Further, in step S61, the contact hole is formed by dry etching.
Drawings
The invention is further illustrated with reference to the following figures and examples.
Fig. 1 is a schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 is an equivalent circuit diagram of the semiconductor device of fig. 1;
FIG. 3 is a schematic flow chart of a method of manufacturing the semiconductor device of FIG. 1;
fig. 4 to 14 are detailed process diagrams of a method of manufacturing the semiconductor device of fig. 1.
In the figure: 1. a substrate; 2. a first epitaxial layer; 3. a second epitaxial layer; 3a, a first sub-epitaxial layer; 3b, a second sub-epitaxial layer; 4. a third epitaxial layer; 4a, a third sub-epitaxial layer; 4b, a fourth sub-epitaxial layer; 5. a fourth epitaxial layer; 5a, a fifth sub-epitaxial layer; 5b, a sixth sub-epitaxial layer; 6. a first dielectric layer; 7. a first doped region; 8. a fifth epitaxial layer; 9. a second dielectric layer; 10. a front metal layer; 10a, a first sub-metal layer; 10b, a second sub-metal layer; 11. a back metal layer; 12. a contact hole; 12a, a first sub-contact hole; 12b, a second sub-contact hole; 13. a second doped region; 13a, a first sub-doping region; 13b, a second sub-doping area; A. a first branch; a1, a first diode; a2, a second diode; B. a second branch circuit; b1, a third diode; b2, a fourth diode; C. a third branch; c1, a fifth diode; c2, sixth diode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and clearly apparent, the technical solutions in the embodiments of the present invention will be described below in detail and completely with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The technical solution of the present invention is further specifically described below with reference to the accompanying drawings and examples.
Referring to fig. 1, a semiconductor device 100 includes:
a substrate 1 of a first conductivity type;
a first epitaxial layer 2 of a first conductivity type formed on an upper surface of the substrate 1;
a second epitaxial layer 3 of the first conductivity type formed on a portion of the upper surface of the first epitaxial layer 2, including a first sub-epitaxial layer 3a and a second sub-epitaxial layer 3 b;
a third epitaxial layer 4 of the second conductivity type, including a third sub-epitaxial layer 4a formed on the upper surface of the first sub-epitaxial layer 3a and a fourth sub-epitaxial layer 4b formed on the upper surface of the second sub-epitaxial layer 3 b;
a fourth epitaxial layer 5 of the first conductivity type, including a fifth sub-epitaxial layer 5a formed on the upper surface of the third sub-epitaxial layer 4a and a sixth sub-epitaxial layer 5b formed on the upper surface of the fourth sub-epitaxial layer 4 b;
a first dielectric layer 6 covering side surfaces of the second epitaxial layer 3, the third epitaxial layer 4 and the fourth epitaxial layer 5 and an upper surface of the fourth epitaxial layer 5;
a first doped region 7 of the second conductivity type extending downward from the upper surface of the first epitaxial layer 2 between the first sub-epitaxial layer 3a and the second sub-epitaxial layer 3 b;
a fifth epitaxial layer 8 of the first conductivity type formed on the upper surface of the first doped region 7;
the second medium layer 9 covers the upper surface of the fifth epitaxial layer 8;
a front metal layer 10 including a first sub-metal layer 10a electrically connected to the fourth epitaxial layer 5 and a second sub-metal layer 10b electrically connected to the fifth epitaxial layer 8;
and a back metal layer 11 electrically connected to the lower surface of the substrate 1.
The semiconductor device 100 has a structure in which three groups of diodes are connected in parallel, so that the parasitic capacitance of the semiconductor device in a high-frequency circuit is greatly reduced; three groups of diodes connected in parallel are formed by forming the second epitaxial layer 3, the third epitaxial layer 4, the fourth epitaxial layer 5 and the fifth epitaxial layer 8, so that the semiconductor device 100 has fewer defects, small leakage current and low manufacturing cost. Thus, the performance and reliability of the semiconductor device 100 are improved.
Specifically, the substrate 1 is a carrier in an integrated circuit, the substrate 1 plays a role of support, and the substrate 1 also participates in the operation of the integrated circuit. In the present embodiment, the substrate 1 is a silicon substrate, so that the cost can be reduced, the large size can be ensured, and the substrate has the characteristics of conductivity, and can avoid the edge effect and greatly improve the yield.
The first dielectric layer 6 and the second dielectric layer 9 may be made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the first dielectric layer 6 and the second dielectric layer 9 are made of silicon oxide, and serve as a final interlayer insulating layer of the semiconductor device 100 to isolate current.
The doping concentration of the first epitaxial layer 2 is different from the doping concentration of the substrate 1, i.e. the doping concentration of the first epitaxial layer 2 may be greater than, less than or equal to the doping concentration of the substrate 1. In this embodiment, the doping concentration of the first epitaxial layer 2 is less than that of the substrate 1, so that the resistivity of the first epitaxial layer 2 is greater than that of the substrate 1, and the conductivity of the first epitaxial layer 2 is lower than that of the substrate 1.
The semiconductor device 100 further includes a contact hole 12 and a second doped region 13 of the first conductivity type.
The contact holes 12 include a first contact hole 12a formed in the first dielectric layer 6 for filling the first sub-metal layer 10a and a second contact hole 12b formed in the second dielectric layer 9 for filling the second sub-metal layer 10 b.
The second doped region 13 includes a first sub-doped region 13a extending downward from the upper surface of the fourth epitaxial layer 5 and a second sub-doped region 13b extending downward from the upper surface of the fifth epitaxial layer 8. In this embodiment, the second doping region 13 is aligned with the contact hole 12 to form an ohmic contact to reduce the on-resistance.
The first conductive type can be N-type doped, and correspondingly, the second conductive type is P-type doped; conversely, the first conductivity type may also be P-type doped, and correspondingly, the second conductivity type is N-type doped. In this embodiment, the first conductivity type is P-type doping, the second conductivity type is N-type doping, the first conductivity type substrate 1 is a P-type substrate 1, the first conductivity type epitaxial layer 2 grown on the upper surface of the first conductivity type substrate 1 is a P-type first epitaxial layer 2, the first conductivity type second epitaxial layer 3 is a P-type second epitaxial layer 3, and so on. In theory, both a P-type substrate and an N-type substrate are feasible, but in production, the cost of performing N-type diffusion on the P-type substrate is lower than that of performing P-type diffusion on the N-type substrate, the production speed is higher, the P-type substrate can play a role in protection, has higher internal resistance, can prevent the conduction of a PN junction, can be started by positive voltage, and is more convenient to use. Therefore, in the following embodiments, the first conductive type is P-type doped, and the second conductive type is N-type doped, but the description is not limited thereto.
Referring to fig. 2, an equivalent circuit diagram of the semiconductor device 100 is shown: when electricity is applied to the front metal layer 10 and the back metal layer 11, the current flows from the front metal layer 10 to the back metal layer 11. Note that, the forward direction and the reverse direction of the PN junction formed below are determined by setting the first conductivity type to be P-type and setting the second conductivity type to be N-type, which is an embodiment of the present invention, but the present invention is not limited thereto. The current sequentially passes through the first sub-metal layer 10a, the first sub-doping region 13a, the fifth sub-epitaxial layer 5a, the third sub-epitaxial layer 4a, the first sub-epitaxial layer 3a, the first epitaxial layer 2, the substrate 1 and the back metal layer 11 to form a first branch circuit a. In the first branch a, the fifth sub-epitaxial layer 5a and the third sub-epitaxial layer 4a form a forward PN junction, that is, a forward first diode a1 is formed; the third sub-epitaxial layer 4a forms an inverted PN junction with the first sub-epitaxial layer 3a, i.e., forms an inverted second diode a 2. The current sequentially passes through the second sub-metal layer 10B, the second sub-doping region 13B, the fifth epitaxial layer 8, the first doping region 7, the first epitaxial layer 2, the substrate 1 and the back metal layer 11 to form a second branch circuit B. In the second branch B, the fifth epitaxial layer 8 and the first doped region 7 form a forward PN junction, that is, a forward third diode B1 is formed; the first doped region 7 forms an inverted PN junction with the first epitaxial layer 2, i.e., an inverted fourth diode B2. The current sequentially passes through the first sub-metal layer 10a, the first sub-doping region 13a, the sixth sub-epitaxial layer 5b, the fourth sub-epitaxial layer 4b, the second sub-epitaxial layer 3b, the first epitaxial layer 2, the substrate 1 and the back metal layer 11 to form a third branch C. In the third branch C, the sixth sub-epitaxial layer 5b and the fourth sub-epitaxial layer 4b form a forward PN junction, that is, a forward fifth diode C1 is formed; the fourth sub-epitaxial layer 4b forms an inverted PN junction with the second sub-epitaxial layer 3b, i.e., an inverted sixth diode C2 is formed. In summary, the semiconductor device 100 to be protected in the present invention forms an equivalent circuit with three groups of diodes connected in parallel, thereby achieving bidirectional protection and reducing its own parasitic capacitance in a high frequency circuit.
A method of manufacturing the semiconductor device 100 of fig. 1, comprising the steps of:
step S10: providing a substrate 1 of a first conductive type, and forming a first epitaxial layer 2 of the first conductive type on the upper surface of the substrate 1;
step S20: forming a second epitaxial layer 3 of the first conductivity type on a part of the upper surface of the first epitaxial layer 2, wherein the second epitaxial layer 3 comprises a first sub-epitaxial layer 3a and a second sub-epitaxial layer 3 b; forming a third epitaxial layer 4 of the second conductivity type on the upper surface of the second epitaxial layer 2, wherein the third epitaxial layer 4 comprises a third sub-epitaxial layer 4a formed on the upper surface of the first sub-epitaxial layer 3a and a fourth sub-epitaxial layer 4b formed on the upper surface of the second sub-epitaxial layer 3 b; forming a fourth epitaxial layer 5 of the first conductivity type on the upper surface of the third epitaxial layer 4, wherein the fourth epitaxial layer 5 comprises a fifth sub-epitaxial layer 5a formed on the upper surface of the third sub-epitaxial layer 4a and a sixth sub-epitaxial layer 5b formed on the upper surface of the fourth sub-epitaxial layer 4 b;
step S30: forming a first dielectric layer 6 covering the side surfaces of the second epitaxial layer 3, the third epitaxial layer 4 and the fourth epitaxial layer 5 and the upper surface of the fourth epitaxial layer 5;
step S40: a first doping region 7 of the second conductivity type is formed by extending downwards from the upper surface of the first epitaxial layer 2 between the first sub-epitaxial layer 3a and the second sub-epitaxial layer 3 b;
step S50: forming a fifth epitaxial layer 8 of the first conductivity type on the upper surface of the first doped region 7;
step S60: forming a second dielectric layer 9 covering the upper surface of the fifth epitaxial layer 8;
step S70: forming a front metal layer 10, wherein the front metal layer 10 comprises a first sub-metal layer 10a electrically connected with the fourth epitaxial layer 5 and a second sub-metal layer 10b electrically connected with the fifth epitaxial layer 8; a back metal layer 11 is formed to be electrically connected to the lower surface of the substrate 1.
The semiconductor device 100 has a structure in which three groups of diodes are connected in parallel, so that the parasitic capacitance of the semiconductor device in a high-frequency circuit is greatly reduced; three groups of diodes connected in parallel are formed by forming the second epitaxial layer 3, the third epitaxial layer 4, the fourth epitaxial layer 5 and the fifth epitaxial layer 8, so that the semiconductor device 100 has fewer defects, small leakage current and low manufacturing cost. Thus, the performance and reliability of the semiconductor device 100 are improved.
Referring to fig. 3 and fig. 4 to 14, the method for manufacturing the semiconductor device 100 of fig. 1 includes the following steps:
step S10: a substrate 1 of a first conductivity type is provided, a first epitaxial layer 2 of the first conductivity type being formed on an upper surface of said substrate 1.
Specifically, referring to fig. 4, the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by vapor phase epitaxy, liquid phase epitaxy, solid phase epitaxy, molecular beam epitaxy or chemical vapor deposition. In the present embodiment, the first epitaxial layer 2 is formed on the upper surface of the substrate 1 by a vapor phase epitaxy process, so that the perfection of the silicon material can be improved, the defects can be reduced, and the leakage current of the storage unit can be reduced.
Step S20: forming a second epitaxial layer 3 of the first conductivity type on a part of the upper surface of the first epitaxial layer 2, wherein the second epitaxial layer 3 comprises a first sub-epitaxial layer 3a and a second sub-epitaxial layer 3 b; forming a third epitaxial layer 4 of the second conductivity type on the upper surface of the second epitaxial layer 2, wherein the third epitaxial layer 4 comprises a third sub-epitaxial layer 4a formed on the upper surface of the first sub-epitaxial layer 3a and a fourth sub-epitaxial layer 4b formed on the upper surface of the second sub-epitaxial layer 3 b; forming a fourth epitaxial layer 5 of the first conductivity type on the upper surface of the third epitaxial layer 4, wherein the fourth epitaxial layer 5 comprises a fifth sub-epitaxial layer 5a formed on the upper surface of the third sub-epitaxial layer 4a and a sixth sub-epitaxial layer 5b formed on the upper surface of the fourth sub-epitaxial layer 4 b;
specifically, referring to fig. 5, first, three complete epitaxial layers of the first conductivity type, the second conductivity type, and the first conductivity type are sequentially formed on the entire upper surface of the first epitaxial layer 2 from bottom to top. The three complete epitaxial layers may be formed by vapor phase epitaxy, liquid phase epitaxy, solid phase epitaxy, molecular beam epitaxy or chemical vapor deposition. In the present embodiment, the three complete epitaxial layers are formed by a vapor phase epitaxy process, so that the perfection of the silicon material can be improved, the defects can be reduced, and the leakage current of the storage unit can be reduced. Next, referring to fig. 6, a mask material is prepared on the upper surface of the uppermost epitaxial layer, where the mask material is specifically a first photoresist; forming the second epitaxial layer 3, the third epitaxial layer 4 and the fourth epitaxial layer 5 on the first photoresist layer by etching; and finally, removing the first photoresist. The etching method comprises dry etching and wet etching. The dry etching includes light volatilization, gas phase etching, plasma etching and the like. In the embodiment, the adopted etching method is dry etching, so that automation is easier to realize, no pollution is introduced in the treatment process, and the cleanliness is high.
Step S30: forming a first dielectric layer 6 covering the side surfaces of the second epitaxial layer 3, the third epitaxial layer 4 and the fourth epitaxial layer 5 and the upper surface of the fourth epitaxial layer 5;
first, referring to fig. 7, a first complete dielectric layer is formed on the side surfaces of the second epitaxial layer 3, the third epitaxial layer 4 and the fourth epitaxial layer 5, the upper surface of the fourth epitaxial layer 5 and the upper surface of the first epitaxial layer, specifically, the first complete dielectric layer may be made of silicon oxide, silicon nitride or silicon oxynitride, and may be formed by using a sputtering or thermal oxidation method or a chemical vapor deposition process. In this embodiment, the first complete dielectric layer is a silicon oxide layer formed by thermal oxidation. Next, referring to fig. 8, a mask material is prepared on the upper surface of the first complete dielectric layer, where the mask material is specifically a second photoresist; forming the first dielectric layer 6 on the second photoresist layer by etching; and finally, removing the second photoresist. The etching method comprises dry etching and wet etching. The dry etching includes light volatilization, gas phase etching, plasma etching and the like. In the embodiment, the adopted etching method is dry etching, so that automation is easier to realize, no pollution is introduced in the treatment process, and the cleanliness is high.
Step S40: a first doping region 7 of the second conductivity type is formed by extending downwards from the upper surface of the first epitaxial layer 2 between the first sub-epitaxial layer 3a and the second sub-epitaxial layer 3 b;
specifically, referring to fig. 9, the first doped region 7 may be formed by ion implantation or diffusion. In the present embodiment, the first doping region 7 is formed by ion implantation, so that the total dose, depth distribution and surface uniformity of impurities can be precisely controlled, re-diffusion of the original impurities can be prevented, and a self-aligned technique can be implemented to reduce a capacitance effect.
Step S50: forming a fifth epitaxial layer 8 of the first conductivity type on the upper surface of the first doped region 7;
specifically, referring to fig. 10, the fifth epitaxial layer 8 may be formed on the upper surface of the first doped region 7 by vapor phase epitaxy, liquid phase epitaxy, solid phase epitaxy, molecular beam epitaxy or chemical vapor deposition. In this embodiment, the fifth epitaxial layer is formed on the upper surface of the first doped region 7 by a vapor phase epitaxy process, so that the perfection of the silicon material can be improved, the defects can be reduced, and the leakage current of the memory cell can be reduced.
Step S60: a second dielectric layer 9 is formed covering the upper surface of the fifth epitaxial layer 8.
Specifically, referring to fig. 11, the material of the second dielectric layer 9 may be silicon oxide, silicon nitride, or silicon oxynitride, and the second dielectric layer 9 may be formed by sputtering, a thermal oxidation method, or a chemical vapor deposition process. In this embodiment, the second dielectric layer 9 is a silicon oxide layer formed by thermal oxidation, and functions to isolate current, and serves as a final interlayer insulating layer of the semiconductor device 100.
Step S61: forming contact holes 12, wherein the contact holes 12 comprise a first contact hole 12a formed in the first dielectric layer 6 for filling the first sub-metal layer 10a and a second contact hole 12b formed in the second dielectric layer 9 for filling the second sub-metal layer 10 b.
Specifically, referring to fig. 12, a mask material is prepared on the upper surfaces of the first dielectric layer 6 and the second dielectric layer 9, the mask material is specifically a third photoresist, the contact hole 12 is formed on the third photoresist layer by etching, and then the third photoresist is removed. The etching method comprises dry etching and wet etching. The dry etching includes light volatilization, gas phase etching, plasma etching and the like. In the embodiment, the adopted etching method is dry etching, so that automation is easier to realize, no pollution is introduced in the treatment process, and the cleanliness is high.
Step S62: forming a second doped region 13 of the first conductivity type, where the second doped region 13 includes a first sub-doped region 13a extending downward from the upper surface of the fourth epitaxial layer 5 and a second sub-doped region 13b extending downward from the upper surface of the fifth epitaxial layer 8.
Specifically, referring to fig. 13, the second doped region 13 may be formed by ion implantation or diffusion. In the present embodiment, the second doping region 13 is formed by ion implantation, so that the total dose, depth distribution and surface uniformity of the impurities can be precisely controlled, re-diffusion of the original impurities can be prevented, and a self-aligned technique can be implemented to reduce the capacitance effect.
Step S70: forming a front metal layer 10, wherein the front metal layer 10 comprises a first sub-metal layer 10a electrically connected with the fourth epitaxial layer 5 and a second sub-metal layer 10b electrically connected with the fifth epitaxial layer 8; a back metal layer 11 is formed to be electrically connected to the lower surface of the substrate 1. Please refer to fig. 14.
The semiconductor device 100 has a structure in which three groups of diodes are connected in parallel, so that the parasitic capacitance of the semiconductor device in a high-frequency circuit is greatly reduced; three groups of diodes connected in parallel are formed by forming the second epitaxial layer 3, the third epitaxial layer 4, the fourth epitaxial layer 5 and the fifth epitaxial layer 8, so that the semiconductor device 100 has fewer defects, small leakage current and low manufacturing cost. Thus, the performance and reliability of the semiconductor device 100 are improved.
The foregoing is merely exemplary and illustrative of the principles of the present invention and various modifications, additions and substitutions of the specific embodiments described herein may be made by those skilled in the art without departing from the principles of the present invention or exceeding the scope of the claims set forth herein.
Claims (10)
1. A semiconductor device, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a first conductivity type formed on an upper surface of the substrate;
the second epitaxial layer of the first conductivity type is formed on part of the upper surface of the first epitaxial layer and comprises a first sub-epitaxial layer and a second sub-epitaxial layer;
the third epitaxial layer of the second conduction type comprises a third sub-epitaxial layer formed on the upper surface of the first sub-epitaxial layer and a fourth sub-epitaxial layer formed on the upper surface of the second sub-epitaxial layer;
a fourth epitaxial layer of the first conductivity type, including a fifth sub-epitaxial layer formed on the upper surface of the third sub-epitaxial layer and a sixth sub-epitaxial layer formed on the upper surface of the fourth sub-epitaxial layer;
the first dielectric layer covers the side surfaces of the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer and the upper surface of the fourth epitaxial layer;
a first doped region of a second conductivity type extending downward from an upper surface of the first epitaxial layer between the first sub-epitaxial layer and the second sub-epitaxial layer;
the fifth epitaxial layer of the first conductivity type is formed on the upper surface of the first doped region;
the second dielectric layer covers the upper surface of the fifth epitaxial layer;
the front metal layer comprises a first sub-metal layer electrically connected with a fifth sub-epitaxial layer and a sixth sub-epitaxial layer of the fourth epitaxial layer and a second sub-metal layer electrically connected with the fifth epitaxial layer;
and the back metal layer is electrically connected with the lower surface of the substrate.
2. The semiconductor device according to claim 1, further comprising:
and the contact holes comprise a first contact hole which is formed in the first dielectric layer and is used for filling the first sub-metal layer and a second contact hole which is formed in the second dielectric layer and is used for filling the second sub-metal layer.
3. The semiconductor device according to claim 2, further comprising:
and the second doped region of the first conductivity type comprises a first sub-doped region extending downwards from the upper surface of the fourth epitaxial layer and a second sub-doped region extending downwards from the upper surface of the fifth epitaxial layer.
4. The semiconductor device of claim 3, wherein the second doped region is disposed in alignment with the contact hole.
5. The semiconductor device according to any one of claims 1 to 4, wherein the first dielectric layer and the second dielectric layer are made of silicon oxide.
6. The semiconductor device of claim 5, wherein a doping concentration of the first epitaxial layer is less than a doping concentration of the substrate.
7. A method of manufacturing a semiconductor device, comprising the steps of:
step S10: providing a substrate of a first conductive type, and forming a first epitaxial layer of the first conductive type on the upper surface of the substrate;
step S20: forming a second epitaxial layer of the first conductivity type on part of the upper surface of the first epitaxial layer, wherein the second epitaxial layer comprises a first sub-epitaxial layer and a second sub-epitaxial layer; forming a third epitaxial layer of a second conductivity type on the upper surface of the second epitaxial layer, wherein the third epitaxial layer comprises a third sub-epitaxial layer formed on the upper surface of the first sub-epitaxial layer and a fourth sub-epitaxial layer formed on the upper surface of the second sub-epitaxial layer; forming a fourth epitaxial layer of the first conductivity type on the upper surface of the third epitaxial layer, wherein the fourth epitaxial layer comprises a fifth sub-epitaxial layer formed on the upper surface of the third sub-epitaxial layer and a sixth sub-epitaxial layer formed on the upper surface of the fourth sub-epitaxial layer;
step S30: forming a first dielectric layer covering the side surfaces of the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer and the upper surface of the fourth epitaxial layer;
step S40: a first doping region of a second conduction type is formed by extending downwards from the upper surface of the first epitaxial layer between the first sub-epitaxial layer and the second sub-epitaxial layer;
step S50: forming a fifth epitaxial layer of the first conductivity type on the upper surface of the first doped region;
step S60: forming a second dielectric layer covering the upper surface of the fifth epitaxial layer;
step S70: forming a front metal layer, wherein the front metal layer comprises a first sub-metal layer electrically connected with a fifth sub-epitaxial layer and a sixth sub-epitaxial layer of the fourth epitaxial layer and a second sub-metal layer electrically connected with the fifth epitaxial layer; and forming a back metal layer which is electrically connected with the lower surface of the substrate.
8. The method for manufacturing a semiconductor device according to claim 7, further comprising, after the step S60, the steps of:
step S61: and forming contact holes, wherein the contact holes comprise a first contact hole formed in the first medium layer and used for filling the first sub-metal layer and a second contact hole formed in the second medium layer and used for filling the second sub-metal layer.
9. The method for manufacturing a semiconductor device according to claim 8, further comprising, after the step S61, the steps of:
step S62: and forming a second doped region of the first conductivity type, wherein the second doped region comprises a first sub-doped region extending downwards from the upper surface of the fourth epitaxial layer and a second sub-doped region extending downwards from the upper surface of the fifth epitaxial layer.
10. The method for manufacturing the semiconductor device according to claim 9, wherein in step S61, the contact hole is formed by dry etching.
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| US5892558A (en) * | 1997-06-26 | 1999-04-06 | Gl Displays, Inc. | Wire electrode structure based on 2 or 3 terminal device employed in a liquid crystal display |
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