CN114695557A - VDMOS device for lithium battery charging management and preparation method thereof - Google Patents
VDMOS device for lithium battery charging management and preparation method thereof Download PDFInfo
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- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 title claims abstract description 45
- 229910052744 lithium Inorganic materials 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000007726 management method Methods 0.000 title description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000002347 injection Methods 0.000 claims abstract description 62
- 239000007924 injection Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 210000000746 body region Anatomy 0.000 claims description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims description 22
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 description 12
- 238000002513 implantation Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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Abstract
The invention discloses a VDMOS device for lithium battery charging management, which comprises a substrate, a first epitaxial layer, a first groove extending from the first epitaxial layer to the substrate, a second epitaxial layer filled in the first groove, a second groove positioned between the first grooves and extending to the substrate, a first silicon oxide layer filled in the second groove, a second silicon oxide layer formed on the second groove and the first epitaxial layer, an opening positioned between the second silicon oxide layers and a polycrystalline silicon layer on the second silicon oxide layer, a body area between the second grooves, a first injection area positioned in the body area and connected with the second silicon oxide layer through the opening, a second injection area positioned between the first injection areas, a third injection area, a first metal layer, a second metal layer and a third metal layer, wherein the lower surface of the substrate extends to the first grooves and is connected with part of the second grooves. The invention also provides a preparation method of the VDMOS device for lithium battery charging management, which improves the over-temperature feedback rate and the working stability of the lithium battery charging management.
Description
Technical Field
The invention relates to the field of lithium battery charging management, in particular to a VDMOS (vertical double-diffused metal oxide semiconductor) device for lithium battery charging management and a preparation method thereof.
Background
With the development of science and technology, lithium batteries are widely used in the fields of life, military and the like because of their special charge-discharge characteristics. However, the lithium battery has certain limitations in use, for example, when charging, if the current is not limited, the battery is overheated or even explodes in the charging process, which greatly threatens the personal safety, and the charging temperature of the lithium battery is too high, which accelerates the reduction of the service life of the battery. Therefore, there is a need for effective thermal control and management of the charging of lithium batteries to avoid overheating of the lithium batteries. In the charging process, the lithium battery is heated and damaged due to the overhigh charging current, so that the overcurrent protection capability is also necessary for the lithium battery charging system.
For the reasons, a temperature sensor and an over-temperature circuit are required to be arranged in the lithium battery charging system, and the over-current protection circuit is used for detecting the temperature of the charging system, detecting the over-temperature and performing over-current protection. Temperature, current sensor can carry out real-time monitoring to the temperature of system, charging current to give protection circuit with information feedback, when the temperature of system is too high or the electric current is too big, protection circuit can in time carry out the shutoff operation to VDMOS, thereby prevents that the lithium cell from suffering the damage because overtemperature, overcurrent. Due to the fact that the charging current is too large when the temperature is too high, the working environment temperature and the charging current magnitude information of the device are difficult to extract, and the problem that the reliability of the system is reduced due to the fact that the over-temperature feedback speed is slow is caused.
Disclosure of Invention
In view of the above, the present invention provides a VDMOS integrated with a temperature sensor, and aims to accurately and timely extract temperature information of a working environment of a device, and when the temperature is too high, the device automatically cuts off a charging current, so that a lithium battery charging system can effectively protect a lithium battery and the charging system from being damaged by over-temperature. The novel device is used for a charging system, can reduce manufacturing cost, accelerates the over-temperature feedback speed and improves the reliability of the system, and is realized by adopting the following technical scheme.
In a first aspect, the present invention provides a VDMOS device for lithium battery charging management, including:
a substrate of a first conductivity type;
the structure comprises a first epitaxial layer of a first conductivity type formed on a substrate, first trenches arranged at intervals and extending from the upper surface of the first epitaxial layer to the substrate, second epitaxial layers of the first conductivity type filled in the first trenches, and second trenches located between the first trenches and extending to the substrate, wherein a first silicon oxide layer is filled in the second trenches, and the depth of the second trenches is greater than that of the first trenches;
second silicon dioxide layers which are formed on the second groove and the first epitaxial layer and are arranged at intervals, an opening positioned between the second silicon dioxide layers and a polycrystalline silicon layer formed on the second silicon dioxide layers;
the second conductive body region is formed between the second trenches, the first conductive first injection region is formed in the body region at intervals, located on the lower surface of the opening and connected with the second silicon oxide layer, the second conductive second injection region is located between the first injection regions, and the second conductive third injection region is formed on the lower surface of the substrate, extends to the first trenches and is connected with a part of the second trenches;
the first dielectric layer is formed on the first epitaxial layer and a part of the first groove, the second dielectric layer is formed on a part of the first groove and the polycrystalline silicon layer and is connected with the first injection region, the first contact hole is positioned between the first dielectric layer and the second dielectric layer, and the second contact hole penetrates through the second dielectric layer and is positioned in the opening and is connected with a part of the first injection region and the second injection region;
the first metal layer is formed on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, the second metal layer is formed on the lower surface of the substrate and is arranged corresponding to the third injection regions, and the third metal layer is formed on the lower surface of the substrate between the third injection regions.
In a second aspect, the invention further provides a preparation method of the VDMOS device for lithium battery charging management, including the following steps:
providing a substrate of a first conductive type, and forming a first epitaxial layer of the first conductive type on the substrate;
photoetching and forming first grooves which are arranged at intervals and extend from the upper surface of the first epitaxial layer into the substrate, filling first conductive type ions into the first grooves to form a second epitaxial layer, photoetching and forming second grooves which penetrate through the first epitaxial layer and extend into the substrate between the first grooves, and filling first silicon oxide layers into the second grooves, wherein the depth of the second grooves is greater than that of the first grooves;
forming second silicon dioxide layers arranged at intervals on the second groove and the first epitaxial layer, forming an opening between the second silicon dioxide layers, and forming a polycrystalline silicon layer on the second silicon dioxide layers;
forming a body region of a second conductivity type between the second trenches, forming first implanted regions of the first conductivity type which are arranged at intervals in the body region and located on the lower surface of the opening to be connected with the second silicon oxide layer, forming second implanted regions of the second conductivity type located between the first implanted regions, and forming third implanted regions of the second conductivity type which are connected with a part of the second trenches by extending the lower surface of the substrate to the first trenches;
forming a first dielectric layer on the first epitaxial layer and a part of the first trench, a second dielectric layer connected with the first injection region on the polycrystalline silicon layer, a first contact hole between the first dielectric layer and the second dielectric layer, and a second contact hole penetrating through the second dielectric layer and positioned in the opening and connected with a part of the first injection region and the second injection region;
and forming a first metal layer on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, forming a second metal layer on the lower surface of the substrate and corresponding to the third injection region, and forming a third metal layer on the lower surface of the substrate between the third injection regions.
Compared with the prior art, the VDMOS device for lithium battery charging management and the preparation method thereof provided by the invention have the following beneficial effects:
the method comprises the steps that a first epitaxial layer with the same conductivity type as a substrate is formed on the substrate, first grooves which are arranged at intervals are formed in the first epitaxial layer in a mode of extending from the upper surface of the first epitaxial layer to the substrate, high-resistance epitaxy is filled in the first grooves to form a second epitaxial layer, second grooves are formed between the first grooves, and a first silicon oxide layer is filled in the second grooves to serve as isolation grooves to form a plurality of current paths. The second silicon dioxide layer is formed on the second groove and the first epitaxial layer, the polycrystalline silicon layer is formed on the second silicon dioxide layer, the body region is formed in the first epitaxial layer in an ion implantation mode, the first injection region and the second injection region are formed, ion implantation is carried out in the substrate to form a third injection region connected with the bottoms of the first groove and the second groove, a second metal layer corresponding to the third injection region is used for outputting over-temperature and over-current detection signals in a circuit, namely, the over-temperature and over-current detection module is integrated into a device, the accurate and timely extraction of the working environment temperature of the device can be realized, the manufacturing cost is reduced, the risk that the lithium battery is prevented from being damaged due to over-temperature can be reduced, when the temperature is too high, the charging current of the device is automatically cut off, the over-temperature feedback rate is improved, and the working stability of lithium battery charging management is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a flowchart of a VDMOS device manufacturing method for lithium battery charging management according to an embodiment of the present invention;
fig. 2 to fig. 7 are process diagrams of a VDMOS device manufacturing method for lithium battery charging management according to an embodiment of the present invention;
fig. 8 is a circuit diagram of a lithium battery power management system according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of a VDMOS device for lithium battery charging management according to an embodiment of the present invention.
The main element symbols are as follows:
10-a substrate; 11-a first epitaxial layer; 12-a first trench; 13-a second epitaxial layer; 14-a second trench; 15-a first silicon oxide layer; 16-a second silicon dioxide layer; 17-an opening; 18-a polysilicon layer; 19-body region; 20-a first implanted region; 21-a second implanted region; 22-a third implanted region; 23-a first dielectric layer; 24-a second dielectric layer; 25-a first contact hole; 26-a second contact hole; 27-a first metal layer; 28-a second metal layer; 29-third metal layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, 2 to 7, the invention further provides a method for manufacturing a VDMOS device for lithium battery charging management, including the following steps:
s1: providing a substrate 10 of a first conductivity type, and forming a first epitaxial layer 11 of the first conductivity type on the substrate 10;
referring to fig. 2, in the present embodiment, substrate 10 is a clean single crystal wafer having a particular crystal plane and suitable electrical, optical, and mechanical properties for growing epitaxial layers, substrate 10 typically being a nitride substrate material. The first conductive type is N type, the second conductive type is P type, N type ions are phosphorus, P type ions are boron, the conductive types of the substrate and the first epitaxial layer 11 are the same, the substrate is prepared by adopting an epitaxial layer growth technology, the resistivity of the substrate 10 is 0.02-0.005ohm.cm, the resistivity of the first epitaxial layer 11 is 20-40ohm.cm, and the subsequent preparation process is facilitated.
S2: photoetching to form first trenches 12 which are arranged at intervals and extend from the upper surface of the first epitaxial layer 11 to the substrate 10, filling first conductivity type ions into the first trenches 12 to form a second epitaxial layer 13, photoetching to form second trenches 14 which extend to the substrate 10 through the first epitaxial layer 11 between the first trenches 12, and filling first silicon oxide layers 15 into the second trenches 14, wherein the depth of the second trenches 14 is greater than that of the first trenches 12;
referring to fig. 3 and 4, in this embodiment, photoresist (not shown) is coated on the first epitaxial layer 11 at intervals, the first epitaxial layer 11 not covered by the photoresist is removed by dry etching to form two deep trenches arranged at intervals, that is, first trenches 12, the bottom of the first trenches 12 is located in the substrate 10, second epitaxial layers 13 of the first conductivity type are filled in the first trenches 12, the second epitaxial layers 13 are high-resistance N-type epitaxy, epitaxy on the surface of the silicon wafer is removed by mechanical grinding, and epitaxy in the first epitaxial layers 11 is retained. Similarly, a second trench 14 is formed on the first epitaxial layer 11 between the first trenches 12 by using a dry etching technique, the width of the second trench 14 is smaller than that of the first trenches 12, the depth of the second trench 14 is greater than that of the first trenches 12, the second trench 14 is connected with the first trenches 12, the bottoms of the second trenches are located in the substrate 10, the second trenches 14 are filled with a first silicon oxide layer 15 which can be used as isolation trenches to play a role in shunt isolation, the second epitaxial layer 13 is a high-resistance N-type epitaxial layer, so that the internal voltage resistance of the device can be improved, and the area of a PN junction is also increased.
S3: forming second silicon dioxide layers 16 arranged at intervals on the second trenches 14 and the first epitaxial layer 11, forming openings 17 between the second silicon dioxide layers 16, and forming a polysilicon layer 18 on the second silicon dioxide layers 16;
referring to fig. 5 and 6, in the present embodiment, a photoresist is coated on the first trench 12 and the first epitaxial layer 11 to expose the first epitaxial layer 11 between the second trench 14 and the second trench 14, silicon oxide is deposited, then a layer of polysilicon is deposited on the silicon oxide, and a photoresist is coated on the polysilicon at intervals to remove a portion of the polysilicon and the silicon oxide from the polysilicon by dry etching to form spaced second silicon oxide layers 16, polysilicon layers 18 and openings 17, wherein the thickness of the second silicon oxide layer 16 is smaller than that of the polysilicon layer 18, the second silicon oxide layer 16 is a gate oxide layer, and the polysilicon layer 18 is a gate polysilicon, in order to effectively suppress a short channel effect and maintain a good subthreshold slope, the thickness of the gate oxide layer is reduced in the same proportion as the channel length, and the operation stability of the device is improved.
S4: forming body regions 19 of the second conductivity type between the second trenches 14, first implanted regions 20 of the first conductivity type arranged at intervals in the body regions 19 and located on the lower surface of the opening 17 and connected with the second silicon oxide layer 16, second implanted regions 21 of the second conductivity type located between the first implanted regions 20, and third implanted regions 22 of the second conductivity type extending from the lower surface of the substrate 10 to the first trenches 12 and connected with a part of the second trenches 14;
referring to fig. 7, in the present embodiment, second conductivity type ions are implanted into the first epitaxial layer 11 along the opening 17 and diffused to form a body region 19, the upper surface of the body region 19 is connected to the two second silicon oxide layers 16, the first conductivity type ions are sequentially implanted into the body region 19 along the opening 17, the second conductive type ions form a first injection region 20 and a second injection region 21 positioned between the first injection regions 20, the second conductive type ions are injected from the lower surface of the substrate 10 to the bottom of the first trench 12 and the bottom of the second trench 14 to form a third injection region 22, the doping concentration of the first injection region 20 and the second injection region 21 is greater than that of the body region 19, the first injection region 20 is symmetrically arranged relative to the second injection region 21, and the width of the opening 17 is smaller than the sum of the lateral widths of the two first injection regions 20 and the second injection region 21, so that the switching frequency of the device is improved, and the conduction loss is reduced.
S5: forming a first dielectric layer 23 on the first epitaxial layer 11 and a part of the first trench 12, forming a second dielectric layer 24 on the first trench 12 and the polysilicon layer 18, the second dielectric layer being connected to the first injection region 20, forming a first contact hole 25 between the first dielectric layer 23 and the second dielectric layer 24, and forming a second contact hole 26 penetrating the second dielectric layer 24 and located in the opening 17 and connected to a part of the first injection region 20 and the second injection region 21;
referring to fig. 7 again, in the present embodiment, a dielectric growth is performed on the first epitaxial layer 11, the first trench 12, the polysilicon layer 18 and in the opening 17, a portion of the dielectric on the first trench 12 is removed by dry etching to form a first dielectric layer 23 on the first epitaxial layer 11 and on a portion of the first trench 12, a second dielectric layer 24 on a portion of the first trench 12, on the polysilicon layer 18 and connected to the second injection region 21, a first contact hole 25 is formed between the first dielectric layer 23 and the second dielectric layer 24, the second dielectric layers 24 are symmetrically disposed with respect to the second injection region 21, a second contact hole 26 connected to a portion of the first injection region 20 and the second injection region 21 is formed between the second dielectric layers 24, and the width of the second contact hole 26 is greater than the width of the first contact hole 25.
S6: a first metal layer 27 is formed on the first dielectric layer 23, in the first contact hole 25, on the second dielectric layer 24 and in the second contact hole 26, a second metal layer 28 is formed on the lower surface of the substrate 10 and is arranged corresponding to the third injection region 22, and a third metal layer 29 is formed on the lower surface of the substrate 10 between the third injection regions 22.
Referring to fig. 7 again, in the present embodiment, a magnetron sputtering technique is used to deposit metal on the first dielectric layer 23, in the first contact hole 25, on the second dielectric layer 24 and in the second contact hole 26 to form a first metal layer 27, similarly, a layer of metal is deposited on the lower surface of the substrate 10, and is etched to remove a portion of the metal correspondingly disposed on the second trench 14 and a portion of the third implantation region 22 to form second metal layers 28 arranged at intervals, and third metal layers 29 between the third implantation regions 22, the second metal layers 28 are symmetrically disposed with respect to the third metal layers 29, a projection area of the third implantation region 22 in a direction perpendicular to the substrate 10 is larger than a projection area of the second metal layers 28 in a direction perpendicular to the substrate 10, the third metal layers 29 are exactly disposed corresponding to the body region 19, the first metal layer 27 may be a source metal of the device, the second metal layers 28 may be used for over-temperature over-current and over-current detection signal output, the third metal layer 29 can be used as drain metal of the device, the device integrates a temperature sensor structure, the temperature information of the working environment of the device can be accurately extracted in time, when the temperature is too high, the device automatically cuts off the charging current, the charging current is applied to lithium battery charging management, the lithium battery and a charging system can be effectively prevented from being damaged by over temperature, meanwhile, the novel device can reduce the manufacturing cost, and the reliability of the over temperature feedback speed is accelerated to improve the system.
Referring again to fig. 7, the present invention provides a VDMOS device for lithium battery charging management, including:
a substrate 10 of a first conductivity type;
the semiconductor device comprises a first epitaxial layer 11 of a first conductivity type formed on a substrate 10, first trenches 12 arranged at intervals and extending from the upper surface of the first epitaxial layer 11 into the substrate 10, second epitaxial layers 13 of the first conductivity type filled in the first trenches 12, second trenches 14 located between the first trenches 12 and extending to the substrate 10, first silicon oxide layers 15 filled in the second trenches 14, and the depth of the second trenches 14 is greater than that of the first trenches 12;
second silicon dioxide layers 16 which are formed on the second trenches 14 and the first epitaxial layer 11 and are arranged at intervals, openings 17 which are positioned between the second silicon dioxide layers 16, and a polysilicon layer 18 which is formed on the second silicon dioxide layers 16;
a body region 19 of the second conductivity type formed between the second trenches 14, first implanted regions 20 of the first conductivity type formed in the body region 19 at intervals and located under the opening 17 to be connected to the second silicon oxide layer 16, second implanted regions 21 of the second conductivity type located between the first implanted regions 20, and third implanted regions 22 of the second conductivity type formed under the substrate 10 to extend to the first trenches 12 and to be connected to a portion of the second trenches 14;
a first dielectric layer 23 formed on the first epitaxial layer 11 and a portion of the first trench 12, a second dielectric layer 24 formed on a portion of the first trench 12 and the polysilicon layer 18 and connected to the first implantation region 20, a first contact hole 25 located between the first dielectric layer 23 and the second dielectric layer 24, and a second contact hole 26 penetrating the second dielectric layer 24 and located in the opening 17 and connected to a portion of the first implantation region 20 and the second implantation region 21;
a first metal layer 27 formed on the first dielectric layer 23, in the first contact hole 25, on the second dielectric layer 24 and in the second contact hole 26, a second metal layer 28 formed on the lower surface of the substrate 10 and disposed corresponding to the third implantation regions 22, and a third metal layer 29 formed on the lower surface of the substrate 10 between the third implantation regions 22.
In this embodiment, the first conductivity type is an N type, the second conductivity type is a P type, the width of the first trench 12 is greater than the width of the second trench 14, the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the first epitaxial layer 11, the doping concentration of the body region 19 is less than the doping concentration of the second implantation region 21, the thickness of the polysilicon layer 18 is greater than the thickness of the second silicon dioxide layer 16, and the width of the first contact hole 25 is less than the width of the second contact hole 26. The first trench 12 and the second trench 14 are both prepared by dry etching, the second trench 14 is used as an isolation trench to form a plurality of current paths in a device, the bottoms of the first trench 12 and the second trench 14 are connected with a third injection region 22, the third injection region 22 and the substrate 10 are different in conductivity type and can form a PN junction, the third injection region 22 and the second epitaxial layer 13 are different in conductivity type, the substrate 10 and the first epitaxial layer 11 are the same in conductivity type, and the first epitaxial layer 11 and the body region 19 are different in conductivity type and can form a PN junction. The first silicon oxide layer 15 and the second silicon oxide layer 16 are formed vertically in an L-shape.
Referring to fig. 8, it should be noted that, in the charging management circuit, the VDMOS device of the present invention integrates an over-temperature and over-current detection system, and after the temperature is too high, the charging current is too large, and the integrated detection system can output a shutdown signal to shut down the VDMOS2, so as to cut off the charging current and protect the safety of the lithium battery and the system. The functions of the VDMOS and the over-temperature and over-current detection system in the conventional system can be completed only by using a novel VDMOS device, the temperature and current detection structure can be integrated in the VDMOS device, the corresponding speed and the temperature measurement accuracy are improved, and the manufacturing cost of the charging system is reduced.
Referring to fig. 9, it should be understood that when the temperature detection and over-temperature and over-current protection structure of the novel VDMOS in the present invention is in a normal operating state, a current passes through the path a, the device is turned on, a system temperature is too high or a current of the path a is too large, that is, a charging current is too large, a current path of the detection system is turned on, that is, a breakdown voltage of a high-temperature junction is decreased, the path is turned on, a voltage drop of the current on a high-resistance epitaxy layer, that is, the second epitaxy layer 13 is increased, the NP junction is turned on to form a path, the current passes through the path B, an over-temperature and over-current detection output signal is turned off, the VDMOS2 is turned off, the charging system stops operating, the temperature of the charging system is decreased, or the path B is turned off after the current is decreased and returns to normal, the charging is resumed, and the operational reliability of the lithium battery charging management is improved to a certain extent.
The invention provides a VDMOS device for lithium battery charging management and a preparation method thereof.A first epitaxial layer 11 with the same conductivity type as that of a substrate 10 is formed on the substrate 10, first trenches 12 which are arranged at intervals are formed in the substrate 10 from the upper surface of the first epitaxial layer 11, the first trenches 12 are filled with high-resistance epitaxy to form a second epitaxial layer 13, second trenches 14 are formed between the first trenches 12, and a first silicon oxide layer 15 is filled in the second trenches 14 to be used as isolation trenches to form a plurality of current paths. Forming a second silicon oxide layer 16 on the second trench 14 and on the first epitaxial layer 11 and forming a polysilicon layer 18 on the second silicon oxide layer 16, forming a body region 19, a first implanted region 20 and a second implanted region 21 in the first epitaxial layer 11 by ion implantation, ion implantation is carried out in the substrate 10 to form a third implantation region 22 connected with the bottoms of the first trench 12 and the second trench 14, a second metal layer 28 corresponding to the third implantation region 22 is used for outputting over-temperature and over-current detection signals in a circuit, the over-temperature and over-current detection module is integrated into the device, so that the working environment temperature of the device can be accurately and timely extracted, the manufacturing cost is reduced, the risk of preventing the lithium battery from being damaged by over-temperature can be reduced, when the temperature is too high, the device automatically cuts off the charging current, and the over-temperature feedback rate is improved, so that the working stability of lithium battery charging management is improved.
In all examples shown and described herein, any particular value should be construed as merely exemplary, and not as a limitation, and thus other examples of example embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above examples are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention.
Claims (9)
1. A VDMOS device for lithium battery charging management, comprising:
a substrate of a first conductivity type;
the structure comprises a first epitaxial layer of a first conductivity type formed on a substrate, first trenches arranged at intervals and extending from the upper surface of the first epitaxial layer to the substrate, second epitaxial layers of the first conductivity type filled in the first trenches, and second trenches located between the first trenches and extending to the substrate, wherein a first silicon oxide layer is filled in the second trenches, and the depth of the second trenches is greater than that of the first trenches;
second silicon dioxide layers which are formed on the second groove and the first epitaxial layer and are arranged at intervals, an opening positioned between the second silicon dioxide layers and a polycrystalline silicon layer formed on the second silicon dioxide layers;
the second conductive body region is formed between the second trenches, the first conductive first injection region is formed in the body region at intervals, located on the lower surface of the opening and connected with the second silicon oxide layer, the second conductive second injection region is located between the first injection regions, and the second conductive third injection region is formed on the lower surface of the substrate, extends to the first trenches and is connected with a part of the second trenches;
the first dielectric layer is formed on the first epitaxial layer and a part of the first groove, the second dielectric layer is formed on a part of the first groove and the polycrystalline silicon layer and is connected with the first injection region, the first contact hole is positioned between the first dielectric layer and the second dielectric layer, and the second contact hole penetrates through the second dielectric layer and is positioned in the opening and is connected with a part of the first injection region and the second injection region;
the first metal layer is formed on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, the second metal layer is formed on the lower surface of the substrate and is arranged corresponding to the third injection regions, and the third metal layer is formed on the lower surface of the substrate between the third injection regions.
2. The VDMOS device for lithium battery charge management according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type, and wherein a width of the first trench is greater than a width of the second trench.
3. The VDMOS device for lithium battery charge management according to claim 1, wherein a doping concentration of the second epitaxial layer is greater than a doping concentration of the first epitaxial layer, and a doping concentration of the body region is less than a doping concentration of the second implanted region.
4. The VDMOS device for lithium battery charge management according to claim 1, wherein a thickness of the polysilicon layer is greater than a thickness of the second silicon oxide layer, and a width of the first contact hole is smaller than a width of the second contact hole.
5. A preparation method of a VDMOS device for lithium battery charging management is characterized by comprising the following steps:
providing a substrate of a first conductive type, and forming a first epitaxial layer of the first conductive type on the substrate;
photoetching and forming first grooves which are arranged at intervals and extend from the upper surface of the first epitaxial layer into the substrate, filling first conductive type ions into the first grooves to form a second epitaxial layer, photoetching and forming second grooves which penetrate through the first epitaxial layer and extend into the substrate between the first grooves, and filling first silicon oxide layers into the second grooves, wherein the depth of the second grooves is greater than that of the first grooves;
forming second silicon dioxide layers arranged at intervals on the second groove and the first epitaxial layer, forming an opening between the second silicon dioxide layers, and forming a polycrystalline silicon layer on the second silicon dioxide layers;
forming body regions of a second conductivity type between the second trenches, forming first injection regions of the first conductivity type which are arranged at intervals in the body regions and located on the lower surfaces of the openings and connected with the second silicon oxide layer, forming second injection regions of the second conductivity type which are located between the first injection regions, and forming third injection regions of the second conductivity type which are connected with part of the second trenches and extend from the lower surface of the substrate to the first trenches;
forming a first dielectric layer on the first epitaxial layer and a part of the first trench, a second dielectric layer connected with the first injection region on the polycrystalline silicon layer, a first contact hole between the first dielectric layer and the second dielectric layer, and a second contact hole penetrating through the second dielectric layer and positioned in the opening and connected with a part of the first injection region and the second injection region;
and forming a first metal layer on the first dielectric layer, in the first contact hole, on the second dielectric layer and in the second contact hole, forming a second metal layer on the lower surface of the substrate and corresponding to the third injection region, and forming a third metal layer on the lower surface of the substrate between the third injection regions.
6. The method for preparing a VDMOS device for lithium battery charge management according to claim 5, wherein the first conductivity type is N-type, the second conductivity type is P-type, the resistivity of the substrate is 0.02-0.005 ohm-cm, and the resistivity of the first epitaxial layer is 20-40 ohm-cm.
7. The method for preparing a VDMOS device for lithium battery charging management according to claim 5, wherein the first trench and the second trench are prepared by dry etching, and the width of the first trench is greater than the width of the second trench.
8. The method for preparing a VDMOS device for lithium battery charge management according to claim 5, wherein forming second silicon oxide layers spaced apart from each other on the second trenches and the first epitaxial layer comprises:
depositing silicon oxide on the first epitaxial layer, the second epitaxial layer and the first silicon oxide layer;
coating photoresist on the silicon oxide corresponding to the first epitaxial layer positioned on the first silicon oxide layer and between the second grooves;
and removing the silicon oxide which is not covered by the photoresist to form second silicon oxide layers and openings positioned between the second silicon oxide layers.
9. The method for preparing the VDMOS device for lithium battery charging management according to claim 5, wherein the first metal layer, the second metal layer, and the third metal layer are prepared by magnetron sputtering, and the second epitaxial layer is prepared by removing the first epitaxial layer by mechanical grinding and leaving the second epitaxial layer in the first trench.
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