CN113838916A - 一种具有pmos电流嵌位的分离栅cstbt及其制作方法 - Google Patents
一种具有pmos电流嵌位的分离栅cstbt及其制作方法 Download PDFInfo
- Publication number
- CN113838916A CN113838916A CN202111116185.9A CN202111116185A CN113838916A CN 113838916 A CN113838916 A CN 113838916A CN 202111116185 A CN202111116185 A CN 202111116185A CN 113838916 A CN113838916 A CN 113838916A
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- gate electrode
- dielectric layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000926 separation method Methods 0.000 title claims abstract description 98
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000003860 storage Methods 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 339
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 49
- 229920005591 polysilicon Polymers 0.000 claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- 238000002955 isolation Methods 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 20
- 238000002513 implantation Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 5
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims description 5
- 229910003465 moissanite Inorganic materials 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 230000002829 reductive effect Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 15
- 238000009826 distribution Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 230000002441 reversible effect Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 230000036961 partial effect Effects 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/765—Making of isolation regions between components by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
本发明涉及一种具有PMOS电流嵌位的分离栅CSTBT及其制作方法,属于功率半导体器件技术领域。本发明在传统的CSTBT基础上引入P型埋层和与发射极金属等电位的分离栅电极,通过电荷补偿作用有效的消除了N型电荷存储层对器件击穿特性的影响,有利于改善导通压降Vceon和关断损耗Eoff的折中关系。而且寄生PMOS结构的引入,有利于降低饱和电流,提高器件短路安全工作区,同时减小米勒电容,提高器件的开关速度,降低器件的开关损耗。另外本发明将分离栅电极和栅电极集成在同一个沟槽内,在提高芯片集成度的同时也可以缩短PMOS和NMOS沟道的距离,有利于增强PMOS的钳位效果以及提高关断过程中芯片内部的电流均匀性,提高器件的可靠性和反偏安全工作区。
Description
技术领域
本发明属于功率半导体器件技术领域,具体涉及一种具有PMOS电流嵌位的分离栅CSTBT及其制作方法。
背景技术
绝缘栅双极型晶体管(IGBT)兼具了场效应晶体管(MOSFET)和双极结晶型晶体管(BJT)的优点,既具有MOSFET易于驱动、输入阻抗低、开关速度快的优点,又具有BJT通态电流密度大、导通压降低、损耗小、稳定性好的优点,因而发展为现代电力电子电路中的核心电子元器件之一,被广泛应用于交通、通信、家用电器及航空航天各个领域。IGBT的运用极大地改善了电力电子***的性能。
从二十世纪八十年代IGBT被发明以来,IGBT一直是沿着降低器件开关损耗、提高器件工作频率和提高器件可靠性的趋势发展。其中沟槽电荷存储型IGBT(CSTBT)是在第六代沟槽场阻止型IGBT(Trench FS-IGBT)的基础上在P型基区下方引入具有较高掺杂和一定厚度的N型掺杂的电荷存储层制得。N型电荷存储层的引入提高了空穴势垒,改善了器件漂移区载流子分布,增强漂移区域的电导调制效应,降低了器件的导通压降,优化了器件的导通压降与开关损耗之间的折中关系。然而,传统的CSTBT(如图1所示)也存在一些问题,比如N型电荷存储层的引入虽然改善了漂移区的载流子分布,但是随着N型电荷存储层掺杂浓度的增加,在器件的正向导通特性得到改善的同时器件的击穿特性会发生了退化,这限制了器件在高压领域的应用。另一个缺点是对于沟槽型IGBT来说,为了提高芯片的集成度,沟槽密度做的比较大,导致器件正向导通时的饱和电流较大,但大的饱和电流会使其短路安全工作能力变差,通过减小沟槽密度可以减小饱和电流,但这会使器件表面电流分布不均匀,影响器件的可靠性,并且沟道密度的增加会增大器件的栅极电容,增加器件的开关损耗。
发明内容
本发明所要解决的技术问题是针对现有技术存在的问题,提供一种具有PMOS电流嵌位的分离栅CSTBT及其制作方法,从而改善载流子存储层的引入导致CSTBT击穿特性退化的影响和沟道密度大引起的栅极电容大以及正向导通时饱和电流大的缺点。
为解决上述技术问题,本发明实施例提供一种具有PMOS电流嵌位的分离栅CSTBT,其元胞结构包括由下至上依次层叠设置的背面集电极金属1、P型集电区2、N型场阻止层3和N-漂移区4;所述N-漂移区4的上层具有交替设置的P型埋层5和沟槽结构,所述沟槽结构下表面的深度大于P型埋层5下表面的结深;
所述P型埋层5的上表面具有N型电荷存储层6,所述N型电荷存储层6的上表面具有P型基区7,所述P型基区7的上表面具有侧面相互接触的N+发射区10及P+发射区8;
所述沟槽结构包括栅电极121、分离栅电极122、栅介质层123、分离栅介质层124和多晶硅隔离介质层125;其特征在于,栅电极121和分离栅电极122通过多晶硅隔离介质层125相隔离;所述栅电极121下表面的深度大于P型埋层5下表面的结深,栅电极121与N-漂移区4、P型埋层5、N型电荷存储层6、P型基区7和N+发射区10的一侧通过栅介质层123相连;所述分离栅电极122下表面的深度大于P型埋层5下表面的深度,分离栅电极122与N-漂移区4、P型埋层5、N型电荷存储层6、P型基区7和P+发射区8的另一侧通过分离栅介质层124相连;
在栅电极121、栅介质层123、多晶硅隔离介质层125上表面覆盖有绝缘介质层11;在分离栅电极122、分离栅介质层124、绝缘介质层11、N+发射区10和P+发射区8上表面覆盖有发射极金属9,分离栅电极122和发射极金属9等电位。
为解决上述技术问题,本发明实施例提供一种具有PMOS电流嵌位的分离栅CSTBT,其元胞结构包括由下至上依次层叠设置的背面集电极金属1、P型集电区2、N型场阻止层3和N-漂移区4;所述N-漂移区4的上层具有交替设置的P型埋层5和沟槽结构,所述沟槽结构下表面的深度大于P型埋层5下表面的结深;
所述P型埋层5的上表面具有N型电荷存储层6,所述N型电荷存储层6的上表面具有P型基区7,所述P型基区7的上层中靠近栅电极的一侧具有N+发射区10;
所述沟槽结构包括栅电极121、分离栅电极122、栅介质层123、分离栅介质层(124)和多晶硅隔离介质层125;其特征在于,栅电极121和分离栅电极122通过多晶硅隔离介质层125相隔离;所述栅电极121下表面的深度大于P型埋层5下表面的结深,栅电极121与N-漂移区4、P型埋层5、N型电荷存储层6、P型基区7和N+发射区10的一侧通过栅介质层123相连;所述分离栅电极122下表面的深度大于P型埋层5下表面的深度,分离栅电极122与N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7的另一侧通过分离栅介质层124相连;
在P型基区7的上表面覆盖有肖特基接触金属13;在栅电极121、栅介质层123、多晶硅隔离介质层125上表面覆盖有绝缘介质层11;在分离栅电极122、分离栅介质层124、绝缘介质层11和N+发射区10上表面覆盖有发射极金属9,分离栅电极122和肖特基接触金属13与发射极金属9等电位。
在上述技术方案的基础上,本发明还可以做如下改进。
进一步的,分离栅电极122呈L型并半包围栅电极121,栅电极121的下表面和侧面通过多晶硅隔离介质层125与分离栅电极122相隔离。
进一步的,N-漂移区4中具有侧面相互接触的超结P柱14和超结N柱15;所述超结N柱15位于P型埋层5的下方,超结P柱14位于沟槽结构的下方;所述超结P柱14和超结N柱15满足电荷平衡要求。
进一步的,分离栅介质层124的厚度大于或等于栅介质层123的厚度。
进一步的,器件所用的半导体材料为Si、SiC、GaAs、GaN、Ga2O3、AlN和金刚石中的任意一种或多种。
进一步的,器件结构不仅适用于IGBT器件,将器件背面的P型集电区2换为N型掺杂,所述结构同样适用于MOSFET器件。
为解决上述技术问题,本发明实施例提供一种具有PMOS电流嵌位的分离栅CSTBT的制作方法,包括以下步骤:
步骤1:采用N型轻掺杂单晶硅片作为器件的N-漂移区4;
步骤2:在硅片表面生长一层场氧化层,光刻得到有源区,再生长一层预氧化层,通过离子注入P型杂质在N-漂移区4的上方制得P型埋层5,通过离子注入N型杂质在P型埋层5的上表面制得N型电荷存储层6,通过离子注入P型杂质在N型电荷存储层6的上表面制得P型基区7;
步骤3:在硅片表面淀积保护层,光刻出窗口进行沟槽硅刻蚀,进而在N-漂移区4上刻蚀出多个分离栅沟槽,每个分离栅沟槽之间具有N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7,所述分离栅沟槽下表面的深度大于P型埋层5下表面的结深;
步骤4:在所述分离栅沟槽的底部和侧壁形成介质层作为分离栅介质层124,在所述分离栅介质层124上淀积多晶硅制得分离栅电极122;
步骤5:在硅片表面淀积保护层,光刻出窗口进行部分多晶硅及介质层刻蚀,进而在N-漂移区4上刻蚀出栅沟槽,所述栅沟槽下表面的深度大于P型埋层5下表面的结深;
步骤6:在栅沟槽里形成栅介质层123和多晶硅隔离介质层125,然后在栅沟槽里淀积多晶硅制得栅电极121,栅电极121和分离栅电极122相互独立并通过多晶硅隔离介质层125相隔离;所述N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7的一侧均与栅介质层123相连,所述N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7的另一侧均与分离栅介质层124相连;
步骤7:通过掩膜、光刻和离子注入工艺在P型基区7的顶部分别注入N型杂质和P型杂质,制得侧面相互接触且并排设置的N+发射区10和P+发射区8,所述N+发射区10和栅介质层123相连,所述P+发射区8与分离栅介质层124相连;
步骤8:在硅片正面淀积介质层,并通过光刻、刻蚀工艺在栅电极121、栅介质层123和多晶硅隔离介质层125的上表面形成绝缘介质层11,然后在硅片正面淀积金属,在N+发射区10、P+发射区8、绝缘介质层11、分离栅电极122和分离栅介质层(124)的上表面形成发射极金属9;
步骤9:翻转硅片,减薄硅片厚度,在硅片背面注入N型杂质并退火制作器件的N型场阻止层3;在N型场阻止层3背面注入P型杂质并进行退火处理形成P型集电区2;再在硅片背面淀积金属形成集电极金属1。
进一步的,所述N型轻掺杂单晶硅片的厚度为300~600um,掺杂浓度为1013~1014个/cm3。
进一步的,制备P型埋层5时,离子注入的能量为200~500keV,注入剂量为1013~1014个/cm2,或,制备N型电荷存储层6时,离子注入能量为150~400keV,注入剂量为1013~1014个/cm2,或,制备P型基区7时,离子注入能量为100~400keV,注入剂量为1013~1014个/cm2,或,制备N+发射区10时,N型杂质的能量为30~60keV,注入剂量为1015~1016个/cm2,或,制备P+发射区8时,P型杂质的能量为60~80keV,注入剂量为1015~1016个/cm2。
进一步的,制备N型场阻止层3时,离子注入的能量为1500~2000keV,注入剂量为1013~1014个/cm2,退火温度为1200~1250℃,时间为300~600分钟;
或,制备P型集电区2时,注入能量为40~60keV,注入剂量为1012~1013个/cm2,退火温度为400~450℃,时间为20~30分钟。
进一步的,形成分离栅电极与栅电极结构的顺序可交换。
进一步的,形成沟槽结构和形成P型埋层5、N型电荷存储层6和P型基区7的顺序可交换。
进一步的,器件所用半导体材料为Si、SiC、GaAs、GaN、Ga2O3、AlN和金刚石中的任意一种或多种,各结构可采用同种半导体材料或者不同种半导体材料相组合。
进一步的,为了简化描述,上述器件结构和制备方法是以N沟道IGBT器件为例来说明,但本发明同样适用于P沟道IGBT器件的制备。
本发明的工作原理如下:
对于CSTBT来说,电荷存储层的引入会使得器件的击穿特性发生退化,另一个缺点是其具有大的栅极电容和饱和电流,通过增加沟槽之间距离减小NMOS的沟道密度可以减小饱和电流,但这会导致器件表面电流分布不均匀,从而降低器件工作时的可靠性。为此,本发明提出了一种具有PMOS电流嵌位的分离栅CSTBT。本发明在传统CSTBT结构的基础上,引入了与发射极等电位的分离栅电极122,并在N型电荷存储层6的下方引入P型埋层。当器件工作在阻断状态时,P型埋层5和N-漂移区4之间的PN结承担反向偏压,并且P型埋层5使得N型电荷存储层6被隔离,屏蔽了N型电荷存储层6对器件击穿特性的影响;同时分离栅电极122与发射极金属9等电位,从而形成电荷补偿,削弱N型电荷存储层6对器件击穿特性的影响,从而提高器件的击穿电压。因此与传统CSTBT相比,本发明可以提高N型电荷存储层6的掺杂浓度来改善器件正向导通时的载流子分布,从而提高了漂移区的电导调制能力降低了器件正向导通压降,改善导通压降Vceon和关断损耗Eoff的折中关系。另外,栅电极121和分离栅电极122位于同一沟槽内,其中P型埋层5、N型电荷存储层6、P型基区7和分离栅电极122形成一个寄生PMOS结构。当器件正向导通时,P型埋层5和N型电荷存储层6的电势会随着集电极电压的增大而增大,但当P型埋层5的电势增大到一定的值会使得PMOS开启。PMOS开启一方面使得N型电荷存储层6和P型埋层5相当于和发射极短接,则部分栅极-集电极电容转变为栅极-发射极电容,这可以有效的减小栅极-集电极电容(米勒电容),提高器件的开关速度,减小开关损耗。同时,在器件关断过程中,寄生PMOS结构的开启可以提高器件的载流子抽取速度,减小关断损耗,进一步改善器件正向导通压降Vceon和关断损耗Eoff之间的折中关系。另一方面PMOS开启可以使N型电荷存储层6和P型埋层5的电势被钳位,使得IGBT的NMOS沟道提前饱和,从而降低了IGBT的饱和电流,提高器件的短路安全工作区(SCSOA)。另外由于分离栅电极和栅电极位于同一个沟槽里,不仅可以节约芯片面积,提高芯片集成度,还缩短了PMOS和NMOS沟道的距离,有利于增强PMOS的钳位效果以及提高关断过程中芯片内部的电流均匀性,避免了电流集中,提高器件的可靠性和反偏安全工作区(RBSOA)。
本发明的有益效果表现在:
本发明通过在传统的CSTBT基础上引入P型埋层和与发射极金属等电位的分离栅电极,有效的消除了N型电荷存储层6对器件击穿特性的影响,因此可以提高N型电荷存储层6的掺杂浓度来改善器件正向导通时的载流子分布,从而提高了漂移区的电导调制能力降低了器件正向导通压降。而且寄生PMOS结构的引入,加速关断过程载流子的抽取速度,提高了器件的开关速度,降低了器件的开关损耗,进一步的改善了导通压降Vceon和关断损耗Eoff的折中关系。本发明通过PMOS结构开启对N型电荷存储层和P型埋层的电势进行钳位,不仅可以降低器件的饱和电流密度,从而提高器件的短路安全工作区(SCSOA);还可以有效的减小米勒电容,减小器件的开关损耗。另外分离栅电极和栅电极位于同一个沟槽内,在提高芯片集成度的同时也可以缩短PMOS和NMOS沟道的距离,可以提高PMOS的钳位效果,并且提高芯片内部的电流均匀性,提高器件的反偏安全工作区(RBSOA),提高可靠性。
附图说明
图1是传统CSTBT器件四个元胞并联的结构示意图;
图2是本发明实施例1提供的一种具有PMOS电流嵌位的分离栅CSTBT的四个元胞并联的结构示意图;
图3是本发明实施例2提供的一种具有PMOS电流嵌位的分离栅CSTBT的四个元胞并联的结构示意图;
图4是本发明实施例3提供的一种具有PMOS电流嵌位的分离栅CSTBT的四个元胞并联的结构示意图;
图5是本发明实施例4提供的一种具有PMOS电流嵌位的分离栅CSTBT的四个元胞并联的结构示意图;
图6是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT形成P型埋层5、N型电荷存储层6、P型基区7、并进行沟槽刻蚀后的四个元胞并联的结构示意图;
图7是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在沟槽底部和侧壁形成分离栅介质层124后的四个元胞并联的结构示意图;
图8是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在沟槽填充多晶硅后形成分离栅电极122后的四个元胞并联的结构示意图;
图9是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在分离栅沟槽内完成部分多晶硅和氧化层刻蚀后的四个元胞并联的结构示意图;
图10是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在栅沟槽内形成栅介质层123和多晶硅隔离介质层125后的四个元胞并联的结构示意图;
图11是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在栅沟槽内淀积多晶硅后形成栅电极121的四个元胞并联的结构示意图;
图12是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT通过离子注入形成N+发射区10及P+发射区8后的四个元胞并联的结构示意图;
图13是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在栅电极121、栅介质层123和多晶硅隔离介质层125的上表面形成绝缘介质层11的四个元胞并联的结构示意图;
图14是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在正面通过金属淀积形成发射极金属后的四个元胞并联的结构示意图;
图15是本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT在背面形成N型场阻止层、P+集电区、集电极金属后的四个元胞并联的结构示意图。
附图中,各标号所代表的部件列表如下:
1为集电极金属,2为P型集电区,3为N型场阻止层,4为N-漂移区,5为P型埋层,6为N型电荷存储层,7为P型基区,8为P+发射区,9为发射极金属,10为N+发射区,11为绝缘介质层,121为栅电极,122为分离栅电极,123为栅介质层,124为分离栅介质层,125为多晶硅隔离介质层,13为肖特基接触金属,14为超结P柱,15为超结N柱。
具体实施方式
以下结合附图对本发明的原理和特征进行描述,本发明的具体实施例以1200V电压等级的IGBT为例进行说明,所举实例只用于解释本发明,并非用于限定本发明的范围。
如图2所示,本发明实施例1提供的一种具有PMOS电流嵌位的分离栅CSTBT,其元胞结构包括由下至上依次层叠设置的背面集电极金属1、P型集电区2、N型场阻止层3和N-漂移区4;所述N-漂移区4的上层具有交替设置的P型埋层5和沟槽结构,所述沟槽结构下表面的深度大于P型埋层5下表面的结深;
所述P型埋层5的上表面具有N型电荷存储层6,所述N型电荷存储层6的上表面具有P型基区7,所述P型基区7的上表面具有侧面相互接触的N+发射区10及P+发射区8;
所述沟槽结构包括栅电极121、分离栅电极122、栅介质层123、分离栅介质层124和多晶硅隔离介质层125;其特征在于,栅电极121和分离栅电极122通过多晶硅隔离介质层125相隔离;所述栅电极121下表面的深度大于P型埋层5下表面的结深,栅电极121与N-漂移区4、P型埋层5、N型电荷存储层6、P型基区7和N+发射区10的一侧通过栅介质层123相连;所述分离栅电极122下表面的深度大于P型埋层5下表面的深度,分离栅电极122与N-漂移区4、P型埋层5、N型电荷存储层6、P型基区7和P+发射区8的另一侧通过分离栅介质层124相连;
在栅电极121、栅介质层123、多晶硅隔离介质层125上表面覆盖有绝缘介质层11;在分离栅电极122、分离栅介质层124、绝缘介质层11、N+发射区10和P+发射区8上表面覆盖有发射极金属9,分离栅电极122和发射极金属9等电位。
如图3所示,本发明实施例2提供的一种具有PMOS电流嵌位的分离栅CSTBT,其元胞结构包括由下至上依次层叠设置的背面集电极金属1、P型集电区2、N型场阻止层3和N-漂移区4;所述N-漂移区4的上层具有交替设置的P型埋层5和沟槽结构,所述沟槽结构下表面的深度大于P型埋层5下表面的结深;
所述P型埋层5的上表面具有N型电荷存储层6,所述N型电荷存储层6的上表面具有P型基区7,所述P型基区7的上层中靠近栅电极的一侧具有N+发射区10;
所述沟槽结构包括栅电极121、分离栅电极122、栅介质层123、分离栅介质层(124)和多晶硅隔离介质层125;其特征在于,栅电极121和分离栅电极122通过多晶硅隔离介质层125相隔离;所述栅电极121下表面的深度大于P型埋层5下表面的结深,栅电极121与N-漂移区4、P型埋层5、N型电荷存储层6、P型基区7和N+发射区10的一侧通过栅介质层123相连;所述分离栅电极122下表面的深度大于P型埋层5下表面的深度,分离栅电极122与N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7的另一侧通过分离栅介质层124相连;
在P型基区7的上表面覆盖有肖特基接触金属13;在栅电极121、栅介质层123、多晶硅隔离介质层125上表面覆盖有绝缘介质层11;在分离栅电极122、分离栅介质层124、绝缘介质层11和N+发射区10上表面覆盖有发射极金属9,分离栅电极122和肖特基接触金属13与发射极金属9等电位。
上述实施例通过引入与发射极金属1等电位的肖特基接触金属13,降低PMOS的导通压降,使得PMOS更快开启。这不仅可以在导通的时候钳位效果更好,更好的提高器件的短路工作安全区以及减小米勒电容;在关断的时候还可以进一步提高器件空穴的抽取速度,进一步改善导通压降和关断损耗的折中关系。
如图4所示,本发明实施例3提供的一种具有PMOS电流嵌位的分离栅CSTBT,是在实施例1或实施例2的基础上,使分离栅电极122呈L型并半包围栅电极121,栅电极121的下表面和侧面通过多晶硅隔离介质层125与分离栅电极122相隔离。
上述实施例中,通过工艺的调整,在进行多晶硅和分离栅介质层刻蚀时控制刻蚀的深度,改变分离栅电极的形状。L型分离栅可以通过减小栅电极和N-漂移区之间的耦合面积减小米勒电容,提高器件的开关速度,减小了器件的开关损耗。此外本实例还可以通过增加分离栅介质层124的厚度,有效的改善了器件在阻断状态下沟槽底部电场集中的现象,提高了器件的耐压能力。
如图5所示,本发明实施例4提供的一种具有PMOS电流嵌位的分离栅CSTBT,是在实施例1的基础上,使N-漂移区4中具有侧面相互接触的超结P柱14和超结N柱15;所述超结N柱15位于P型埋层5的下方,超结P柱14位于沟槽结构的下方;所述超结P柱14和超结N柱15满足电荷平衡要求。
上述实施例中,通过在漂移区4中引入超结P柱14和超结N柱15来将漂移区中一维耐压变成二维方向的耐压,改善了导通压降与器件击穿电压之间的折中关系,提高了器件的性能。
可选地,所述超结N柱15的掺杂浓度大于或等于N-漂移区4的掺杂浓度。
可选地,分离栅介质层124的厚度大于或等于栅介质层123的厚度。
上述实施例可以提高阻断状态下的介质层可靠性。
可选地,器件所用的半导体材料为Si、SiC、GaAs、GaN、Ga2O3、AlN和金刚石中的任意一种或多种。
可选地,器件结构不仅适用于IGBT器件,将器件背面的P型集电区2换为N型掺杂,所述结构同样适用于MOSFET器件。
本发明实施例5是以1200V电压等级的具有PMOS电流嵌位的分离栅CSTBT为例进行说明,根据本领域常识可根据实际需求制备不同性能参数的器件。
如图6-15所示,本发明实施例5提供的一种具有PMOS电流嵌位的分离栅CSTBT的制作方法,包括以下步骤:
步骤1:采用N型轻掺杂单晶硅片作为器件的N-漂移区4,所选硅片厚度为300~600um,掺杂浓度为1013~1014个/cm3;
步骤2:在硅片表面生长一层场氧化层,光刻得到有源区,再生长一层预氧化层,通过离子注入P型杂质在N-漂移区4的上方制得P型埋层5,离子注入的能量为200~500keV,注入剂量为1013~1014个/cm2,通过离子注入N型杂质在P型埋层5的上表面制得N型电荷存储层6,离子注入能量150~400keV,注入剂量为1013~1014个/cm2,通过离子注入P型杂质在N型电荷存储层6的上表面制得P型基区7,离子注入能量为100~400keV,注入剂量为1013~1014个/cm2;
步骤3:在硅片表面淀积保护层,光刻出窗口进行沟槽硅刻蚀,进而在N-漂移区4上刻蚀出多个分离栅沟槽,每个分离栅沟槽之间具有N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7,所述分离栅沟槽下表面的深度大于P型埋层5下表面的结深,如图6所示;
步骤4:在1050℃~1150℃的O2气氛下在所述分离栅沟槽的底部和侧壁形成介质层作为分离栅介质层124,如图7所示,而后在750℃~950℃在所述分离栅介质层124上淀积多晶硅,然后反刻蚀掉表面多余多晶硅制得分离栅电极122,如图8所示;
步骤5:在硅片表面淀积保护层,光刻出窗口进行部分多晶硅及介质层刻蚀,进而在N-漂移区4上刻蚀出栅沟槽,如图9所示,所述栅沟槽下表面的深度大于P型埋层5下表面的结深;
步骤6:在1050℃~1150℃的O2气氛下在栅沟槽里形成栅介质层123和多晶硅隔离介质层125,如图10所示,然后在栅沟槽里淀积多晶硅并反刻表面多晶硅制得栅电极121,如图11所示,栅电极121和分离栅电极122相互独立并通过多晶硅隔离介质层125相隔离;所述N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7的一侧均与栅介质层123相连,所述N-漂移区4、P型埋层5、N型电荷存储层6和P型基区7的另一侧均与分离栅介质层124相连;
步骤7:通过掩膜、光刻和离子注入工艺在P型基区7的顶部分别注入N型杂质和P型杂质,N型杂质的能量为30~60keV,注入剂量为1015~1016个/cm2,离子注入P型杂质的能量为60~80keV,注入剂量为1015~1016个/cm2,退火温度为900℃,时间为20~30分钟,制得侧面相互接触且并排设置的N+发射区10和P+发射区8,如图12所示,所述N+发射区10和栅介质层123相连,所述P+发射区8与分离栅介质层124相连;
步骤8:在硅片正面淀积介质层,并通过光刻、刻蚀工艺在栅电极121、栅介质层123和多晶硅隔离介质层125的上表面形成绝缘介质层11,如图13所示,然后在硅片正面淀积金属,在N+发射区10、P+发射区8、绝缘介质层11、分离栅电极122和分离栅介质层(124)的上表面形成发射极金属9,如图14所示;
步骤9:翻转硅片,减薄硅片厚度,在硅片背面注入N型杂质并退火制作器件的N型场阻止层3,N型场阻止层3的厚度为15~30微米,离子注入的能量为1500~2000keV,注入剂量为1013~1014个/cm2,退火温度为1200~1250℃,时间为300~600分钟;在N型场阻止层3背面注入P型杂质形成P型集电区2,注入能量为40~60keV,注入剂量为1012~1013个/cm2,在H2与N2混合的气氛下进行背面退火,温度为400~450℃,时间为20~30分钟;再在硅片背面淀积金属形成集电极金属1,如图15所示,至此完成了具有PMOS电流嵌位的分离栅CSTBT的制备。
可选地,形成分离栅电极与栅电极结构的顺序可交换。
可选地,形成沟槽结构和形成P型埋层5、N型电荷存储层6和P型基区7的顺序可交换。
可选地,N型场阻止层3的制备可以在制备器件正面结构之前进行制备;或者直接选用具有N型场阻止层3和N-漂移区4的双层外延材料作为工艺起始的硅片材料。
可选地,本发明中绝缘介质层11、栅介质层123、分离栅介质层124和多晶硅隔离介质层125的材料可以选用同种材料也可以采用不同材料组合。
可选地,器件所用半导体材料为Si、SiC、GaAs、GaN、Ga2O3、AlN和金刚石中的任意一种或多种,各结构可采用同种半导体材料或者不同种半导体材料相组合。
可选地,为了简化描述,上述器件结构和制备方法是以N沟道IGBT器件为例来说明,但本发明同样适用于P沟道IGBT器件的制备。
本发明通过在N型电荷存储层下方引入P型埋层,以及在N型电荷存储层、P型埋层、P型基区和P+发射区的侧面引入与发射极等电位的分离栅电极,本发明在传统CSTBT结构的基础上集成了一个由P型埋层作为源极,N型电荷存储层作为基区,P型基区和P+发射区作为漏极,分离栅作为栅电极的PMOS结构。P型埋层以及分离栅电极对N型电荷存储层起到了有效的电荷补偿作用,避免了N型电荷存储层掺杂浓度和厚度对器件击穿电压的影响,因此可以进一步提高N型电荷存储层的浓度,改善器件正向导通时的载流子分布,从而降低器件正向导通压降,减小器件的通态损耗。在器件关断过程中,漂移区的过剩空穴可以通过PMOS结构快速被抽走,从而提高了器件的开关速度,降低了器件的开关损耗,进一步地改善器件正向导通压降Vceon和关断损耗Eoff的折中关系。在正向导通时,N型电荷存储层和P型埋层的电位会随着集电极正向偏压的增大而增大,当P型埋层的电势增加到一定值会使得PMOS开启。PMOS的开启一方面会使得P型埋层和N型电荷存储层相当于和发射极短接,从而使得部分栅极-集电极电容转变为栅极-发射极电容,有效的减小栅极-集电极电容(米勒电容),提高器件的开关速度,减小器件的开关损耗。另一方面PMOS的开启可以使得N型电荷存储层和P型埋层的电位被嵌位住,一方面可以使得当器件集电极偏压进一步增大时,NMOS沟道电势不会进一步增大,从而使得器件饱和电流大大地减小达到提高器件短路安全工作区(SCSOA)的目的。另外由于分离栅电极和栅电极位于同一个沟槽里,不仅可以节约芯片面积,提高芯片集成度,还缩短了PMOS和NMOS沟道的距离,有利于增强PMOS的钳位效果以及提高关断过程中芯片内部的电流均匀性,避免了电流集中,提高器件的可靠性和反偏安全工作区(RBSOA)。
在本发明的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。
在本发明中,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或成一体;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系,除非另有明确的限定。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中,除非另有明确的规定和限定,第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触,或第一和第二特征通过中间媒介间接接触。而且,第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方,或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中,参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且,描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外,在不相互矛盾的情况下,本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种具有PMOS电流嵌位的分离栅CSTBT,其元胞结构包括由下至上依次层叠设置的背面集电极金属(1)、P型集电区(2)、N型场阻止层(3)和N-漂移区(4);所述N-漂移区(4)的上层具有交替设置的P型埋层(5)和沟槽结构,所述沟槽结构下表面的深度大于P型埋层(5)下表面的结深;
所述P型埋层(5)的上表面具有N型电荷存储层(6),所述N型电荷存储层(6)的上表面具有P型基区(7),所述P型基区(7)的上表面具有侧面相互接触的N+发射区(10)及P+发射区(8);
所述沟槽结构包括栅电极(121)、分离栅电极(122)、栅介质层(123)、分离栅介质层(124)和多晶硅隔离介质层(125);其特征在于,栅电极(121)和分离栅电极(122)通过多晶硅隔离介质层(125)相隔离;所述栅电极(121)下表面的深度大于P型埋层(5)下表面的结深,栅电极(121)与N-漂移区(4)、P型埋层(5)、N型电荷存储层(6)、P型基区(7)和N+发射区(10)的一侧通过栅介质层(123)相连;所述分离栅电极(122)下表面的深度大于P型埋层(5)下表面的深度,分离栅电极(122)与N-漂移区(4)、P型埋层(5)、N型电荷存储层(6)、P型基区(7)和P+发射区(8)的另一侧通过分离栅介质层(124)相连;
在栅电极(121)、栅介质层(123)、多晶硅隔离介质层(125)上表面覆盖有绝缘介质层(11);在分离栅电极(122)、分离栅介质层(124)、绝缘介质层(11)、N+发射区(10)和P+发射区(8)上表面覆盖有发射极金属(9),分离栅电极(122)和发射极金属(9)等电位。
2.一种具有PMOS电流嵌位的分离栅CSTBT,其元胞结构包括由下至上依次层叠设置的背面集电极金属(1)、P型集电区(2)、N型场阻止层(3)和N-漂移区(4);所述N-漂移区(4)的上层具有交替设置的P型埋层(5)和沟槽结构,所述沟槽结构下表面的深度大于P型埋层(5)下表面的结深;
所述P型埋层(5)的上表面具有N型电荷存储层(6),所述N型电荷存储层(6)的上表面具有P型基区(7),所述P型基区(7)的上层中靠近栅电极的一侧具有N+发射区(10);
所述沟槽结构包括栅电极(121)、分离栅电极(122)、栅介质层(123)、分离栅介质层(124)和多晶硅隔离介质层(125);其特征在于,栅电极(121)和分离栅电极(122)通过多晶硅隔离介质层(125)相隔离;所述栅电极(121)下表面的深度大于P型埋层(5)下表面的结深,栅电极(121)与N-漂移区(4)、P型埋层(5)、N型电荷存储层(6)、P型基区(7)和N+发射区(10)的一侧通过栅介质层(123)相连;所述分离栅电极(122)下表面的深度大于P型埋层(5)下表面的深度,分离栅电极(122)与N-漂移区(4)、P型埋层(5)、N型电荷存储层(6)和P型基区(7)的另一侧通过分离栅介质层(124)相连;
在P型基区(7)的上表面覆盖有肖特基接触金属(13);在栅电极(121)、栅介质层(123)、多晶硅隔离介质层(125)上表面覆盖有绝缘介质层(11);在分离栅电极(122)、分离栅介质层(124)、绝缘介质层(11)和N+发射区(10)上表面覆盖有发射极金属(9),分离栅电极(122)和肖特基接触金属(13)与发射极金属(9)等电位。
3.根据权利要求1或权利要求2所述的一种具有PMOS电流嵌位的分离栅CSTBT,其特征在于,分离栅电极(122)呈L型并半包围栅电极(121),栅电极(121)的下表面和侧面通过多晶硅隔离介质层(125)与分离栅电极(122)相隔离。
4.根据权利要求1或权利要求2所述的一种具有PMOS电流嵌位的分离栅CSTBT,其特征在于,N-漂移区(4)中具有侧面相互接触的超结P柱(14)和超结N柱(15),所述超结N柱(15)位于P型埋层(5)的下方,超结P柱(14)位于沟槽结构的下方;所述超结P柱(14)和超结N柱(15)满足电荷平衡要求。
5.根据权利要求1或权利要求2所述的一种具有PMOS电流嵌位的分离栅CSTBT,其特征在于,分离栅介质层124的厚度大于或等于栅介质层123的厚度。
6.根据权利要求1或权利要求2所述的一种具有PMOS电流嵌位的分离栅CSTBT,其特征在于,器件所用的半导体材料为Si、SiC、GaAs、GaN、Ga2O3、AlN和金刚石中的任意一种或多种。
7.一种具有PMOS电流嵌位的分离栅CSTBT的制作方法,其特征在于,包括以下步骤:
步骤1:采用N型轻掺杂单晶硅片作为器件的N-漂移区(4);
步骤2:在硅片表面生长一层场氧化层,光刻得到有源区,再生长一层预氧化层,通过离子注入P型杂质在N-漂移区(4)的上方制得P型埋层(5),通过离子注入N型杂质在P型埋层(5)的上表面制得N型电荷存储层(6),通过离子注入P型杂质在N型电荷存储层(6)的上表面制得P型基区(7);
步骤3:在硅片表面淀积保护层,光刻出窗口进行沟槽硅刻蚀,进而在N-漂移区(4)上刻蚀出多个分离栅沟槽,每个分离栅沟槽之间具有N-漂移区(4)、P型埋层(5)、N型电荷存储层(6)和P型基区(7),所述分离栅沟槽下表面的深度大于P型埋层(5)下表面的结深;
步骤4:在所述分离栅沟槽的底部和侧壁形成介质层作为分离栅介质层(124),在所述分离栅介质层(124)上淀积多晶硅制得分离栅电极(122);
步骤5:在硅片表面淀积保护层,光刻出窗口进行部分多晶硅及介质层刻蚀,进而在N-漂移区(4)上刻蚀出栅沟槽,所述栅沟槽下表面的深度大于P型埋层(5)下表面的结深;
步骤6:在栅沟槽里形成栅介质层(123)和多晶硅隔离介质层(125),然后在栅沟槽里淀积多晶硅制得栅电极(121),栅电极(121)和分离栅电极(122)相互独立并通过多晶硅隔离介质层(125)相隔离;所述N-漂移区(4)、P型埋层(5)、N型电荷存储层(6)和P型基区(7)的一侧均与栅介质层(123)相连,所述N-漂移区(4)、P型埋层(5)、N型电荷存储层(6)和P型基区(7)的另一侧均与分离栅介质层(124)相连;
步骤7:通过掩膜、光刻和离子注入工艺在P型基区(7)的顶部分别注入N型杂质和P型杂质,制得侧面相互接触且并排设置的N+发射区(10)和P+发射区(8),所述N+发射区(10)和栅介质层(123)相连,所述P+发射区(8)与分离栅介质层(124)相连;
步骤8:在硅片正面淀积介质层,并通过光刻、刻蚀工艺在栅电极(121)、栅介质层(123)和多晶硅隔离介质层(125)的上表面形成绝缘介质层(11),然后在硅片正面淀积金属,在N+发射区(10)、P+发射区(8)、绝缘介质层(11)、分离栅电极(122)和分离栅介质层(124)的上表面形成发射极金属(9);
步骤9:翻转硅片,减薄硅片厚度,在硅片背面注入N型杂质并退火制作器件的N型场阻止层(3);在N型场阻止层(3)背面注入P型杂质并进行退火处理形成P型集电区(2);再在硅片背面淀积金属形成集电极金属(1)。
8.根据权利要求1或权利要求2所述的一种具有PMOS电流嵌位的分离栅CSTBT的制作方法,其特征在于,所述N型轻掺杂单晶硅片的厚度为300~600um,掺杂浓度为1013~1014个/cm3。
9.根据权利要求1或权利要求2所述的一种具有PMOS电流嵌位的分离栅CSTBT的制作方法,其特征在于,制备P型埋层(5)时,离子注入的能量为200~500keV,注入剂量为1013~1014个/cm2,或,制备N型电荷存储层(6)时,离子注入能量为150~400keV,注入剂量为1013~1014个/cm2,或,制备P型基区(7)时,离子注入能量为100~400keV,注入剂量为1013~1014个/cm2,或,制备N+发射区(10)时,N型杂质的能量为30~60keV,注入剂量为1015~1016个/cm2,或,制备P+发射区(8)时,P型杂质的能量为60~80keV,注入剂量为1015~1016个/cm2。
10.根据权利要求1或权利要求2所述的一种具有PMOS电流嵌位的分离栅CSTBT的制作方法,其特征在于,制备N型场阻止层(3)时,离子注入的能量为1500~2000keV,注入剂量为1013~1014个/cm2,退火温度为1200~1250℃,时间为300~600分钟;
或,制备P型集电区(2)时,注入能量为40~60keV,注入剂量为1012~1013个/cm2,退火温度为400~450℃,时间为20~30分钟。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111116185.9A CN113838916B (zh) | 2021-09-23 | 2021-09-23 | 一种具有pmos电流嵌位的分离栅cstbt及其制作方法 |
US17/752,889 US20230088637A1 (en) | 2021-09-23 | 2022-05-25 | Split gate cstbt with current clamping pmos and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111116185.9A CN113838916B (zh) | 2021-09-23 | 2021-09-23 | 一种具有pmos电流嵌位的分离栅cstbt及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113838916A true CN113838916A (zh) | 2021-12-24 |
CN113838916B CN113838916B (zh) | 2023-05-26 |
Family
ID=78969426
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111116185.9A Active CN113838916B (zh) | 2021-09-23 | 2021-09-23 | 一种具有pmos电流嵌位的分离栅cstbt及其制作方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20230088637A1 (zh) |
CN (1) | CN113838916B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114093934A (zh) * | 2022-01-20 | 2022-02-25 | 深圳市威兆半导体有限公司 | 一种igbt器件及其制造方法 |
CN114792734A (zh) * | 2022-06-22 | 2022-07-26 | 深圳芯能半导体技术有限公司 | 一种双沟槽碳化硅mosfet及其制备方法 |
WO2023193370A1 (zh) * | 2022-04-08 | 2023-10-12 | 苏州东微半导体股份有限公司 | Igbt器件及其制造方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116632052B (zh) * | 2023-06-01 | 2024-02-09 | 上海林众电子科技有限公司 | 一种沟槽栅igbt器件及其制备方法 |
CN118231456A (zh) * | 2024-05-14 | 2024-06-21 | 深圳天狼芯半导体有限公司 | 一种碳化硅沟槽mos器件及其制备方法、芯片 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150372131A1 (en) * | 2014-06-24 | 2015-12-24 | François Hébert | Charged balanced devices with shielded gate trench |
WO2016014224A1 (en) * | 2014-07-25 | 2016-01-28 | United Silicon Carbide, Inc. | Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same |
CN105702739A (zh) * | 2016-05-04 | 2016-06-22 | 深圳尚阳通科技有限公司 | 屏蔽栅沟槽mosfet器件及其制造方法 |
CN105742346A (zh) * | 2016-04-26 | 2016-07-06 | 电子科技大学 | 双***沟槽栅电荷存储型rc-igbt及其制造方法 |
CN107623027A (zh) * | 2017-10-20 | 2018-01-23 | 电子科技大学 | 一种沟槽栅电荷储存型绝缘栅双极型晶体管及其制造方法 |
CN109037312A (zh) * | 2018-08-23 | 2018-12-18 | 惠州市乾野微纳电子有限公司 | 一种带有屏蔽栅的超结igbt及其制造方法 |
CN112259598A (zh) * | 2020-09-21 | 2021-01-22 | 倪炜江 | 一种沟槽型mosfet器件及其制备方法 |
-
2021
- 2021-09-23 CN CN202111116185.9A patent/CN113838916B/zh active Active
-
2022
- 2022-05-25 US US17/752,889 patent/US20230088637A1/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150372131A1 (en) * | 2014-06-24 | 2015-12-24 | François Hébert | Charged balanced devices with shielded gate trench |
WO2016014224A1 (en) * | 2014-07-25 | 2016-01-28 | United Silicon Carbide, Inc. | Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same |
CN105742346A (zh) * | 2016-04-26 | 2016-07-06 | 电子科技大学 | 双***沟槽栅电荷存储型rc-igbt及其制造方法 |
CN105702739A (zh) * | 2016-05-04 | 2016-06-22 | 深圳尚阳通科技有限公司 | 屏蔽栅沟槽mosfet器件及其制造方法 |
CN107623027A (zh) * | 2017-10-20 | 2018-01-23 | 电子科技大学 | 一种沟槽栅电荷储存型绝缘栅双极型晶体管及其制造方法 |
CN109037312A (zh) * | 2018-08-23 | 2018-12-18 | 惠州市乾野微纳电子有限公司 | 一种带有屏蔽栅的超结igbt及其制造方法 |
CN112259598A (zh) * | 2020-09-21 | 2021-01-22 | 倪炜江 | 一种沟槽型mosfet器件及其制备方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114093934A (zh) * | 2022-01-20 | 2022-02-25 | 深圳市威兆半导体有限公司 | 一种igbt器件及其制造方法 |
WO2023193370A1 (zh) * | 2022-04-08 | 2023-10-12 | 苏州东微半导体股份有限公司 | Igbt器件及其制造方法 |
CN114792734A (zh) * | 2022-06-22 | 2022-07-26 | 深圳芯能半导体技术有限公司 | 一种双沟槽碳化硅mosfet及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US20230088637A1 (en) | 2023-03-23 |
CN113838916B (zh) | 2023-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107623027B (zh) | 一种沟槽栅电荷储存型绝缘栅双极型晶体管及其制造方法 | |
CN107799582B (zh) | 一种沟槽栅电荷储存型绝缘栅双极型晶体管及其制造方法 | |
CN107799587B (zh) | 一种逆阻型igbt及其制造方法 | |
CN108321196B (zh) | 一种沟槽栅电荷存储型igbt及其制作方法 | |
CN107731897B (zh) | 一种沟槽栅电荷存储型igbt及其制造方法 | |
CN113838916B (zh) | 一种具有pmos电流嵌位的分离栅cstbt及其制作方法 | |
CN110600537B (zh) | 一种具有pmos电流嵌位的分离栅cstbt及其制作方法 | |
CN107731899B (zh) | 一种具有拑位结构的沟槽栅电荷储存型igbt器件及其制造方法 | |
CN108321193B (zh) | 一种沟槽栅电荷存储型igbt及其制作方法 | |
CN107731898B (zh) | 一种cstbt器件及其制造方法 | |
CN109713037B (zh) | 一种绝缘栅双极性晶体管器件及其制备方法 | |
CN110504310B (zh) | 一种具有自偏置pmos的ret igbt及其制作方法 | |
CN113838921B (zh) | 一种三维沟槽电荷存储型igbt及其制作方法 | |
CN113838917B (zh) | 一种三维分离栅沟槽电荷存储型igbt及其制作方法 | |
CN110444586B (zh) | 具有分流区的沟槽栅igbt器件及制备方法 | |
CN113838920B (zh) | 一种具有自偏置pmos的分离栅cstbt及其制作方法 | |
CN109166916B (zh) | 一种绝缘栅双极型晶体管及其制备方法 | |
CN112038401A (zh) | 一种绝缘栅双极性晶体管结构及其制备方法 | |
CN110473917B (zh) | 一种横向igbt及其制作方法 | |
CN110504260B (zh) | 一种具有自偏置pmos的横向沟槽型igbt及其制备方法 | |
CN109065608B (zh) | 一种横向双极型功率半导体器件及其制备方法 | |
CN108155230B (zh) | 一种横向rc-igbt器件及其制备方法 | |
CN113838918A (zh) | 具有载流子浓度增强的超结igbt器件结构及制作方法 | |
CN110943124A (zh) | Igbt芯片及其制造方法 | |
CN110504313B (zh) | 一种横向沟槽型绝缘栅双极晶体管及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |