WO2006004746A2 - Mosgated power semiconductor device with source field electrode - Google Patents

Mosgated power semiconductor device with source field electrode Download PDF

Info

Publication number
WO2006004746A2
WO2006004746A2 PCT/US2005/022917 US2005022917W WO2006004746A2 WO 2006004746 A2 WO2006004746 A2 WO 2006004746A2 US 2005022917 W US2005022917 W US 2005022917W WO 2006004746 A2 WO2006004746 A2 WO 2006004746A2
Authority
WO
WIPO (PCT)
Prior art keywords
source
electrode
source field
insulation
gate
Prior art date
Application number
PCT/US2005/022917
Other languages
French (fr)
Other versions
WO2006004746A3 (en
Inventor
Jianjun Cao
Dave Kent
Paul Harvey
Ritu Sodhi
Daniel M. Kinzer
Naresh Thapar
Andrew N. Sawle
Original Assignee
International Rectifier Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corporation filed Critical International Rectifier Corporation
Priority to JP2007518368A priority Critical patent/JP2008504697A/en
Priority to DE112005001434.7T priority patent/DE112005001434B4/en
Publication of WO2006004746A2 publication Critical patent/WO2006004746A2/en
Publication of WO2006004746A3 publication Critical patent/WO2006004746A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Definitions

  • the present invention relates to power semiconductor devices and more particularly to MOSgated power semiconductor devices.
  • the breakdown voltage and the operating resistance are important characteristics of a power semiconductor device.
  • the Rdson and the breakdown voltage of a power semiconductor device are inversely related. That is, the improvement in one adversely affects the other.
  • US Patent No. 5,998,833 proposes a trench type power semiconductor in which buried electrodes are disposed within the same trench as the gate electrodes in order to deplete the common conduction region under reverse voltage conditions, whereby the breakdown voltage of the device is improved.
  • the resistivity of the common conduction region can be improved without an adverse affect on the breakdown voltage.
  • the buried electrodes shown in US patent No. '833 are electrically connected to the source contact of the device remotely, which may limit the switching speed of the device. Furthermore, the device shown therein may require at least one additional masking step.
  • US Patent No. 6,649,975 ('975 patent) and US Patent No. 6,710,403 ('403 patent) both show power semiconductor devices which include trenches that are deeper than the gate trenches to support field electrodes that are electrically connected to the source contact.
  • the extra trenches increase the cell pitch and thus reduce cell density, which is undesirable.
  • a MOS gated power semiconductor device includes at least one gate electrode, and a source field electrode disposed within the same trench, the source field electrode being connected locally (i.e. within each unit cell) to obtain faster switching speed.
  • a device includes an active area having at least one active cell, the active cell including at least one source region, a source contact electrode connected to the source region, a source field electrode electrically connected to the source contact and an insulated gate electrode adjacent one side of the source field electrode and a base region, the source field electrode extending to a depth below a depth of the insulated gate electrode and a height above a height of the insulated gate electrode, wherein the source field electrode and the insulated gate electrode reside within a common trench.
  • a device exhibits low Rdson, high breakdown voltage, very low Qgd, and very low Qgd/Qgs ratio.
  • Figure 1 schematically illustrates a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention.
  • Figures 2A-2N schematically illustrate the intermediate structures obtained as a result of a process for fabricating a device according to the present invention.
  • a power semiconductor device is a trench type MOSFET, which in the active area thereof includes trench 10 in semiconductor body 56.
  • Trench 10 extends from the top 14 of semiconductor body 56 through source regions 16, and base region 18 into drift region 20.
  • Trench 10 is preferably stripe shaped, but may also be cellular.
  • a device includes: first gate electrode 22 adjacent one sidewall of trench 10 and spanning base region 18; second gate electrode 24 adjacent the opposing sidewall of trench 10 and spanning base region 18; first gate insulation 26 interposed between base region 18 and first gate electrode 22; second gate insulation 28 interposed between second gate electrode 24 and base region 18; and source field electrode 30 having a first portion disposed between first and second gate electrodes 22, 24 and a second portion disposed below first and second gate electrodes 22, 24.
  • First gate electrode 22 and second gate electrode 24 are electrically connected to one another so that they may be activated together, but are insulated from source field electrode 38. Specifically, the first portion of source field electrode 30 is insulated from first and second gate electrodes - A -
  • bottom insulation body 34 which is preferably thicker than first and second gate insulations 26, 28.
  • bottom insulation body 34 extends underneath first and second gate electrodes 22, 24.
  • the device further includes source contact 36 which is electrically connected to source regions 16, source field electrode 30, and high conductivity contact regions 38 in base region 18.
  • first insulation cap 40 is interposed between source contact 36 and first gate electrode 22, and second insulation cap 42 is interposed between source contact 36 and second gate electrode 24.
  • a device according to the present invention includes two insulated gate electrodes, and a source field electrode which is electrically connected to the source contact and disposed between the two gate electrodes and extends to a position below the gate electrodes.
  • the first portion of source field electrode 30 extends out of trench 10 and above surface 14 of semiconductor body 56.
  • caps 40, 42 may also extend out of trench 10 and above surface 14 of semiconductor body 56.
  • Semiconductor body 56 is preferably comprised of silicon, which is epitaxially formed over a semiconductor substrate 58, such as a silicon substrate.
  • the preferred embodiment further includes drain contact 43, which is in ohmic contact with substrate 58, whereby vertical conduction between source contact 36 and drain contact 43 is made possible.
  • source regions 16 would be of the same conductivity as drift region 20 and substrate 58, e.g. N-type, while base region 18 and high conductivity contact regions 38 are of another conductivity, e.g. P-type.
  • first and second gate electrodes 22, 24 and source field electrode 30 are composed of conductive polysilicon
  • gate insulations 26, 28, insulation caps 40, 42, insulation bodies 32, and bottom insulation body 34 are composed of silicon dioxide.
  • a device includes a termination structure disposed in the Termination Area which surrounds the Active Area.
  • the termination structure in the preferred embodiment includes termination trench 44, and field oxide 46 disposed within termination trench 44 adjacent at least the active area and the bottom of termination trench 44, and preferably adjacent both sidewalls of termination trench 44 and its bottom. Disposed adjacent to field oxide 44 is termination field plate 47.
  • Termination field plate 47 is preferably composed of conductive polysilicon. Termination field plate 47 is connected to source contact 36.
  • gate contact 48 is electrically connected to gate runner 50, which is in turn connected to gate electrodes 22, 24. Specifically, gate runner 50, is electrically connected to a second gate electrode disposed within termination trench 44, and thus electrically connected to all gate electrodes 22, 24 within the Active Area as well. Gate runner 50 is preferably composed of conductive polysilicon and resides over thick insulation body 52. [0020] In the preferred embodiment, source contact 36, drain contact 42 and gate contact 48 are composed of any suitable metal such as aluminum or aluminum silicon. [0021] A method for fabricating a device according to the present invention is next described with reference to Figures 2A-2N.
  • a layer of pad oxide 54 is grown over semiconductor body 56.
  • Semiconductor body 56 is preferably an epitaxial silicon of one conductivity, e.g. N-type, that is grown over a semiconductor substrate 58, which is preferably a silicon substrate of the same conductivity, but of lower resistivity (higher concentration of dopants).
  • a layer of silicon nitride 60 (Si 3 N 4 ) (which is an oxidation retardant material) is then deposited over pad oxide 54.
  • Si 3 N 4 60 layer and pad oxide 54 are patterned to form a trench mask over semiconductor body 56, and, in an etching step termination trench 44 and trench 10 are defined in semiconductor body 56.
  • a plurality of trenches 10 are formed in the Active Area of the device during this step. Thereafter, a sacrificial oxide is grown over the sidewalls and the bottom of termination trench 44 and trenches 10, etched, and then pad oxide is grown over the sidewalls and the bottom of termination trench 44 and trenches 10 to obtain the structure shown in Figure 2C.
  • polysilicon 62 is deposited over the structure shown in Figure 2C. Thereafter, polysilicon 62 is oxidized to form silicon dioxide 64 (SiO 2 ) as seen in Figure 2E. It should be noted that oxide 64 does not completely fill trenches 10 and termination trench 44, but that a space 65 remains in both trenches.
  • a conductive polysilicon body 66 is formed in each respective space 65 as seen in Figure 2F. Polysilicon bodies 66 may be formed by depositing polysilicon, doping the polysilicon and then etching the doped polysilicon to define bodies 66, or by in situ doping (i.e. doping while depositing the polysilicon). Thereafter, oxide 64 is removed to define bottom oxide 34 and field oxide 46 in termination trench 44 as seen in Figure 2G.
  • the polysilicon for forming gate electrodes 22, 24 and gate runner 50 is deposited and made conductive by implanting dopants after deposition or during deposition (i.e. in situ doping). Thereafter, using preferably photolithography, the deposited polysilicon is selectively removed to define gate electrodes 22, 24 and gate bus 50 as seen in Figure 21.
  • a low density oxide such as TEOS or the like is then deposited over the structure shown in Figure 21 and selectively etched to define insulation caps 40, 42 over gate electrodes 22, 24, and an opening for access by gate contact 48 to gate runner 50. It should be noted that an oxide from the top surface of source field electrodes 30 is removed to expose a top portion thereof as seen in Figure 2J.
  • Si 3 N 4 60 is removed from the Active Area, channel dopants are implanted and driven to form base region 18 and define drift region 20. Note that preferably no channel dopants are implanted beyond termination trench 44. Thereafter, a source mask is applied, pad oxide 54 is etched away form the Active Area to expose base region 18, and source dopants are implanted to form source implant regions 68 or as seen in Figure 2L.
  • oxide spacers are formed adjacent insulation caps 40, 42 to extend over source implant regions 68. Then, a portion of base region 18 is removed to form recesses 70 therein. It should be noted that the top surface of semiconductor body 56 is now the top surface 14 of source implant regions 68, and as seen in Figure 2M source field electrodes 30 rise above surface 14. Next, source implants in source implant regions 68 are driven in a diffusion drive to form source regions 16. Thereafter, dopants of the same conductivity as that of base region 18 are implanted at the bottom of recesses 70, and activated to form high conductivity contact regions 38 as seen in Figure 2N.
  • top metal is deposited and patterned to define source contact 36, and gate contact 48, and bottom metal is deposited to form drain contact 43, whereby a device according to the present invention as illustrated by Figure 1 is obtained.
  • the preferred embodiment shown herein is a power MOSFET. It should be noted that other power devices such as IGBTs, ACCUFETs and the like may be devised according to the principles disclosed herein without deviating from the scope and the spirit of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A power semiconductor device which includes a source field electrode (30), and at least one insulated gate electrode (24, 26) adjacent a respective side of the source field electrode (30), the source field electrode (30) and the gate electrode being disposed in a common trench (10), and a method for fabricating the device.

Description

MOSGATED POWER SEMICONDUCTOR DEVICE WΓΓH SOURCE FIELD ELECTRODE
RELATED APPLICATION
[0001] This application is based on and claims benefit of United States Provisional Application No. 60/582,898, filed on June 25, 2005, entitled TRENCH FET WITH DEEP SOURCE POLY ELECTRODE AND PROCESS OF MANUFACTURE, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.
FIELD OF INVENTION
[0002] The present invention relates to power semiconductor devices and more particularly to MOSgated power semiconductor devices.
BACKGROUND OF THE INVENTION
[0003] The breakdown voltage and the operating resistance (On resistance or Rdson) are important characteristics of a power semiconductor device. The Rdson and the breakdown voltage of a power semiconductor device are inversely related. That is, the improvement in one adversely affects the other. To overcome this problem, US Patent No. 5,998,833 proposes a trench type power semiconductor in which buried electrodes are disposed within the same trench as the gate electrodes in order to deplete the common conduction region under reverse voltage conditions, whereby the breakdown voltage of the device is improved. As a result, the resistivity of the common conduction region can be improved without an adverse affect on the breakdown voltage. [0004] The buried electrodes shown in US patent No. '833 are electrically connected to the source contact of the device remotely, which may limit the switching speed of the device. Furthermore, the device shown therein may require at least one additional masking step.
[0005] US Patent No. 6,649,975 ('975 patent) and US Patent No. 6,710,403 ('403 patent) both show power semiconductor devices which include trenches that are deeper than the gate trenches to support field electrodes that are electrically connected to the source contact. The devices illustrated by the '975 patent and the '403 both require additional masking steps for defining trenches that receive field electrodes, which may increase the cost of production. In addition, the extra trenches increase the cell pitch and thus reduce cell density, which is undesirable.
SUMMARY OF THE INVENTION
[0006] A MOS gated power semiconductor device according to the present invention includes at least one gate electrode, and a source field electrode disposed within the same trench, the source field electrode being connected locally (i.e. within each unit cell) to obtain faster switching speed.
[0007] A device according to the preferred embodiment of the present invention includes an active area having at least one active cell, the active cell including at least one source region, a source contact electrode connected to the source region, a source field electrode electrically connected to the source contact and an insulated gate electrode adjacent one side of the source field electrode and a base region, the source field electrode extending to a depth below a depth of the insulated gate electrode and a height above a height of the insulated gate electrode, wherein the source field electrode and the insulated gate electrode reside within a common trench. [0008] A device according to the present invention exhibits low Rdson, high breakdown voltage, very low Qgd, and very low Qgd/Qgs ratio. [0009] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 schematically illustrates a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention.
[0011] Figures 2A-2N schematically illustrate the intermediate structures obtained as a result of a process for fabricating a device according to the present invention.
DETAILED DESCRIPTION OF THE FIGURES
[0012] Referring to Figure 1, a power semiconductor device according to the preferred embodiment of the present invention is a trench type MOSFET, which in the active area thereof includes trench 10 in semiconductor body 56. Trench 10 extends from the top 14 of semiconductor body 56 through source regions 16, and base region 18 into drift region 20. Trench 10 is preferably stripe shaped, but may also be cellular.
[0013] A device according to an embodiment of the present invention includes: first gate electrode 22 adjacent one sidewall of trench 10 and spanning base region 18; second gate electrode 24 adjacent the opposing sidewall of trench 10 and spanning base region 18; first gate insulation 26 interposed between base region 18 and first gate electrode 22; second gate insulation 28 interposed between second gate electrode 24 and base region 18; and source field electrode 30 having a first portion disposed between first and second gate electrodes 22, 24 and a second portion disposed below first and second gate electrodes 22, 24. First gate electrode 22 and second gate electrode 24 are electrically connected to one another so that they may be activated together, but are insulated from source field electrode 38. Specifically, the first portion of source field electrode 30 is insulated from first and second gate electrodes - A -
22, 24 by respective insulation bodies 32, and insulated from drift region 20 by bottom insulation body 34, which is preferably thicker than first and second gate insulations 26, 28. Preferably, bottom insulation body 34 extends underneath first and second gate electrodes 22, 24.
[0014] The device further includes source contact 36 which is electrically connected to source regions 16, source field electrode 30, and high conductivity contact regions 38 in base region 18. To insulate gate electrodes 24, 26 from source contact 36, first insulation cap 40 is interposed between source contact 36 and first gate electrode 22, and second insulation cap 42 is interposed between source contact 36 and second gate electrode 24. Thus, a device according to the present invention includes two insulated gate electrodes, and a source field electrode which is electrically connected to the source contact and disposed between the two gate electrodes and extends to a position below the gate electrodes. [0015] In the preferred embodiment of the present invention, the first portion of source field electrode 30 extends out of trench 10 and above surface 14 of semiconductor body 56. It should be noted that caps 40, 42 may also extend out of trench 10 and above surface 14 of semiconductor body 56. [0016] Semiconductor body 56 is preferably comprised of silicon, which is epitaxially formed over a semiconductor substrate 58, such as a silicon substrate. The preferred embodiment further includes drain contact 43, which is in ohmic contact with substrate 58, whereby vertical conduction between source contact 36 and drain contact 43 is made possible. As would be readily apparent to a skilled person, source regions 16 would be of the same conductivity as drift region 20 and substrate 58, e.g. N-type, while base region 18 and high conductivity contact regions 38 are of another conductivity, e.g. P-type. Also, in the preferred embodiment, first and second gate electrodes 22, 24 and source field electrode 30 are composed of conductive polysilicon, and gate insulations 26, 28, insulation caps 40, 42, insulation bodies 32, and bottom insulation body 34 are composed of silicon dioxide. [0017] The features described so far belong to a single active cell of a device in the Active Area of a device according to the present invention. Although not shown, it should be appreciated that a device according to the present invention would include a plurality of active cells in the Active Area, which have not been shown here for the sake of brevity.
[0018] A device according to the preferred embodiment of the present invention includes a termination structure disposed in the Termination Area which surrounds the Active Area. The termination structure in the preferred embodiment includes termination trench 44, and field oxide 46 disposed within termination trench 44 adjacent at least the active area and the bottom of termination trench 44, and preferably adjacent both sidewalls of termination trench 44 and its bottom. Disposed adjacent to field oxide 44 is termination field plate 47. Termination field plate 47 is preferably composed of conductive polysilicon. Termination field plate 47 is connected to source contact 36.
[0019] Also seen in Figure 1 is gate contact 48. Gate contact 48 is electrically connected to gate runner 50, which is in turn connected to gate electrodes 22, 24. Specifically, gate runner 50, is electrically connected to a second gate electrode disposed within termination trench 44, and thus electrically connected to all gate electrodes 22, 24 within the Active Area as well. Gate runner 50 is preferably composed of conductive polysilicon and resides over thick insulation body 52. [0020] In the preferred embodiment, source contact 36, drain contact 42 and gate contact 48 are composed of any suitable metal such as aluminum or aluminum silicon. [0021] A method for fabricating a device according to the present invention is next described with reference to Figures 2A-2N.
[0022] Referring first to Figure 2A, a layer of pad oxide 54 is grown over semiconductor body 56. Semiconductor body 56 is preferably an epitaxial silicon of one conductivity, e.g. N-type, that is grown over a semiconductor substrate 58, which is preferably a silicon substrate of the same conductivity, but of lower resistivity (higher concentration of dopants). A layer of silicon nitride 60 (Si3 N4) (which is an oxidation retardant material) is then deposited over pad oxide 54. [0023] Referring next to Figure 2B, Si3N4 60 layer and pad oxide 54 are patterned to form a trench mask over semiconductor body 56, and, in an etching step termination trench 44 and trench 10 are defined in semiconductor body 56. It should be noted that although not shown a plurality of trenches 10 are formed in the Active Area of the device during this step. Thereafter, a sacrificial oxide is grown over the sidewalls and the bottom of termination trench 44 and trenches 10, etched, and then pad oxide is grown over the sidewalls and the bottom of termination trench 44 and trenches 10 to obtain the structure shown in Figure 2C.
[0024] Referring next to Figure 2D, polysilicon 62 is deposited over the structure shown in Figure 2C. Thereafter, polysilicon 62 is oxidized to form silicon dioxide 64 (SiO2) as seen in Figure 2E. It should be noted that oxide 64 does not completely fill trenches 10 and termination trench 44, but that a space 65 remains in both trenches. [0025] Next, a conductive polysilicon body 66 is formed in each respective space 65 as seen in Figure 2F. Polysilicon bodies 66 may be formed by depositing polysilicon, doping the polysilicon and then etching the doped polysilicon to define bodies 66, or by in situ doping (i.e. doping while depositing the polysilicon). Thereafter, oxide 64 is removed to define bottom oxide 34 and field oxide 46 in termination trench 44 as seen in Figure 2G.
[0026] Referring next to Figure 2H, the exposed portions of conductive polysilicon bodies 66 extending above bottom oxide 34 and field oxide 46 are oxidized, whereby insulation bodies 32 are formed over termination field plate 47 and source field electrodes 30. It should be noted that during this oxidation step the exposed portions of the sidewalls of trenches 10 and termination trench 44 are also oxidized to form gate insulations 26, 28.
[0027] Next, the polysilicon for forming gate electrodes 22, 24 and gate runner 50 is deposited and made conductive by implanting dopants after deposition or during deposition (i.e. in situ doping). Thereafter, using preferably photolithography, the deposited polysilicon is selectively removed to define gate electrodes 22, 24 and gate bus 50 as seen in Figure 21. A low density oxide such as TEOS or the like is then deposited over the structure shown in Figure 21 and selectively etched to define insulation caps 40, 42 over gate electrodes 22, 24, and an opening for access by gate contact 48 to gate runner 50. It should be noted that an oxide from the top surface of source field electrodes 30 is removed to expose a top portion thereof as seen in Figure 2J.
[0028] Next, Si3N4 60 is removed from the Active Area, channel dopants are implanted and driven to form base region 18 and define drift region 20. Note that preferably no channel dopants are implanted beyond termination trench 44. Thereafter, a source mask is applied, pad oxide 54 is etched away form the Active Area to expose base region 18, and source dopants are implanted to form source implant regions 68 or as seen in Figure 2L.
[0029] Referring next to Figure 2M, oxide spacers are formed adjacent insulation caps 40, 42 to extend over source implant regions 68. Then, a portion of base region 18 is removed to form recesses 70 therein. It should be noted that the top surface of semiconductor body 56 is now the top surface 14 of source implant regions 68, and as seen in Figure 2M source field electrodes 30 rise above surface 14. Next, source implants in source implant regions 68 are driven in a diffusion drive to form source regions 16. Thereafter, dopants of the same conductivity as that of base region 18 are implanted at the bottom of recesses 70, and activated to form high conductivity contact regions 38 as seen in Figure 2N.
[0030] Finally, top metal is deposited and patterned to define source contact 36, and gate contact 48, and bottom metal is deposited to form drain contact 43, whereby a device according to the present invention as illustrated by Figure 1 is obtained. [0031] The preferred embodiment shown herein is a power MOSFET. It should be noted that other power devices such as IGBTs, ACCUFETs and the like may be devised according to the principles disclosed herein without deviating from the scope and the spirit of the present invention.
[0032] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A power semiconductor device comprising: a semiconductor body having a common conduction region of one conductivity, and a base region of another conductivity, said semiconductor body including a first surface; a trench extending from said first surface through said base region and into said common conduction region, said trench including at least two opposing sidewalls and a bottom; a first gate insulation adjacent one of said sidewalls; a first gate electrode adjacent said first gate insulation and spanning said base region; a second gate insulation adjacent the other of said sidewalls; a second gate electrode adjacent said second gate insulation and spanning said base region; a source field electrode having a first portion and a second portion, said first portion of said source field electrode being disposed between said first and said second gate electrodes and insulated from the same by an insulation body, and said second portion of said source field electrode being disposed below said first portion and said gate electrodes; a source region adjacent each sidewall of said trench; and a source contact electrically connected to said source field electrode and said source regions.
2. A semiconductor device according to claim 1, further comprising a first insulation cap interposed between said source contact and said first gate electrode and a second insulation cap interposed between said source contact and said second gate electrode, wherein said source field electrode is disposed between said first insulation cap and said second insulation cap.
3. A semiconductor device according to claim 1, wherein said source field electrode extends out of said trench and above said first surface of said semiconductor body.
4. A semiconductor device according to claim 1, further comprising a bottom insulation body disposed between said second portion of said source field electrode and said sidewalls and said bottom of said trench.
5. A semiconductor device according to claim 4, wherein said bottom insulation body is thicker than said gate insulations.
6. A semiconductor device according to claim 5, wherein said insulation body is disposed below both gate electrodes.
7. A semiconductor device according to claim 1, wherein said source field electrode is comprised of conductive polysilicon.
8. A semiconductor device according to claim 1, wherein said gate electrodes are comprised of conductive polysilicon.
9. A semiconductor device according to claim 1, wherein said semiconductor body is comprised of epitaxial silicon.
10. A semiconductor device according to claim 9, wherein said epitaxial silicon is formed over a silicon substrate, and further comprising a drain contact ohmically connected to said silicon substrate.
11. A MOSgated power semiconductor device comprising: an active area including at least one active cell, said active cell including at least one source region, a source contact electrode connected to said source region, a source field electrode electrically connected to said source contact and an insulated gate electrode adjacent one side of said source field electrode and a base region, said source field electrode extending to a depth below a depth of said insulated gate electrode and a height above a height of said insulated gate electrode, wherein said source field electrode and said insulated gate electrode reside within a common trench.
12. A device according to claim 11, further comprising another insulated gate electrode residing within said common trench and adjacent another side of said source field electrode and said base region.
13. A device according to claim 12, wherein each insulated gate electrode includes a respective electrode said electrode being electrically connected to one another.
14. A device according to claim 11, further comprising an insulation body adjacent a bottom portion of said source field electrode.
15. A device according to claim 11, wherein said common trench is defined in a semiconductor body and extends from a top surface of said semiconductor body to a drift region within said semiconductor body, said source field electrode extending to a height above said top surface of said semiconductor body.
16. A device according to claim 11, further comprising a termination area adjacent said active area having a termination structure, said termination structure including a termination trench adjacent said active area.
17. A device according to claim 11, wherein said insulated gate electrode includes a conductive gate electrode and further comprising a gate bus electrically connected to said gate electrode and a gate contact.
18. A device according to claim 11, further comprising a drain contact.
19. A device according to claim 11, wherein said insulated gate electrode includes an insulation cap that extends over said source region.
20. A device according to claim 12, wherein each insulated gate electrode includes a respective insulation cap, said source field electrode extending to a height above said insulation caps.
PCT/US2005/022917 2004-06-25 2005-06-27 Mosgated power semiconductor device with source field electrode WO2006004746A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007518368A JP2008504697A (en) 2004-06-25 2005-06-27 Power semiconductor device provided with a MOS gate having a source field electrode
DE112005001434.7T DE112005001434B4 (en) 2004-06-25 2005-06-27 MOS gate-connected power semiconductor device with source field electrode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58289804P 2004-06-25 2004-06-25
US60/582,898 2004-06-25

Publications (2)

Publication Number Publication Date
WO2006004746A2 true WO2006004746A2 (en) 2006-01-12
WO2006004746A3 WO2006004746A3 (en) 2006-02-16

Family

ID=35783318

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/022917 WO2006004746A2 (en) 2004-06-25 2005-06-27 Mosgated power semiconductor device with source field electrode

Country Status (3)

Country Link
JP (1) JP2008504697A (en)
DE (1) DE112005001434B4 (en)
WO (1) WO2006004746A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006007096A1 (en) * 2006-02-15 2007-08-30 Infineon Technologies Austria Ag Metal oxide semiconductor field effect transistor, comprises drift zone having sub zone arranged between another sub zone and body zone, and drift zone is doped more strongly than sub zone
EP1909331A3 (en) * 2006-10-03 2009-04-15 Power Integrations, Inc. Trench-gate vertical MOSFET manufacturing method
CN107910268A (en) * 2017-11-17 2018-04-13 杭州士兰集成电路有限公司 Power semiconductor and its manufacture method

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090096027A1 (en) * 2007-10-10 2009-04-16 Franz Hirler Power Semiconductor Device
DE102009014418B3 (en) * 2009-03-26 2010-04-15 Heraeus Quarzglas Gmbh & Co. Kg Drawing method for the production of cylindrical components made of quartz glass
JP5627494B2 (en) * 2011-02-09 2014-11-19 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2012204529A (en) * 2011-03-24 2012-10-22 Toshiba Corp Semiconductor device and method of manufacturing the same
JP2012204590A (en) * 2011-03-25 2012-10-22 Toshiba Corp Semiconductor device and method of manufacturing the same
WO2016046901A1 (en) * 2014-09-24 2016-03-31 新電元工業株式会社 Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and method for designing silicon carbide semiconductor device
JP6426642B2 (en) * 2016-03-08 2018-11-21 株式会社東芝 Semiconductor device
IT201700057056A1 (en) 2017-05-25 2018-11-25 St Microelectronics Srl SELF-ALIGNED MANUFACTURING METHOD OF A VDMOS TRANSISTOR, AND AUTO-LINKED VDMOS TRANSISTOR

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030132460A1 (en) * 2001-12-18 2003-07-17 Fuji Electric Co., Ltd. Semiconductor device and semiconductor device manufacturing method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5326711A (en) * 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
US5998833A (en) 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
DE10038177A1 (en) * 2000-08-04 2002-02-21 Infineon Technologies Ag Semiconductor switching element with two control electrodes which can be controlled by means of a field effect
AU2002230482A1 (en) 2000-11-16 2002-05-27 Silicon Wireless Corporation Discrete and packaged power devices for radio frequency (rf) applications and methods of forming same
JP3709814B2 (en) * 2001-01-24 2005-10-26 株式会社豊田中央研究所 Semiconductor device and manufacturing method thereof
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6635544B2 (en) 2001-09-07 2003-10-21 Power Intergrations, Inc. Method of fabricating a high-voltage transistor with a multi-layered extended drain structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030132460A1 (en) * 2001-12-18 2003-07-17 Fuji Electric Co., Ltd. Semiconductor device and semiconductor device manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006007096A1 (en) * 2006-02-15 2007-08-30 Infineon Technologies Austria Ag Metal oxide semiconductor field effect transistor, comprises drift zone having sub zone arranged between another sub zone and body zone, and drift zone is doped more strongly than sub zone
DE102006007096B4 (en) * 2006-02-15 2008-07-17 Infineon Technologies Austria Ag Compensating structure and edge termination MOSFET and method of making the same
EP1909331A3 (en) * 2006-10-03 2009-04-15 Power Integrations, Inc. Trench-gate vertical MOSFET manufacturing method
EP2346081A1 (en) * 2006-10-03 2011-07-20 Power Integrations, Inc. Trench-gate vertical MOSFET manufacturing method
CN107910268A (en) * 2017-11-17 2018-04-13 杭州士兰集成电路有限公司 Power semiconductor and its manufacture method
CN107910268B (en) * 2017-11-17 2023-12-26 杭州士兰集昕微电子有限公司 Power semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
DE112005001434B4 (en) 2018-06-07
DE112005001434T5 (en) 2007-05-16
WO2006004746A3 (en) 2006-02-16
JP2008504697A (en) 2008-02-14

Similar Documents

Publication Publication Date Title
US7482654B2 (en) MOSgated power semiconductor device with source field electrode
US7411266B2 (en) Semiconductor device having trench charge compensation regions and method
US7361555B2 (en) Trench-gate transistors and their manufacture
US7253477B2 (en) Semiconductor device edge termination structure
US10355125B2 (en) Electrode contact structure for semiconductor device
US7176524B2 (en) Semiconductor device having deep trench charge compensation regions and method
WO2006004746A2 (en) Mosgated power semiconductor device with source field electrode
US7943466B2 (en) Method of forming a semiconductor device having sub-surface trench charge compensation regions
US7285823B2 (en) Superjunction semiconductor device structure
US7579650B2 (en) Termination design for deep source electrode MOSFET
KR100714198B1 (en) Mos-gated device having a buried gate and process for forming same
US8969953B2 (en) Method of forming a self-aligned charge balanced power DMOS
US7371641B2 (en) Method of making a trench MOSFET with deposited oxide
US7998808B2 (en) Semiconductor device fabrication using spacers
US20060060916A1 (en) Power devices having trench-based source and gate electrodes
US7494876B1 (en) Trench-gated MIS device having thick polysilicon insulation layer at trench bottom and method of fabricating the same
US8884367B2 (en) MOSgated power semiconductor device with source field electrode
US6639276B2 (en) Power MOSFET with ultra-deep base and reduced on resistance
US6518129B2 (en) Manufacture of trench-gate semiconductor devices
EP1162665A2 (en) Trench gate MIS device and method of fabricating the same
CN113690303A (en) Semiconductor device and method for manufacturing the same
EP4362068A1 (en) Transistor device and method of fabricating contacts to a semiconductor substrate

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1120050014347

Country of ref document: DE

WWE Wipo information: entry into national phase

Ref document number: 2007518368

Country of ref document: JP

RET De translation (de og part 6b)

Ref document number: 112005001434

Country of ref document: DE

Date of ref document: 20070516

Kind code of ref document: P

REG Reference to national code

Ref country code: DE

Ref legal event code: 8607

122 Ep: pct application non-entry in european phase