CN113452361A - Universal serial bus signal output circuit with reverse flow current prevention mechanism - Google Patents
Universal serial bus signal output circuit with reverse flow current prevention mechanism Download PDFInfo
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Abstract
A universal serial bus signal output circuit with a back-flow current prevention mechanism, comprising: the switching circuit and the first and second voltage pull-down circuits. The switch circuit is conducted when the switch control end receives the first high-state voltage, so that signal output from the signal input end to the signal output end is carried out. The first voltage pull-down circuit includes: a passive element high-pass filter circuit and a discharge circuit. The passive element high-pass filter circuit couples the output end voltage of the signal output end to the pull-down control end. The discharging circuit is conducted when the voltage of the pull-down control end is larger than a preset level so as to discharge the switch control end and pull down the switch control end to a second high-state voltage. The second voltage pull-down circuit pulls down the switch control terminal to a low-state voltage when the output terminal voltage is greater than the reference voltage and has no burst.
Description
Technical Field
The present invention relates to a universal serial bus transmission technology, and more particularly, to a universal serial bus signal output circuit having a reverse current prevention mechanism and an operating method thereof.
Background
The usb is a serial port bus standard for connecting a computer system and an external device, and is also a specification of an input/output interface. In recent years, the Type-C usb standard has attracted attention because it is unnecessary to consider the directivity of the plug, and the charging speed is increased by greatly increasing the transmission speed and increasing the supported charging power.
However, even if the plug is no longer directional, the user may still deviate from the correct pin-to-pin position during use, and the signal output circuit may erroneously touch the pin with higher voltage. In such a situation, if there is no fast reaction mechanism, the high voltage will generate a backward flowing large current, which may cause damage to the signal output circuit or other circuits related to the signal output circuit.
Disclosure of Invention
In view of the problems of the prior art, it is an object of the present invention to provide a Universal Serial Bus (USB) signal output circuit having a reverse current (reverse current) prevention mechanism and a method for operating the same, so as to improve the prior art.
The invention aims to provide a universal serial bus signal output circuit with a reverse current prevention mechanism and an operation method thereof.
The invention includes a universal serial bus signal output circuit with a reverse current prevention mechanism, one embodiment of which comprises: the circuit comprises a switch circuit, a first voltage pull-down circuit and a second voltage pull-down circuit. The switch circuit comprises a switch control end which is configured to be conducted when the switch control end receives a first high-state voltage so as to output a signal from the signal input end to the signal output end. The first voltage pull-down circuit includes: a passive element high-pass filter circuit and a discharge circuit. The passive element high-pass filter circuit is configured to couple an output terminal voltage of the signal output terminal to the pull-down control terminal. The discharge circuit is configured to be conducted when the voltage of the pull-down control end is greater than a preset level so as to discharge the switch control end and pull down the switch control end to a second high-state voltage which is less than the first high-state voltage. The second voltage pull-down circuit is configured to compare the output voltage with a reference voltage, determine whether the output voltage has a surge, and pull down the switch control terminal to a low-state voltage when the output voltage is greater than the reference voltage and does not have a surge.
The invention also discloses an operation method of the universal serial bus signal output circuit with the reverse current prevention mechanism, which is applied to the universal serial bus signal output circuit, and one embodiment of the method comprises the following steps: the switch circuit is conducted when the switch control end receives the first high-state voltage, so that signal output from the signal input end to the signal output end is carried out; enabling a passive element high-pass filter circuit of the first voltage pull-down circuit to couple the output end voltage of the signal output end to the pull-down control end; the discharging circuit of the first voltage pull-down circuit is conducted when the voltage of the pull-down control end is larger than a preset level, so that the switch control end is discharged and pulled down to a second high-state voltage smaller than the first high-state voltage; the second voltage pull-down circuit compares the output end voltage with a reference voltage and judges whether the output end voltage has a surge; and the second voltage pull-down circuit pulls down the switch control terminal to a low-state voltage when the output terminal voltage is greater than the reference voltage and has no burst.
The features, operation and effects of the present invention will be described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a USB signal output circuit with a reverse current prevention mechanism according to an embodiment of the present invention;
FIG. 2 is a diagram showing voltage versus current versus time for a plurality of circuit nodes of a USB signal output circuit, in accordance with an embodiment of the present invention; and
FIG. 3 is a flow chart of a method of operating a USB signal output circuit with a reverse current prevention mechanism according to an embodiment of the present invention.
Detailed Description
The invention aims to provide a universal serial bus signal output circuit with a reverse current prevention mechanism and an operation method thereof.
Referring to fig. 1, fig. 1 is a schematic diagram of a usb signal output circuit 100 with a reverse current prevention mechanism according to an embodiment of the present invention.
The usb signal output circuit 100 may be disposed in an electronic device to output, for example, but not limited to, a power signal or a data signal when electrically coupled to an external electronic device. In one embodiment, the USB is of Type-C specification.
The universal serial bus signal output circuit 100 includes: a switching circuit 110, a first voltage pull-down circuit 120, and a second voltage pull-down circuit 130.
In one embodiment, the switch circuit 110 includes a first N-type transistor MT1 and a second N-type transistor MT 2. The gate of the first N-type transistor MT1 is electrically coupled to the switch control terminal SC, and the source thereof is electrically coupled to the signal input terminal SI. The gate of the second N-type transistor MT2 is electrically coupled to the switch control terminal SC, and the source thereof is electrically coupled to the signal output terminal SO. The drains of the first and second N-type transistors MT1 and MT2 are electrically coupled to each other.
In one embodiment, the universal serial bus signal output circuit 100 further includes a switch control circuit 140. The switch control terminal SC receives the control signal CS from the switch control circuit 140 to control the switch circuit 110 to be turned on or off according to the voltage state thereof.
In more detail, when the control signal CS is at the first high-state voltage, the voltage Vcp of the switch control terminal SC receives the high-state voltage, SO as to drive the gates of the first N-type transistor MT1 and the second N-type transistor MT2 to turn on the switch circuit 110, and output a signal from the signal input terminal SI to the signal output terminal SO. When the control signal CS is at the low voltage level, the voltage Vcp at the switch control terminal SC will be at the low voltage level, and the gates of the first N-type transistor MT1 and the second N-type transistor MT2 will receive the low voltage level and turn off, so that the switch circuit 110 is turned off.
In one embodiment, the first high state voltage output by the control signal CS may be, for example, but not limited to, 10 volts, and the low state voltage may be, for example, but not limited to, 0 volts. The signal input SI may be electrically coupled to a voltage source having an input voltage Vconn of, for example, but not limited to, 5 volts. The output terminal voltage Vcc of the signal output terminal SO will approach but be slightly less than 5 volts through the conduction and voltage drop of the switch circuit 110.
In some cases, the user may mistakenly touch the signal output terminal SO to another pin with a high voltage due to improper operation, which may cause the output terminal voltage Vcc to rise rapidly. Under such a situation, the first voltage pull-down circuit 120 provides a fast response mechanism to reduce the conduction degree of the switch circuit 110, so as to prevent the rising output voltage Vcc from causing the large current backflow to cause the damage of the switch circuit 110.
The second voltage pull-down circuit 130 provides a relatively slow response mechanism to determine whether the rising output voltage Vcc is only a surge, so as to further turn off the switch circuit 110 if it is determined that the surge is not occurring, or to resume the operation of the switch circuit 110 if it is determined that the surge occurs.
FIG. 2 is a waveform diagram of voltage and current versus time of a plurality of circuit nodes of the USB signal output circuit 100 according to an embodiment of the present invention.
The structure and operation of the first pull-down circuit 120 and the second pull-down circuit 130 will be described with reference to fig. 1 and 2.
The first voltage pull-down circuit 120 includes: a passive component high pass filter circuit 150 and a discharge circuit 160.
The passive element high-pass filter circuit 150 couples the output terminal voltage Vcc of the signal output terminal SO to the pull-down control terminal PC. In one embodiment, the passive high pass filter circuit 150 includes a capacitor C1 and a resistor R1. The capacitor C1 is electrically coupled between the signal output terminal SO and the pull-down control terminal PC. The resistor R1 is electrically coupled between the pull-down control terminal PC and the ground terminal GND.
Before time point T1 of fig. 2, the switch circuit 110 is in a conducting state for normal operation. Therefore, the voltage Vcp of the switch control terminal SC is 10 volts of the first high-state voltage. The output terminal voltage Vcc of the signal output terminal SO is maintained at about 5 volts. The voltage Vpc at the control terminal PC is pulled low at 0 volts due to the resistance R1 being discharged continuously.
At time T1 in fig. 2, the signal output terminal SO generates a false touch condition, which causes the output terminal voltage Vcc to rise sharply, for example, but not limited to 24 volts. Since the passive element high-pass filter circuit 150 has a fast response time, the boosted output terminal voltage Vcc can be quickly coupled to the pull-down control terminal PC at a time almost equivalent to the time point T1.
In one embodiment, the usb signal output circuit 100 may include a diode circuit 170 electrically coupled to the pull-down control terminal PC and the ground terminal GND for limiting the voltage of the pull-down control terminal PC to a maximum value, such as but not limited to 5 volts or less, to ensure that the voltage Vpc of the pull-down control terminal PC does not directly receive an excessively high voltage, thereby providing a protection mechanism for the discharge circuit 160 that subsequently receives the voltage Vpc. In various embodiments, the diode circuit 170 may include different numbers of diode devices to achieve different voltage limits, as desired.
The discharging circuit 160 is turned on when the voltage Vpc of the pull-down control terminal PC is greater than a predetermined level to discharge the switch control terminal SC and pull down the voltage Vcp to a second high-state voltage that is less than the first high-state voltage. In one embodiment, the discharge circuit 160 includes an N-type transistor M1 and a P-type transistor M2.
The gate of the N-type transistor M1 is electrically coupled to the pull-down control terminal PC, and the source thereof is electrically coupled to the ground terminal GND. The gate of the P-type transistor M2 receives a driving voltage less than the first high-state voltage. In one embodiment, the gate of the P-type transistor M2 can be connected to a voltage source having an input voltage Vconn, such that the driving voltage is equivalent to the input voltage Vconn. For ease of illustration, the drive voltage is indicated directly in fig. 1 at Vconn.
The drain of the P-type transistor M2 is electrically coupled to the drain of the N-type transistor M1, and the source thereof is electrically coupled to the switch control terminal SC.
Before the time point T1 of fig. 2, the N-type transistor M1 is turned off because the voltage Vpc of the pull-down control terminal PC is a low voltage. The source of the P-type transistor M2 receives the voltage Vcp at the switch control terminal SC with the first high-state voltage, the gate receives the driving voltage, and the voltage difference between the source and the gate makes the P-type transistor M2 be in the conducting state. However, since the turning off of the N-type transistor M1 makes the voltage at the drain of the P-type transistor M2 rise to be equal to the driving voltage, the P-type transistor M2 is also turned off, so as to ensure that the voltage across the drain and the source of the N-type transistor M1 is not too large and is not damaged.
At the time point T1 in fig. 2, the voltage Vpc of the control terminal PC is pulled down and increased by the coupling of the passive element high-pass filter circuit 150, so that the N-type transistor M1 is turned on, and the voltages of the drains of the N-type transistor M1 and the P-type transistor M2 are further pulled down, so that the P-type transistor M2 starts to be turned on, the switch control terminal SC is discharged, and the voltage Vcp thereof starts to fall.
At time T2 in fig. 2, when the voltage Vcp at the switch control terminal SC drops to a level close to the driving voltage received by the gate of the P-type transistor M2 plus the threshold voltage of the P-type transistor M2, the P-type transistor M2 cannot be turned on any more. Therefore, after the P-type transistor M2 is turned off, the voltage Vcp of the switch control terminal SC will reach the second high-state voltage smaller than the first high-state voltage. In one embodiment, the second high state voltage is about 6 volts, which is the sum of the driving voltage (e.g., but not limited to 5 volts) and the threshold voltage (e.g., but not limited to 1 volt) of the P-type transistor M2.
By discharging the switch control terminal SC through the above mechanism, the voltage Vcp at the second high-state voltage will greatly decrease the conduction degree of the first N-type transistor MT1 and the second N-type transistor MT2, and thus the reverse flow of large current will not be generated. As shown in fig. 2, the backward current Icc generated between the switch circuits 110 generates only a slight surge from time T1 to time T2, and then drops to a relatively low level due to the above-mentioned mechanism.
In one embodiment, the universal serial bus signal output circuit 100 further includes a passive component low pass filter circuit 180. The gate of the P-type transistor M2 actually receives the driving voltage through the passive low pass filter circuit 180. In one embodiment, the passive low pass filter circuit 180 includes a resistor R2 and a capacitor C2. The resistor R2 is electrically coupled between a voltage source for driving voltage and the gate of the P-type transistor M2. The capacitor C2 is electrically coupled between the gate of the P-type transistor M2 and the ground GND.
In the present embodiment, since the gate of the P-type transistor M2 is electrically coupled to the voltage source having the input terminal voltage Vconn, when the signal output terminal SO touches the high voltage by mistake, the instantaneously raised output terminal voltage Vcc may still cause the input terminal voltage Vconn to be temporarily raised through the turned-on switch circuit 110. Therefore, the parasitic element low pass filter circuit 180 can couple the input voltage Vconn to the gate of the P-type transistor M2 at a slower speed, thereby preventing the P-type transistor M2 from being damaged.
The second voltage pull-down circuit 130 includes: a comparator 190 and a pull-down control circuit 195.
At time point T3 of fig. 2, the comparator 190 compares the output terminal voltage Vcc with the reference voltage Vref to generate the comparison result CR. Since the comparator 190 is an active circuit and the response time is slow, the time point T3 generated by the comparison result CR is later than the time point T1 when the passive high-pass filter circuit 150 couples the output terminal voltage Vcc to the pull-down control terminal PC.
The pull-down control circuit 195 determines whether the output terminal voltage Vcc is greater than the reference voltage Vref and whether the output terminal voltage Vcc has a surge according to the comparison result CR. In one embodiment, the occurrence of the glitch may be set to a condition where the output terminal voltage Vcc exceeds the predetermined voltage value only within a predetermined time range.
At time T4 of fig. 2, when the output terminal voltage Vcc is greater than the reference voltage Vref and has no glitch, the pull-down control circuit 195 may pull down the voltage Vcp of the switch control terminal SC to a low-state voltage through a mechanism such as, but not limited to, discharging. In one embodiment, the glitch elimination interval from the time point T3 when the comparison result CR is generated to the time point T4 when the glitch determination is completed is, for example, but not limited to, 20 ns.
In one embodiment, the pull-down control circuit 195 may also control the switch control circuit 140 to stop outputting the control signal CS with the first high-state voltage by transmitting a signal (not shown), and to switch to output the low-state voltage, so as to further ensure the switch circuit 110 is turned off.
In one embodiment, pull-down control circuit 195 may include logic circuitry to make the determination and a discharge circuit (not shown) to discharge to implement the above-described operating mechanism. The present invention is not limited to a particular circuit configuration.
When the rising and non-surge output terminal voltage Vcc gradually decays with time, the first voltage pull-down circuit 120 will turn off the N-type transistor M1 due to the voltage drop of the passive device high-pass filter circuit 150 coupled to the pull-down control terminal PC, and further turn off the P-type transistor M2 due to the voltage rise of the drain of the N-type transistor M1 and the drain of the P-type transistor M2, thereby stopping the conduction of the discharge circuit 160. The pull-down control circuit 195 may also determine that the output terminal voltage Vcc is not greater than the reference voltage Vref according to the comparison result CR of the comparator 190, stop pulling down the voltage Vcp of the switch control terminal SC, and control the switch control circuit 140 to resume outputting the control signal CS with the first high-state voltage. The switching circuit 110 can restore the original conduction level and operate normally.
On the other hand, when the output terminal voltage Vcc is greater than the reference voltage Vref and has a glitch, the pull-down control circuit 195 may not perform the voltage pull-down mechanism, and may enable the switch control circuit 140 to continuously output the control signal CS having the first high-state voltage. At this time, the first voltage pull-down circuit 120 also stops the conduction of the discharge circuit 160 after the voltage of the surge attenuates, so that the voltage Vcp of the switch control terminal SC is returned to the first high-state voltage from the second high-state voltage, and further the switch circuit 110 recovers the original conduction degree and operates normally.
Therefore, the universal serial bus signal output circuit can quickly respond to the voltage rise of the signal output end by the passive element high-pass filter circuit through the arrangement of the first voltage pull-down circuit, and drives the discharge circuit to adjust and reduce the voltage of the control end of the switch so as to reduce the conduction degree of the switch circuit and avoid the generation of backward flow large current. The second voltage pull-down circuit with a slower response speed further provides a surge judgment mechanism to determine whether to completely turn off the switch circuit. The switching circuit and other circuits associated with the signal input will be protected.
It should be noted that the circuit structure and the voltage values are only examples. In other embodiments, the reverse current prevention mechanism can be implemented by using a circuit structure and other voltage values that can achieve the same function. The present invention is not limited to the above-described embodiments.
Please refer to fig. 3. FIG. 3 is a flowchart of a method 300 for operating a USB signal output circuit with a reverse current prevention mechanism according to an embodiment of the present invention.
In addition to the aforementioned devices, the present invention further discloses a method 300 for operating a usb signal output circuit with a reverse current prevention mechanism, which is applied to, for example, but not limited to, the usb signal output circuit 100 of fig. 1. One embodiment of a method 300 for operating a universal serial bus signal output circuit is shown in FIG. 3 and includes the steps of:
s310: the switch circuit 110 is turned on when the switch control terminal SC receives the first high-state voltage, SO as to output the signal from the signal input terminal SI to the signal output terminal SO.
S320: the passive high pass filter circuit 150 of the first voltage pull-down circuit 120 is enabled to couple the output terminal voltage Vcc of the signal output terminal SO to the pull-down control terminal PC.
S330: the discharging circuit 160 of the first voltage pull-down circuit 120 is turned on when the voltage Vpc of the pull-down control terminal PC is greater than a predetermined level, so as to discharge the switch control terminal SC and pull down to a second high-state voltage smaller than the first high-state voltage.
S340: the second voltage pull-down circuit 130 compares the output terminal voltage Vcc with the reference voltage Vref and determines whether the output terminal voltage Vcc has a surge.
S350: when the output terminal voltage Vcc is greater than the reference voltage Vref and no glitch exists, the second voltage pull-down circuit 130 pulls down the switch control terminal SC to a low-state voltage.
S360: the second voltage pull-down circuit 130 does not pull down the switch control terminal SC to a low voltage when the output terminal voltage Vcc is not greater than the reference voltage Vref or has a glitch.
It should be noted that the above-described embodiments are only examples. In other embodiments, variations can be made by one of ordinary skill in the art without departing from the spirit of the invention.
In summary, the usb signal output circuit and the operating method thereof according to the present invention can rapidly adjust the voltage of the switch control terminal to avoid the generation of the backward flow large current when the voltage of the signal output terminal rises by setting the first voltage pull-down circuit, thereby providing a protection mechanism for the switch circuit.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
Description of the reference numerals
100 universal serial bus signal output circuit
110 switching circuit
120 first voltage pull-down circuit
130 second voltage pull-down circuit
140 switch control circuit
150 passive element high-pass filter circuit
160 discharge circuit
170 diode circuit
180 passive element low-pass filter circuit
190: comparator
195 pull-down control circuit
300 method for operating universal serial bus signal output circuit
S310-S360 step
C1 capacitor
C2 capacitor
CR comparison result
CS control signal
GND (ground)
Icc reverse current
M1N type transistor
M2P-type transistor
MT1 first N-type transistor
MT2 second N-type transistor
Pull-down control terminal for PC
R1 resistance
R2 resistance
SC switch control terminal
SI signal input terminal
SO signal output terminal
Vcc is the voltage at the output terminal
Input terminal voltage Vconn
Vcp voltage
Vpc voltage
Vref-reference Voltage
T1-T4 time points
Claims (10)
1. A universal serial bus signal output circuit with a back-flow current prevention mechanism, comprising:
the switch circuit comprises a switch control end and a switch control end, wherein the switch control end is configured to be conducted when receiving a first high-state voltage so as to output a signal from a signal input end to a signal output end;
a first voltage pull-down circuit comprising:
a passive element high-pass filter circuit configured to couple an output terminal voltage of the signal output terminal to a pull-down control terminal; and
the discharge circuit is configured to be conducted when the voltage of the pull-down control end is greater than a preset level so as to discharge the switch control end and pull down the switch control end to a second high-state voltage which is less than the first high-state voltage; and
and the second voltage pull-down circuit is configured to compare the voltage at the output end with a reference voltage, judge whether the voltage at the output end has a surge or not, and pull down the switch control end to a low-state voltage when the voltage at the output end is greater than the reference voltage and does not have the surge.
2. The USB signal output circuit of claim 1, further comprising a diode circuit electrically coupled to the pull-down control terminal and a ground terminal to limit the voltage at the pull-down control terminal to below a maximum value.
3. The universal serial bus signal output circuit of claim 1, wherein the discharge circuit further comprises:
an N-type transistor including a first gate, a first drain, and a first source, wherein the first gate is electrically coupled to the pull-down control terminal, and the first source is electrically coupled to a ground terminal; and
a P-type transistor including a second gate, a second drain and a second source, wherein the second gate is configured to receive a driving voltage smaller than the first high-state voltage, the second drain is electrically coupled to the first drain, and the second source is electrically coupled to the switch control terminal.
4. The USB signal output circuit of claim 3, wherein when the N-type transistor is turned on, the P-type transistor is turned on according to a voltage difference between the second source and the second gate to pull the switch control terminal down to the second high-state voltage.
5. The USB signal output circuit of claim 3, wherein when the N-type transistor is turned off and the P-type transistor is turned on, the voltages of the first drain and the second drain are raised to be equal to the driving voltage to turn off the P-type transistor.
6. The universal serial bus signal output circuit of claim 3, wherein the second gate of the P-type transistor receives the driving voltage through a passive element low pass filter circuit.
7. The universal serial bus signal output circuit of claim 1, wherein the second voltage pull-down circuit comprises:
a comparator configured to compare the output voltage with the reference voltage to generate a comparison result; and
and the pull-down control circuit is configured to judge whether the output end voltage is greater than the reference voltage or not and whether the output end voltage has the surge or not according to the comparison result so as to pull down the switch control end to the low-state voltage when the output end voltage is greater than the reference voltage and does not have the surge.
8. The universal serial bus signal output circuit of claim 1, wherein the switch circuit comprises:
a first N-type transistor including a third gate, a third drain, and a third source, wherein the third gate is electrically coupled to the switch control terminal, and the third source is electrically coupled to the signal input terminal; and
a second N-type transistor including a fourth gate, a fourth drain and a fourth source, wherein the fourth gate is electrically coupled to the switch control terminal, the fourth drain is electrically coupled to the third drain, and the fourth source is electrically coupled to the signal output terminal.
9. The universal serial bus signal output circuit of claim 1, further comprising a switch control circuit configured to output the first high state voltage to the switch control terminal, wherein the second voltage pull-down circuit further causes the control circuit to stop outputting the first high state voltage when the output terminal voltage is greater than the reference voltage and does not have the glitch.
10. A method for operating a universal serial bus signal output circuit with a reverse current prevention mechanism is applied to the universal serial bus signal output circuit and comprises the following steps:
the switch circuit is conducted when the switch control end receives the first high-state voltage, so that signal output from the signal input end to the signal output end is carried out;
enabling a passive element high-pass filter circuit of a first voltage pull-down circuit to couple the output end voltage of the signal output end to a pull-down control end;
enabling a discharge circuit of the first voltage pull-down circuit to be conducted when the voltage of the pull-down control end is greater than a preset level, so as to discharge the switch control end and pull down the voltage to a second high-state voltage smaller than the first high-state voltage;
enabling a second voltage pull-down circuit to compare the voltage at the output end with a reference voltage and judge whether the voltage at the output end has a surge; and
and the second voltage pull-down circuit pulls down the switch control terminal to a low-state voltage when the output terminal voltage is greater than the reference voltage and the burst wave is not existed.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102684670A (en) * | 2012-05-29 | 2012-09-19 | 上海山景集成电路技术有限公司 | High speed signal output circuit with zero reverse current |
| CN103746684A (en) * | 2014-01-16 | 2014-04-23 | 上海斐讯数据通信技术有限公司 | System and method for preventing power supply from flowing backwards |
| CN105915056A (en) * | 2016-05-30 | 2016-08-31 | 武汉新芯集成电路制造有限公司 | Boost circuit preventing reverse current |
| CN105988963A (en) * | 2015-02-09 | 2016-10-05 | 深圳市优笔触控科技有限公司 | External power supply identification circuit for large current touch equipment and electronic signature screen |
| CN106160715A (en) * | 2015-04-17 | 2016-11-23 | 瑞昱半导体股份有限公司 | The multiplexer that switching switchs and comprises it |
| CN207074996U (en) * | 2017-04-19 | 2018-03-06 | 深圳市云顶信息技术有限公司 | Interface circuit and electronic equipment |
| WO2018086458A1 (en) * | 2016-11-11 | 2018-05-17 | 中兴通讯股份有限公司 | Usb interface circuit, method and device for usb interface implementation, and computer storage medium |
| CN110853571A (en) * | 2019-01-14 | 2020-02-28 | 友达光电股份有限公司 | Light emission control circuit |
-
2020
- 2020-03-27 CN CN202010228045.XA patent/CN113452361B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102684670A (en) * | 2012-05-29 | 2012-09-19 | 上海山景集成电路技术有限公司 | High speed signal output circuit with zero reverse current |
| CN103746684A (en) * | 2014-01-16 | 2014-04-23 | 上海斐讯数据通信技术有限公司 | System and method for preventing power supply from flowing backwards |
| CN105988963A (en) * | 2015-02-09 | 2016-10-05 | 深圳市优笔触控科技有限公司 | External power supply identification circuit for large current touch equipment and electronic signature screen |
| CN106160715A (en) * | 2015-04-17 | 2016-11-23 | 瑞昱半导体股份有限公司 | The multiplexer that switching switchs and comprises it |
| CN105915056A (en) * | 2016-05-30 | 2016-08-31 | 武汉新芯集成电路制造有限公司 | Boost circuit preventing reverse current |
| WO2018086458A1 (en) * | 2016-11-11 | 2018-05-17 | 中兴通讯股份有限公司 | Usb interface circuit, method and device for usb interface implementation, and computer storage medium |
| CN207074996U (en) * | 2017-04-19 | 2018-03-06 | 深圳市云顶信息技术有限公司 | Interface circuit and electronic equipment |
| CN110853571A (en) * | 2019-01-14 | 2020-02-28 | 友达光电股份有限公司 | Light emission control circuit |
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