CN113410199A - 半导体存储装置及其制造方法 - Google Patents

半导体存储装置及其制造方法 Download PDF

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CN113410199A
CN113410199A CN202010805083.7A CN202010805083A CN113410199A CN 113410199 A CN113410199 A CN 113410199A CN 202010805083 A CN202010805083 A CN 202010805083A CN 113410199 A CN113410199 A CN 113410199A
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metal pad
memory device
semiconductor memory
array
metal
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CN113410199B (zh
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若月启
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式提供一种能够减少金属焊盘彼此的接合不良的半导体存储装置及其制造方法。一实施方式的半导体存储装置具备：阵列芯片，具有存储单元阵列；电路芯片，具有与存储单元电连接的电路；及金属焊盘，将阵列芯片与电路芯片接合。金属焊盘含有杂质。杂质的浓度在金属焊盘的厚度方向上，随着从表面向深度方向离开而变低。

Description

半导体存储装置及其制造方法
[相关申请]
本申请享有以日本专利申请2020-046781号(申请日：2020年3月17日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体存储装置及其制造方法。
背景技术
已知有在三维存储器等半导体存储装置中将分别形成在2片晶圆的金属焊盘彼此接合的技术。在该技术中，如果金属焊盘被过度研磨，那么产生凹陷。
发明内容
本发明要解决的问题在于提供一种能够减少金属焊盘彼此的接合不良的半导体存储装置及其制造方法。
一实施方式的半导体存储装置具备：阵列芯片，具有存储单元阵列；电路芯片，具有与存储单元电连接的电路；及金属焊盘，将阵列芯片与电路芯片接合。金属焊盘含有杂质。杂质的浓度在金属焊盘的厚度方向上，随着从表面向深度方向离开而变低。
附图说明
图1是表示第1实施方式的半导体存储装置的构造的剖视图。
图2是表示图1所示的柱状部的构造的剖视图。
图3是表示阵列晶圆与电路晶圆的构造的剖视图。
图4是表示研磨后的第2金属焊盘的剖视图。
图5是表示实施烷基硫醇(alkanethiol)处理后的第2金属焊盘的剖视图。
图6是表示实施热处理后的第2金属焊盘的剖视图。
图7是将阵列晶圆与电路晶圆的接合部位放大所得的剖视图。
图8是表示导入有硝酸银的第2金属焊盘的剖视图。
图9是表示形成着银层的第2金属焊盘的剖视图。
图10是表示实施热处理后的第2金属焊盘的剖视图。
图11是将阵列晶圆与电路晶圆的接合部位放大所得的剖视图。
图12是表示在硅烷气氛下实施热处理后的第2金属焊盘的剖视图。
图13是表示生成硅化物的第2金属焊盘的剖视图。
图14是将阵列晶圆与电路晶圆的接合部位放大所得的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。
(第1实施方式)
图1是表示第1实施方式的半导体存储装置的构造的剖视图。图1的半导体存储装置是将阵列芯片1与电路芯片2贴合而成的三维存储器。
阵列芯片1具备包含多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘层12(例如氮化硅膜)、绝缘层12上的绝缘层13(例如氧化硅膜)、及存储单元阵列11下的层间绝缘膜14。
另外，阵列芯片1具备多条字线WL、填埋源极线BSL及选择栅极SG作为存储单元阵列11内的电极层。在存储单元阵列11的阶梯构造部21中，各字线WL经由接触插塞22与字配线层23电连接。同样地，填埋源极线BSL经由接触插塞24与源极线25电连接，选择栅极SG经由接触插塞26与选择栅极配线层27电连接。贯通字线WL、填埋源极线BSL及选择栅极SG的柱状部CL经由插塞28与位线BL电连接。
进而，阵列芯片1具备：焊盘41，经由未图示的通孔插塞与配线层37电连接；外部连接电极42，设置在焊盘41上；及外部连接焊盘43，设置在外部连接电极42上。外部连接焊盘43可经由焊球、金属凸块、键合线等连接于安装基板或其它装置。
电路芯片2介隔绝缘层15设置在阵列芯片1下。电路芯片2具备层间绝缘膜16、及层间绝缘膜16下的基板17。基板17例如为硅基板等半导体基板。在以下的说明中，将与基板17的表面平行且相互垂直的方向设为X方向及Y方向，将与基板17的表面垂直的方向设为Z方向。在本说明书中，将+Z方向作为上方向进行处理，将-Z方向作为下方向进行处理，但-Z方向既可与重力方向一致，又可与重力方向不一致。
另外，电路芯片2具备多个晶体管31。各晶体管31具备：栅极电极32，介隔栅极绝缘膜设置在基板17上；及未图示的源极扩散层及漏极扩散层，设置在基板17内。另外，电路芯片2具备：多个插塞33，设置在源极扩散层或漏极扩散层上；配线层34，设置在这些插塞33上；及配线层35，设置在配线层34上。晶体管31、插塞33、配线层34及配线层35构成与存储单元阵列11电连接的电路。
在配线层35上设置着多个金属焊盘36。各金属焊盘36由绝缘层15包围。在金属焊盘36上设置着阵列芯片1的配线层37。
图2是表示阵列芯片1的柱状部CL的构造的剖视图。如图2所示，存储单元阵列11具备交替地积层在层间绝缘膜14上的多条字线WL与多个绝缘层51。各字线WL例如为钨(W)层。各绝缘层51例如为氧化硅膜。
柱状部CL具备作为第1绝缘膜的例子的阻挡绝缘膜52、电荷蓄积层53、作为第2绝缘膜的例子的隧道绝缘膜54、通道半导体层55及核心绝缘膜56。电荷蓄积层53例如为氮化硅膜，介隔阻挡绝缘膜52形成在字线WL及绝缘层51的侧面。通道半导体层55例如为硅层，介隔隧道绝缘膜54形成在电荷蓄积层53的侧面。阻挡绝缘膜52、隧道绝缘膜54及核心绝缘膜56的例子是氧化硅膜或金属绝缘膜。
以下，对本实施方式的半导体存储装置的制造方法进行说明。
首先，如图3所示，形成包含多个阵列芯片1的阵列晶圆W1、及包含多个电路芯片2的电路晶圆W2。在阵列晶圆W1的下表面形成着第1绝缘层71及多个第1金属焊盘72。各第1金属焊盘72形成在配线层37的下表面。另外，在阵列晶圆W1中，在绝缘层13上设置着基板18。
另一方面，在电路晶圆W2的上表面形成着第2绝缘层61及多个第2金属焊盘62。各第2金属焊盘62形成在配线层35的上表面。此处，参照图4～图6对第2金属焊盘62的制造方法详细地进行说明。
首先，在配线层35上形成以铜(Cu)为主成分的第2金属焊盘62a。然后，如果对第2金属焊盘62a进行研磨，那么如图4所示，有时第2金属焊盘62a的上表面产生相对于第2绝缘层61的上表面下凹的凹陷。在该情况下，将阵列晶圆W1与电路晶圆W2接合时，会产生在接合面形成间隙的接合不良。
因此，在本实施方式中，如图5所示，将包含碳(C)键结于硫醇基(SH)所得的烷基硫醇(CxHyS：x、y为自然数)的气体或液体导入到第2金属焊盘62a。由此，碳作为杂质附着在第2金属焊盘62a的表面。
接着，进行将第2金属焊盘62a加热的热处理。结果，如图6所示，碳向第2金属焊盘62a中扩散而第2金属焊盘62a的体积增加。由此，第2金属焊盘62完成。该第2金属焊盘62的上表面成为位于与第2绝缘层61的上表面大致相同高度的位置的平面。另外，第2金属焊盘62如图6所示，具有如下浓度梯度：随着从表面(上表面)沿厚度方向(-Z方向)前进，也就是说，随着从表面向深度方向离开，而碳浓度变低。
另一方面，关于第1金属焊盘72，也可与第2金属焊盘62同样地形成。也就是说，在对以铜为主成分的第1金属焊盘72进行研磨时产生凹陷的情况下，通过进行所述烷基硫醇处理及热处理，而形成含有碳作为杂质的第1金属焊盘72。在该情况下，第1金属焊盘72的下表面成为位于与第1绝缘层71的下表面大致相同高度的位置的平面。另外，第1金属焊盘72也具有如下浓度梯度：随着从表面(下表面)沿厚度方向(Z方向)前进，也就是说，随着从表面向深度方向离开，而碳浓度变低。
像所述那样形成第1金属焊盘72及第2金属焊盘62之后，通过机械压力将阵列晶圆W1与电路晶圆W2贴合。由此，将第1绝缘层71与第2绝缘层61粘接，形成绝缘层15。
接着，对阵列晶圆W1及电路晶圆W2以例如400℃进行退火。由此，将第1金属焊盘72与第2金属焊盘62接合，形成多个金属焊盘36。
图7是将阵列晶圆W1与电路晶圆W2的接合部位放大所得的剖视图。如上所述，在第1金属焊盘72及第2金属焊盘62中，通过将碳作为杂质导入而凹陷得到矫正。因此，在第1金属焊盘72与第2金属焊盘62的接合面，换句话说，在金属焊盘36的中央部不形成间隙。另外，如图7所示，金属焊盘36具有随着从其中央部沿厚度方向(Z方向、-Z方向)离开而碳浓度变低的浓度梯度。
形成金属焊盘36之后，通过CMP(Chemical Mechanical Polishing，化学机械抛光)或湿蚀刻将基板18去除，将阵列晶圆W1及电路晶圆W2切断成多个芯片。像这样制造图1的半导体存储装置。此外，外部连接电极42与外部连接焊盘43例如在去除基板18之后形成在焊盘41上。
根据本实施方式，通过将碳作为杂质导入到金属焊盘并进行热处理，而使金属焊盘的体积增加。因此，即使因金属焊盘的研磨而产生凹陷，也能够使金属焊盘的体积增加。由此，能够减少阵列芯片1与电路芯片2的接合不良。
此外，在本实施方式中，将碳导入到第1金属焊盘72及第2金属焊盘62这两者，但碳的导入只要根据各金属焊盘的下凹程度进行判断即可。因此，也可根据各金属焊盘的下凹程度而将碳导入到第1金属焊盘72或第2金属焊盘62中的一者。
另外，在本实施方式中，形成第1金属焊盘72及第2金属焊盘62时，热处理在将阵列晶圆W1与电路晶圆W2接合之前进行，但也可在这些晶圆的接合时进行。在阵列晶圆W1与电路晶圆W2的接合时，两晶圆以例如400℃的热进行退火，因此，也可将该退火处理利用于所述热处理。在该情况下，也通过作为杂质所导入的碳扩散而体积增加，因此，如图7所示，可无间隙地将第1金属焊盘72与第2金属焊盘62接合。
(第2实施方式)
以下，针对第2实施方式，以与第1实施方式的不同点为中心进行说明。在本实施方式中，第1金属焊盘72及第2金属焊盘62的制造方法与第1实施方式不同。以下，参照图8～图10对本实施方式中的第2金属焊盘62的制造方法进行说明。
如图8所示，在第2金属焊盘62a中产生凹陷的情况下，首先，将包含硝酸银(AgNO3)的液体导入到第2金属焊盘62a。由此，发生下述式(1)所示的取代反应。
Figure BDA0002628807180000051
通过所述取代反应，如图9所示，银析出到第2金属焊盘62a的表面而形成银层63。
接着，进行将第2金属焊盘62a加热的热处理。结果，如图10所示，银向第2金属焊盘62a中扩散而第2金属焊盘62a的体积增加。由此，第2金属焊盘62完成。该第2金属焊盘62的上表面与第1实施方式同样地，成为位于与第2绝缘层61的上表面大致相同高度的位置的平面。另外，第2金属焊盘62如图10所示，具有随着从表面(上表面)沿厚度方向(-Z方向)前进而银浓度变低的浓度梯度。
另一方面，关于第1金属焊盘72，也可与第2金属焊盘62同样地形成。也就是说，在对以铜为主成分的第1金属焊盘72进行研磨时产生凹陷的情况下，通过进行所述取代反应及热处理，而形成含有银作为杂质的第1金属焊盘72。在该情况下，第1金属焊盘72的下表面与第1实施方式同样地，成为位于与第1绝缘层71的下表面大致相同高度的位置的平面。另外，第1金属焊盘72也具有随着从表面(下表面)沿厚度方向(Z方向)前进而银浓度变低的浓度梯度。
然后，与第1实施方式同样地，通过机械压力将阵列晶圆W1与电路晶圆W2贴合而形成绝缘层15。进而，对阵列晶圆W1及电路晶圆W2以例如400℃进行退火，形成多个金属焊盘36。
图10是将阵列晶圆W1与电路晶圆W2的接合部位放大所得的剖视图。如上所述，在第1金属焊盘72及第2金属焊盘62中，通过将银作为杂质导入而凹陷得到矫正。因此，在金属焊盘36的中央部不形成间隙。另外，如图10所示，金属焊盘36具有随着从其中央部沿厚度方向(Z方向、-Z方向)离开而银浓度变低的浓度梯度。
根据本实施方式，通过将银作为杂质导入到金属焊盘并进行热处理，而使金属焊盘的体积增加。因此，即使因金属焊盘的研磨而产生凹陷，也能够使金属焊盘的体积增加。由此，能够减少阵列芯片1与电路芯片2的接合不良。
此外，在本实施方式中，将硝酸银导入到第2金属焊盘62a，但也可将氯化银(AgCl)导入来代替硝酸银。在该情况下，银也析出到第2金属焊盘62a的表面，因此，可通过热处理使第2金属焊盘62a的体积增加。
另外，关于硝酸银或氯化银的导入，也可与第1实施方式同样地，根据研磨后的各金属焊盘的下凹程度而导入到第1金属焊盘72或第2金属焊盘62中的一者。
(第3实施方式)
以下，针对第3实施方式，以与第1实施方式的不同点为中心进行说明。在本实施方式中，第1金属焊盘72及第2金属焊盘62的制造方法与第1实施方式不同。以下，参照图12及图13对本实施方式中的第2金属焊盘62的制造方法进行说明。
如图12所示，在第2金属焊盘62a中产生凹陷的情况下，首先，在硅烷(SiH4)气氛下对第2金属焊盘62a进行热处理。结果，如图13所示，生成第2金属焊盘62a中包含的铜与硅烷中包含的硅键结所得的硅化物而第2金属焊盘62a的体积增加。由此，第2金属焊盘62完成。该第2金属焊盘62的上表面与第1实施方式同样地，成为位于与第2绝缘层61的上表面大致相同高度的位置的平面。另外，第2金属焊盘62如图13所示，具有随着从表面(上表面)沿厚度方向(-Z方向)前进而硅浓度变低的浓度梯度。
另一方面，关于第1金属焊盘72，也可与第2金属焊盘62同样地形成。也就是说，在对以铜为主成分的第1金属焊盘72进行研磨时产生凹陷的情况下，通过在所述硅烷气氛下进行热处理，而形成含有硅作为杂质的第1金属焊盘72。在该情况下，第1金属焊盘72的下表面与第1实施方式同样地，成为位于与第1绝缘层71的下表面大致相同高度的位置的平面。另外，第1金属焊盘72也具有随着从表面(下表面)沿厚度方向(Z方向)前进而银浓度变低的浓度梯度。
然后，与第1实施方式同样地，通过机械压力将阵列晶圆W1与电路晶圆W2贴合而形成绝缘层15。进而，对阵列晶圆W1及电路晶圆W2以例如400℃进行退火，形成多个金属焊盘36。
图14是将阵列晶圆W1与电路晶圆W2的接合部位放大所得的剖视图。如上所述，在第1金属焊盘72及第2金属焊盘62中，通过将硅作为杂质导入而凹陷得到矫正。因此，在金属焊盘36的中央部不形成间隙。另外，如图14所示，金属焊盘36具有随着从其中央部沿厚度方向(Z方向、-Z方向)离开而硅浓度变低的浓度梯度。
根据本实施方式，通过将硅作为杂质导入到金属焊盘，而使金属焊盘的体积增加。因此，即使因金属焊盘的研磨而产生凹陷，也能够使金属焊盘的体积增加。由此，能够减少阵列芯片1与电路芯片2的接合不良。
此外，在本实施方式中，在硅烷气氛下进行热处理，但也可在乙硅烷(Si2H6)气氛下进行热处理。在该情况下，铜与硅键结所得的硅化物也在第2金属焊盘62a内扩散，因此，能够使第2金属焊盘62a的体积增加。
另外，在本实施方式中，硅烷气氛或乙硅烷气氛的热处理也可在阵列晶圆W1与电路晶圆W2的接合时进行。在阵列晶圆W1与电路晶圆W2的接合时，两晶圆以例如400℃的热进行退火，因此，也可将该退火处理利用于金属焊盘的热处理。在该情况下，也通过作为杂质所导入的硅扩散而金属焊盘的体积增加，因此，如图14所示，可无间隙地将第1金属焊盘72与第2金属焊盘62接合。
已对本发明的若干实施方式进行了说明，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些实施方式能以其它多种方式实施，能够在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，且同样包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 阵列芯片
2 电路芯片
11 存储单元阵列
36 金属焊盘
62、62a 第2金属焊盘
72 第1金属焊盘
W1 阵列晶圆
W2 电路晶圆

Claims (10)

1.一种半导体存储装置，具备：
阵列芯片，具有存储单元阵列；
电路芯片，具有与所述存储单元阵列电连接的电路；及
金属焊盘，将所述阵列芯片与所述电路芯片接合；且
所述金属焊盘含有杂质，所述杂质的浓度在所述金属焊盘的厚度方向上，随着从表面向深度方向离开而变低。
2.根据权利要求1所述的半导体存储装置，其中所述金属焊盘含有铜(Cu)，且
所述杂质为碳(C)、银(Ag)或硅(Si)。
3.根据权利要求1所述的半导体存储装置，其中所述金属焊盘具有设置在所述阵列芯片的第1金属焊盘、及设置在所述电路芯片的第2金属焊盘，且所述金属焊盘内的所述杂质的浓度在所述第1金属焊盘与所述第2金属焊盘的接合面处最高。
4.一种半导体存储装置的制造方法，在具有存储单元阵列的阵列晶圆的表面形成第1金属焊盘，
在具有与所述存储单元阵列电连接的电路的电路晶圆的表面形成第2金属焊盘，
将杂质导入到所述第1金属焊盘及所述第2金属焊盘的至少一者，
对导入有所述杂质的金属焊盘进行热处理，
将所述阵列晶圆与所述电路晶圆贴合而将所述第1金属焊盘与所述第2金属焊盘接合。
5.根据权利要求4所述的半导体存储装置的制造方法，其中利用铜形成所述第1金属焊盘及所述第2金属焊盘，
将烷基硫醇(CxHyS：x、y为自然数)导入到所述第1金属焊盘及所述第2金属焊盘的至少一者，
对导入有所述烷基硫醇的金属焊盘进行热处理。
6.根据权利要求5所述的半导体存储装置的制造方法，其中当将所述第1金属焊盘与所述第2金属焊盘接合时进行所述热处理。
7.根据权利要求4所述的半导体存储装置的制造方法，其中利用铜形成所述第1金属焊盘及所述第2金属焊盘，
将硝酸银(AgNO3)或氯化银(AgCl)导入到所述第1金属焊盘及所述第2金属焊盘的至少一者，
对导入有所述硝酸银或氯化银的金属焊盘进行热处理。
8.根据权利要求7所述的半导体存储装置的制造方法，其中当将所述第1金属焊盘与所述第2金属焊盘接合时进行所述热处理。
9.根据权利要求4所述的半导体存储装置的制造方法，其中利用铜形成所述第1金属焊盘及所述第2金属焊盘，
在硅烷(SiH4)气氛或乙硅烷(Si2H6)气氛下对所述第1金属焊盘及所述第2金属焊盘的至少一者进行热处理。
10.根据权利要求9所述的半导体存储装置的制造方法，其中当将所述第1金属焊盘与所述第2金属焊盘接合时进行所述热处理。
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