CN113396477A - 电子设备 - Google Patents
电子设备 Download PDFInfo
- Publication number
- CN113396477A CN113396477A CN202080009671.8A CN202080009671A CN113396477A CN 113396477 A CN113396477 A CN 113396477A CN 202080009671 A CN202080009671 A CN 202080009671A CN 113396477 A CN113396477 A CN 113396477A
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- Prior art keywords
- chip
- semiconductor substrate
- light emitting
- electronic device
- bump
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- 239000004065 semiconductor Substances 0.000 claims abstract description 193
- 229910052751 metal Inorganic materials 0.000 claims abstract description 168
- 239000002184 metal Substances 0.000 claims abstract description 168
- 239000000758 substrate Substances 0.000 claims abstract description 162
- 239000002245 particle Substances 0.000 claims description 22
- 239000002923 metal particle Substances 0.000 claims description 11
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000010408 film Substances 0.000 description 102
- 238000000034 method Methods 0.000 description 46
- 239000010931 gold Substances 0.000 description 36
- 230000008569 process Effects 0.000 description 28
- 239000000463 material Substances 0.000 description 26
- 238000010586 diagram Methods 0.000 description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 239000010949 copper Substances 0.000 description 15
- 238000012545 processing Methods 0.000 description 14
- 238000003384 imaging method Methods 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 11
- 229910052737 gold Inorganic materials 0.000 description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 238000005259 measurement Methods 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000002844 melting Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000005476 size effect Effects 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02355—Fixing laser chips on mounts
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
- G01S17/06—Systems determining position data of a target
- G01S17/08—Systems determining position data of a target for measuring distance only
- G01S17/10—Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
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- G—PHYSICS
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- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/88—Lidar systems specially adapted for specific applications
- G01S17/89—Lidar systems specially adapted for specific applications for mapping or imaging
- G01S17/894—3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
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- G—PHYSICS
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- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/481—Constructional features, e.g. arrangements of optical elements
- G01S7/4816—Constructional features, e.g. arrangements of optical elements of receivers alone
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- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
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- G01S7/483—Details of pulse systems
- G01S7/484—Transmitters
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- H01S5/02476—Heat spreaders, i.e. improving heat flow between laser chip and heat dissipating elements
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- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
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- H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
- H01S5/42—Arrays of surface emitting lasers
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- G01B11/00—Measuring arrangements characterised by the use of optical techniques
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- G01B11/25—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures by projecting a pattern, e.g. one or more lines, moiré fringes on the object
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- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
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- G01S17/06—Systems determining position data of a target
- G01S17/08—Systems determining position data of a target for measuring distance only
- G01S17/32—Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
- G01S17/36—Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
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- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/481—Constructional features, e.g. arrangements of optical elements
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- G01S7/4815—Constructional features, e.g. arrangements of optical elements of transmitters alone using multiple transmitters
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Abstract
根据本公开的电子设备包括半导体基板、芯片和连接部。所述芯片具有与所述半导体基板的热膨胀率不同的热膨胀率。所述连接部包括用于连接配置在所述半导体基板和所述芯片的相对的主表面上的连接焊盘的多孔金属层。
Description
相关申请的交互参照
本申请要求于2019年2月4日在日本提交的日本专利申请第2019-018088号以及于2019年9月25日在日本提交的日本专利申请第2019-174039号的优先权。
技术领域
本公开涉及一种电子设备。
背景技术
作为用于将电子元件的芯片安装在半导体基板上的技术,例如,已知一种倒装芯片安装,其中将以突起的方式配置在半导体基板的上表面的金属凸块与配置在芯片的下表面的连接焊盘彼此压力接触,同时加热,从而将金属凸块和芯片连接(例如,参见日本特开第2011-077308号公报)。通常使用块状的金、铜、焊料等作为凸块的材料。
[引用文献列表]
[专利文献]
[专利文献1]:JP 2011-077308 A
发明内容
[技术问题]
然而,如果使用块状的金或铜作为凸块的材料,并且热膨胀率与半导体基板不同的的芯片通过倒装芯片安装而安装在半导体基板上,则需要在高温高压下连接凸块,从而损坏芯片并且降低电子设备的可靠性。
此外,如果使用焊料作为凸块的材料,可以在相对较低的温度和低压下连接半导体基板和芯片,但是连接强度低于由金或铜制成的凸块;因此,如果半导体基板和芯片具有不同的热膨胀率,则可靠性会由于连接强度而降低。
[问题的解决方案]
本发明的各个方面和特征限定在所附权利要求书中。根据本公开的电子设备包括半导体基板、芯片和连接部。所述芯片具有与所述半导体基板的热膨胀率不同的热膨胀率。所述连接部包括用于连接配置在所述半导体基板和所述芯片的相对的主表面上的连接焊盘的多孔金属层。
附图说明
当结合附图考虑时,通过阅读以下详细说明将更好地理解本发明的上述和其他目的、特征、优势以及技术和产业意义。
图1是用于说明根据本公开的电子设备的断面的图。
图2A是用于说明根据本公开的在半导体基板上形成凸块的过程的图。
图2B是用于说明根据本公开的在半导体基板上形成凸块的过程的图。
图2C是用于说明根据本公开的在半导体基板上形成凸块的过程的图。
图2D是用于说明根据本公开的在半导体基板上形成凸块的过程的图。
图3A是用于说明根据本公开的在芯片上形成凸块的过程的图。
图3B是用于说明根据本公开的在芯片上形成凸块的过程的图。
图3C是用于说明根据本公开的在芯片上形成凸块的过程的图。
图3D是用于说明根据本公开的在芯片上形成凸块的过程的图。
图4是示出根据本公开的测距装置的构成的示例的框图。
图5是用于说明根据本公开的测距装置的构成要素的配置例的图。
图6是示出根据本公开的驱动电路的等效模型的电路图。
图7是用于说明在根据本公开的发光元件中流动的电流的上升时间和下降时间的图。
图8是用于说明根据本公开的光源装置的断面结构的图。
图9A是用于说明根据本公开的光源装置的组装过程的图。
图9B是用于说明根据本公开的光源装置的组装过程的图。
图9C是用于说明根据本公开的光源装置的组装过程的图。
具体实施方式
下面将基于附图详细说明本公开的实施方案。在下面的各实施方案中,由相同的附图标记以及相同的剖面线表示相同的部件,并且省略重复的说明。
1.电子设备的断面构成
如图1所示,根据本公开的电子设备1包括半导体基板2、芯片3和用于连接配置在半导体基板2和芯片3的相对的主表面上的连接焊盘21和31的连接部(例如,在下文中,记载为凸块4)。下面将给出关于半导体基板2、芯片3和连接焊盘21和31的示例性细节。然而,其他实施方案可以包括其他示例性细节。
例如,芯片3可以是半导体激光器,并且例如可以在由诸如砷化镓(GaAs)等半导体材料或半导体化合物材料制成的基材的内部包括连接焊盘31、半导体激光器的发光部32等。发光部32可以包括多个发光元件321,各个发光元件发出激光。例如,多个发光元件321可以二维地配置。在芯片3的基材中形成的电子元件可以是半导体激光器的发光部32以外的任意电子元件。此外,芯片3的基材可以是例如由磷化铟(InP)等制成的半绝缘性基材。
例如,半导体基板2可以是硅(Si)基板,并且驱动半导体激光器的驱动电路22可以形成在半导体基板2的内部。形成在半导体基板2内部的电子电路可以是半导体激光器的驱动电路22以外的任意的电子电路。
电子设备1可以被构造为使得芯片3通过倒装芯片安装而安装在半导体基板2上,并且凸块4将半导体基板2内部的驱动电路22和作为半导体激光器的芯片3电气连接。
在一般的倒装芯片安装中,芯片通过将配置在半导体基板或芯片的相对的主表面上的诸如金(Au)、铜(Cu)或焊料等块状金属凸块与半导体基板或芯片压力接触并同时进行加热来安装在半导体基板上。
然而,例如,当半导体基板和芯片的热膨胀率之间的差为0.1ppm/℃以上时并且如果使用块状的Au、Cu、焊料等作为凸块的材料,可能会出现以下问题。
例如,如果使用块状的Au作为凸块的材料,为了使用凸块稳定地连接具有不同的热膨胀率的半导体基板和芯片,则需要加热到300℃以上的高温,并且在半导体基板和芯片之间施加100MPa以上的高压。
此外,如果使用块状的Cu作为凸块的材料,则需要加热到380℃以上的温度。以这种方式,当使用块状的Au或Cu作为凸块的材料时,则需要在高温高压下连接凸块,并且高温高压可能会损坏芯片,从而可能会降低电子设备的可靠性。
另一方面,如果使用焊料作为凸块的材料,则与使用Au和Cu相比,可以在更低的温度和更低的压力下连接凸块;然而,焊料具有比Au和Cu更低的耐热性和连接强度。因此,对于由焊料制成的凸块,例如,如果芯片由于安装在芯片上的诸如半导体激光器等电子元件产生的热量而膨胀,则由于半导体基板和芯片的热膨胀率之间的差异会发生开路故障,从而可能会降低电子设备的可靠性。
如上所述,根据本公开的半导体基板2可以是热膨胀率为5.7ppm/℃的Si基板。另一方面,根据本公开的芯片3的基材可以是热膨胀率为2.6ppm/℃的GaAs。
因此,在电子设备1中,半导体基板2和芯片3的热膨胀率之间的差可能远大于0.1ppm/℃。因此,如果电子设备1中的凸块的材料是块状的Au、Cu或焊料,则可能会发生上述问题并且可能会降低可靠性。
为了解决这个问题,例如,电子设备1的凸块4可以包含由例如Au制成的多孔金属层41。多孔金属层41可以包含粒径为0.005微米(μm)~1.003μm的Au粒子。另一方面,例如,多孔金属层41的成分可以是Cu、银(Ag)或铂(Pt)。
多孔金属层41可以包含粒径为0.005μm~1.0μm的金属粒子。由于粒径的尺寸效应,这可以允许在比块状金属的熔点更低的温度下接合金属。例如,多孔金属层41能够在由Au组成时在约100℃下、在由Ag组成时在约250℃下以及在由Cu组成时在约150℃下连接半导体基板2和芯片3。因此,电子设备1能够减少芯片3由于受热而导致的损坏,并且提高可靠性。
例如,多孔金属层41和凸块4之间的高度比,例如多孔金属层41的厚度或纵向延伸与凸块4的厚度或纵向延伸之间的比,可以等于或大于90%,或者等于或大于95%。纵向延伸是沿着垂直方向的延伸,该垂直方向可以是半导体基板2和芯片3的层叠方向,例如垂直于半导体基板2或芯片3的主表面的方向。除了多孔金属层41之外,凸块4还可以包括作为无孔的或孔隙率(例如,孔隙的体积分数)比多孔金属层41更小的一个或多个金属层。下面参照例如金属膜42、43进一步说明金属层的示例。此外,多孔金属层41可以具有弹性,并且例如,即使在芯片3由于半导体激光器产生的热量而以与半导体基板2的热膨胀率不同的热膨胀率膨胀时也可以弹性变形,使得上述的多孔金属层41和凸块4之间的高度比可以防止开路故障的发生。因此,与例如使用由焊料制成的凸块的情况相比,具有上述的多孔金属层41和凸块4之间的高度比的电子设备1能够提高可靠性。
如上所述的电子设备1可以通过以下步骤来制造:在上表面配置有凸块4的半导体基板2上层叠芯片3;在不熔化多孔金属层41的情况下将凸块4的多孔金属层41连接到连接焊盘31;以及通过例如倒装芯片安装将芯片3安装在半导体基板2上。
此外,电子设备1可以通过以下步骤来制造:在半导体基板2上层叠下表面配置有包括多孔金属层41的凸块的芯片3;在不熔化多孔金属层41的情况下将凸块4的多孔金属层41连接到连接焊盘21;以及通过例如倒装芯片安装将芯片3安装在半导体基板2上。另一方面,凸块可以在层叠之前配置在半导体基板2和芯片3中的每一个上。
如果凸块4配置在半导体基板2侧,则金属膜42可以配置在多孔金属层41和半导体基板2侧的连接焊盘21之间。此外,如果凸块配置在芯片3侧,则金属膜可以配置在多孔金属层41和芯片3侧的连接焊盘31之间。
在本公开中,通过将金属膜42的膜厚度与凸块4的厚度在垂直于半导体基板2的主表面的方向上的比率设定为10%以下,可以实现微细间距使得凸块4之间的间距被设定为20μm以下。下面将结合形成凸块4的过程来说明微细间距。
2.凸块的形成过程
下面将参照图2A~图3D说明根据本公开的形成凸块的过程。图2A~图2D是用于说明根据本公开的示例在半导体基板2上形成凸块4的过程的图。图3A~图3D是用于说明根据本公开的在芯片3上形成凸块4a(参照图3D)的过程的图。
如图2A所示,当凸块4将要形成在半导体基板2上时,首先,可以将光刻胶层51形成在半导体基板2的配置有连接焊盘21的表面上。之后,可以使用光刻技术在光刻胶层51上将要形成凸块4的位置处形成通孔,从而露出连接焊盘21的表面。
此时,通孔可以形成为使得相邻通孔的中心之间的间隔被设定为例如20μm(20μm间距)。在后续过程中,通孔可以用包含作为多孔金属层41的材料的金属粒子的糊剂40填充;然而,由于使用示例性的20μm间距的微细结构,所以如果用这种状态下的糊剂40填充通孔,则微细结构可能被损坏和塌陷。
因此,如图2B所示,可以通过例如溅射在光刻胶层51和连接焊盘21的上表面上形成金属膜42。作为金属膜42的材料,可以选择具有与包含在将要注入到通孔中的糊剂40中的金属粒子相同成分的金属。在该示例中,形成由Au制成的金属膜42。
由此,光刻胶层51的表面可以被金属膜42涂覆并且***,从而当通孔用包含金属粒子的糊剂40填充时,可以防止微细结构塌陷。
此外,如果此时形成的金属膜42的膜厚度太厚,则通孔的开口可能变窄并且变得难以用包含金属粒子的糊剂40填充该通孔。因此,在该示例中,形成薄的金属膜42,使得金属膜42的膜厚度与通孔的深度D(换句话说,将要形成的凸块4在垂直于半导体基板2的主表面的方向上的厚度(凸块4的深度D))的比率被设定为10%以下。
例如,当以20μm的间距形成高度为10μm的凸块4时,金属膜42的膜厚度被设定为0.2μm。利用这种构成,即使当形成有金属膜42时,也可以防止通孔的开口变窄,从而可以在后续过程中用包含金属粒子的糊剂40充分填充通孔。
随后,如图2C所示,例如,形成在光刻胶层51上的通孔可以用糊剂40填充。糊剂40可以具有99.9重量%以上的纯度,并且可以包含粒径为0.005μm~1.0μm的粒子,例如Au粒子。例如,作为用糊剂40填充通孔的方法,可以使用诸如丝网印刷或用刮刀涂抹滴下的糊剂40的方法等任意方法。
然后,可以干燥和烧结糊剂40,之后,可以使用剥离液等剥离光刻胶层51。因此,如图2D所示,在连接焊盘21的表面上形成具有例如两层结构的凸块4,其中顺次沉积由Au制成的金属膜42和包含粒径为0.005μm~1.0μm的Au粒子的多孔金属层41。
如以上示例所述,凸块4可以包括金属膜42,使得凸块4的膜厚度与高度的比率被设定为10%以下。如上所述的金属膜42形成在光刻胶层51和连接焊盘21的表面上,以防止在光刻胶层51上图案化的凸块4的微细结构塌陷。利用这种构成,可以实现凸块4的微细间距,使得间距被设定为20μm以下。
此外,金属膜42可以通过溅射形成在连接焊盘21的表面上,并且因此,即使连接焊盘21由成分与金属膜42的成分不同的金属制成,金属膜42也可以与连接焊盘21牢固地接合。
金属膜42可以由成分与沉积在表面上的多孔金属层41的成分不同的金属制成,但是当金属膜42由与多孔金属层41的成分相同的成分例如Au制成时,多孔金属层41可以利用比当多孔金属层41沉积在与多孔金属层41的成分不同的金属膜上时更强的接合力与金属膜42接合。应当注意,当凸块4由Au以外的成分(例如,Cu、Ag(银)、Pt(铂))制成时,金属膜42也可以由Au以外的成分(例如,Cu、Ag(银)或Pt(铂))制成。
下面将说明芯片3上的如图3D所示的凸块4a的形成过程。如图3A所示,当凸块4a将要形成在芯片3上时,首先,可以将光刻胶层52形成在芯片3的形成有连接焊盘31的表面上。之后,例如,可以使用光刻技术在光刻胶层52上将要形成凸块4a的位置处形成通孔,从而露出连接焊盘31的表面。
之后,如图3B所示,可以通过例如溅射在光刻胶层52和连接焊盘31的上表面上形成金属膜43。作为金属膜43的材料,选择具有与包含在将要注入到通孔中的糊剂40中的粒子相同成分的材料,例如Au。
因此,光刻胶层52的表面可以被金属膜43涂覆并且***,从而当通孔用包含例如Au粒子等粒子的糊剂40填充时,可以防止微细结构塌陷。
此外,即使在这种情况下,也可以形成薄的金属膜43,使得金属膜43的膜厚度与通孔的深度D(换句话说,将要形成的凸块4a在垂直于芯片3的主表面的方向上的厚度(凸块4a的深度D))的比率被设定为10%以下。
例如,与半导体基板2侧的凸块4相似,当以20μm的间距形成高度为10μm的凸块时,金属膜43的膜厚被设定为0.2μm。利用这种构成,即使当形成有金属膜43时,也可以防止通孔的开口变窄,从而可以在后续过程中用包含Au粒子的糊剂40充分填充通孔。
随后,如图3C所示,形成在光刻胶层52上的通孔可以用糊剂40填充。例如,糊剂可以具有99.9重量%以上的纯度,并且可以包含粒径为0.005μm~1.0μm的粒子,例如Au粒子。
然后,可以干燥和烧结糊剂40,之后,可以使用剥离液等剥离光刻胶层52。因此,如图3D所示,在连接焊盘31的表面上形成具有例如两层结构的凸块4a,其中顺次沉积由Au制成的金属膜43和包含粒径为0.005μm~1.0μm的Au粒子的多孔金属层41。
如上所述,凸块4a可以包括金属膜43,使得凸块4a的膜厚度与高度的比率被设定为10%以下。利用这种构成,与半导体基板2侧的凸块4相似,可以实现凸块4a的微细间距,使得间距被设定为20μm以下。
此外,与半导体基板2侧的凸块4相似,凸块4a能够将金属膜43与连接焊盘31牢固地接合,从而可以将金属膜43与多孔金属层41牢固地接合。
在如上所述的实施方案中,说明了以下情况,其中其上未配置凸块4a的芯片3安装在其上配置有凸块4的半导体基板2上以及其上配置有凸块4a的芯片3安装在其上配置有凸块4的半导体基板2上,但是这些情况仅通过示例的方式进行说明。
根据本公开的电子设备可以被构造为使得其上配置有凸块4a的芯片3安装在其上配置有凸块4的半导体基板2上。在这种构成中,金属膜42和43可以形成为使得膜厚度与用作用于连接半导体基板2和芯片3的连接部的凸块4和凸块4a的层叠体在垂直于半导体基板2和芯片3的主表面的方向上的厚度的一半的比率被设定为10%以下,优选小于5%。
此外,在如上所述的实施方案中,已经说明了芯片3的基材是Si以外的基材的情况,但是芯片3的基材可以是掺杂有杂质的Si,只要基材的热膨胀率与半导体基板2的热膨胀率不同即可。
例如,上述的包括半导体激光器的发光部32的芯片3和包括半导体激光器的驱动电路22的半导体基板2可以安装在诸如ToF传感器和结构化光等测距装置上。例如,安装在测距装置上的半导体激光器的发光部32用作ToF传感器或结构化光的光源。
接下来,参照图4,将说明其上安装有根据实施方案的电子设备1的测距装置。图4是示出根据实施方案的测距装置100的构成示例的框图。如图4所示,测距装置100可以包括光源装置110、成像装置120和控制部130。
光源装置110可以包括其上安装有发光部32的芯片3、其上安装有驱动电路22的半导体基板2、电源电路111和发光侧光学***112。成像装置120可以包括成像侧光学***121、图像传感器122和图像处理部123。
控制部130可以包括测距部131。控制部130可以被包括在光源装置110或成像装置120中,或者可以与光源装置110或成像装置120分开构造。
发光部32可以包括例如二维排列的发光元件321,各个发光元件发出激光(参照图1)。例如,每个发光元件321可以具有垂直腔面发射激光器(VCSEL)结构。
驱动电路22可以包括利用其驱动发光部32的电气电路。例如,电源电路111从由安装在测距装置100上的电池(未示出)等供给的输入电压产生驱动电路22的电源电压。驱动电路22利用电源电压驱动发光部32。
从发光部32发出的光经由发光侧光学***112照射用作测距对象的被摄体S。来自如上所述被光照射的被摄体S的反射光经由成像侧光学***121入射到图像传感器122的成像面。
例如,图像传感器122可以包括诸如电荷耦合器件(CCD)传感器和互补金属氧化物半导体(CMOS)传感器等成像元件,并且如上所述,经由如上所述的成像侧光学***121接收来自其上入射有光的被摄体S的反射光,并且将接收到的光转换为将要输出的电气信号。
图像传感器122例如对于通过对接收的光进行光电转换而产生的电气信号执行诸如相关双采样(CDS)处理和自动增益控制(AGC)处理等各种处理,并且还对其进行模/数(A/D)转换。
然后,图像传感器122向后述的图像处理部123输出用作数字数据的图像信号。图像传感器122还可以向驱动电路22输出帧同步信号。因此,驱动电路22可以使发光部32中的发光元件321以与图像传感器122的帧周期相对应的时机发光。
图像处理部123可以由诸如数字信号处理器(DSP)等各种图像处理处理器构成。例如,图像处理部123对从图像传感器122输入的数字信号(图像信号)执行各种类型的图像信号处理。
控制部130可以由诸如包括中央处理单元(CPU)、只读存储器(ROM)和随机存取存储器(RAM)的微型计算机以及诸如DSP等信息处理装置等各种类型的信息处理装置构成。控制部130执行控制发光部32的发光操作的驱动电路22的控制和根据图像传感器122的成像操作的控制。
控制部130可以具有用作测距部131的功能。测距部131基于经由图像处理部123输入的图像信号(具体地,通过接收来自被摄体S的反射光而提供的图像信号)来测量距被摄体S的距离。
测距部131测量被摄体S,从而能够通过测量距被摄体S的各个部分的距离来确定其三维形状。在某些情况下,控制部130具有其中对电源电路111进行控制的构成。
下面说明利用测距装置100进行距离测量的具体方法。采用测距装置100的距离测量的示例可以包括结构化光(STL)方式和飞行时间(ToF)方式。
STL方式是基于通过对用具有诸如点状图案、格子图案等某种明/暗图案的光照射被摄体S进行成像而获得的图像来测量距离的方式。
对于STL方式,具有点状图案的光入射在被摄体S上。该图案光被划分成多个块,并且各块具有分配给其的不同的点状图案,使得点状图案不会在块之间重叠。通过采用的STL方式,发光部32用作STL的光源。
ToF方式是通过检测发光部32已经发出的光直到被目标反射后到达图像传感器122的飞行时间(时间滞后)来测量距目标的距离的方式。
当ToF方式使用所谓的直接ToF方式时,图像传感器122使用单光子雪崩二极管(S焊盘),并且对发光部32执行脉冲驱动。
在这种情况下,测距部131基于经由图像处理部123输入的图像信号来计算光从发光部32发出后直到光被图像传感器122接收的时间滞后,并且基于时间滞后和光速来计算距被摄体S的各个部分的距离。
应当注意,例如,当ToF方式使用所谓的间接ToF方式(相位差法)时,图像传感器122使用红外线(IR)图像传感器。当采用ToF方式时,发光部32用作ToF传感器的光源。
接下来,参照图5,将说明根据实施方案的测距装置100中的构成要素的配置例。图5是用于说明根据实施方案的测距装置100中的构成要素的配置例的图。
如图5所示,测距装置100具有安装在安装基板101的同一平面上的光源装置110和成像装置120。应当注意,在图5中,省略了控制部130的图示。成像装置120包括其上配置有多个成像元件124的图像传感器122和图像处理部123,其中图像传感器122层叠在图像处理部123上。
光源装置110包括具有发光部32的芯片3和具有驱动电路22的半导体基板2,其中芯片3通过倒装芯片安装而安装在半导体基板2上。因此,半导体基板2和芯片3构成层状结构。
与半导体基板2和芯片3并排安装在同一平面上的情况相比,这种构成可以减少光源装置110在安装基板101中所占据的面积,从而允许光源装置110的小型化。
应当注意,光源装置110可以具有以下构成,其中包括发光部32的芯片3通过倒装芯片安装而安装在设有温度传感器的半导体基板上,并且包括驱动电路22的半导体基板2安装在与安装基板101上的半导体基板2相同的平面上。
在具有上述这种构成的情况下,温度传感器检测发光部32附近的温度。驱动电路22根据利用温度传感器检测到的发光部32附近的温度向发光部32提供驱动控制。利用这种构成,驱动电路22可以防止发光部32的发光特性因温度变化而变化。
半导体基板2和芯片3可以通过包括例如上述的由Au制成的多孔金属层41的凸块4彼此连接。利用这种构成,半导体基板2和芯片3可以在相对较低的温度和低压的条件下连接,从而减少受热损伤。
在半导体基板2由硅制成并且由GaAs制成的基材用于芯片3的情况下,即使芯片3被加热并且以与半导体基板2不同的热膨胀系数膨胀,多孔金属层41也会发生弹性变形,从而防止凸块4中发生开路故障。
在光源装置110上,芯片3通过倒装芯片安装利用具有包括例如由Au制成的多孔金属层41的凸块4而安装在半导体基板2上。与半导体基板2和芯片3并排安装在同一平面上的情况相比,该构成允许更快的发光。因此,测距部131能够提高测距精度。接下来,将参照图6和图7,说明更快的发光和测距精度的提高。
图6是示出根据实施方案的驱动电路22的等效模型的电路图。图7是用于说明在根据实施方案的发光元件321中流动的电流的上升时间和下降时间的图。如图6所示,驱动电路22使大电流的发光电流I1在用作有源电阻R的发光元件321中流动,从而使其中电流流动的发光元件321发光。
此时,分流电流I2在连接驱动电路22和发光部32的凸块4的寄生电容C中流动,并且在驱动电流I3在寄生电感L中流动的同时,反电动电流I4在寄生电感L中流动。
因此,如图7中虚线所示,虽然在发光元件321中流动的电流瞬时上升和瞬时下降是理想的,但是实际上,如粗实线所示,在反电动电流I4的影响下发光电流I1在用大电流驱动时变钝。
因此,在发光元件321中流动的发光电流I1的上升时间(Tr)和下降时间(Tf)增加。该上升时间Tr和下降时间Tf随着连接驱动电路22和发光部32的连接线变长而变长。
因此,在半导体基板2和芯片3并排安装在同一平面上的光源装置中,半导体基板2内部的驱动电路22和芯片3内部的发光部32通过长的接合线连接,因此上升时间Tr和下降时间Tf很长。
相比之下,在根据实施方案的光源装置110中,驱动电路22和发光部32通过比接合线更短的凸块4连接,从而可以防止上升时间Tr和下降时间Tf增加。因此,与半导体基板2和芯片3并排安装在同一平面上的光源装置相比,光源装置110可以提供更快的发光。
此外,在半导体基板2和芯片3并排安装在同一平面上的光源装置中,测距部131具有更长的上升时间Tr,从而在某些情况下降低了测距精度。例如,当测距装置100是ToF传感器时,测距部131基于从发光元件321发出的光的亮度达到峰值的时机到由图像传感器122接收到的光的亮度达到峰值的时机的时间来测量距被摄体S的距离。
此时,如上所述,半导体基板2和芯片3并排安装在同一平面上的光源装置具有较长的上升时间Tr。据此,从发光元件321发出的光的亮度缓慢增加,使得由图像传感器122接收到的光的亮度缓慢增加。
结果,测距部131在图像传感器122接收到的光的亮度达到本来的峰值之前错误地判定光的亮度已经达到峰值,并且测量出小于实际距离的距被摄体S的距离,这导致了测距精度的下降。
相比之下,根据实施方案的光源装置110允许更快的发光,并且因此从发光元件321发出的光的亮度能够急剧增加。因此,由图像传感器122接收到的光的亮度急剧增加。
因此,测距部131更准确地判定由图像传感器122接收到的光的亮度达到本来的峰值的时机,从而能够正确地测量距被摄体S的距离,这样导致测距精度的提高。
接下来,将参照图8说明光源装置110的断面结构的示例。图8是用于说明根据实施方案的光源装置110的断面结构的图。如图8所示,光源装置110具有其中芯片3通过倒装芯片安装而安装在形成有驱动电路22(参照图1)的例如由Si制成的半导体基板2上的构成。
例如,芯片3可以包括GaAs基板141,其表面(图8中的下表面)具有形成在其上的多个发光元件321。发光元件321分别在GaAs基板141侧用作阴极,并且分别在半导体基板2侧用作阳极,其中各阴极相互连接。应当注意,发光元件321可以分别用作GaAs基板141侧的阳极,并且也可以分别用作半导体基板2侧的阴极,其中在这种情况下各阳极相互连接。
发光元件321分别具有在同一平面上并排设置的用作阳极的电极142和用作阴极的电极143。当电流从用作阳极的电极142流向用作阴极的电极143时,发光元件321发光。如图8中空心箭头所示,发光元件321在从示例性的GaAs基板141的顶表面(下表面)到底表面(上表面)的方向上发出激光。
半导体基板2在面向芯片3的一侧的表面上设置有多个连接焊盘150。每个连接焊盘150可以配置在与用作层叠的芯片的阳极的电极142和用作阴极的电极143相对的对应位置上。
连接焊盘150、用作阳极的电极142和用作阴极的电极143通过可以包括Au的多孔金属层41的凸块4彼此连接。与用作阴极的电极143连接的连接焊盘150可以经由配线151接地(未示出)。
与用作阳极的各电极142连接的各连接焊盘150可以经由***在开关154的一端和连接焊盘150之间的相应配线152和相应焊盘153连接到相应的开关154的一端。开关154的另一端可以连接到供给发光电流I1的电流源。应当注意,在电极142用作阴极并且电极143用作阳极的情况下,开关154与用作阴极的相应电极连接。
多个开关154可以分别由驱动电路22单独控制。因此,驱动电路22能够以独立的方式单独地控制各发光元件321。结果,当测距装置100通过STL方式执行距离测量时,光源装置110可以用具有各种类型的点状图案的图案光照射被摄体S。应当注意,各开关154可以由发光元件321共享,并且针对每组的一些发光元件321进行控制。
接下来,将参照图9A~图9C说明组装光源装置110的过程。图9A~图9C是用于说明组装根据实施方案的光源装置110的过程的图。下面说明连接芯片3和半导体基板2的过程。
在图9A~图9C的构成要素中,与图8所示的构成要素相同的构成具有与图8所示的标号相同的标号,从而将省略重复的说明。应当注意,虽然这里说明的是发光元件321的用作阳极的电极142侧设置有凸块4a(参照图3D)的情况,但是半导体基板2的连接焊盘150侧也可以设置有凸块4(参照图2D)。
如图9A所示,当凸块4a安装在发光元件321的用作阳极的电极142侧(即,芯片3侧)上时,例如,由Au制成的金属膜43可以配置在含有Au的多孔金属层41和用作阳极的电极142之间。
金属膜43可以形成为使得金属膜43的膜厚度与凸块4a的高度的比率被设定为小于10%,优选小于5%。例如,当形成高度(厚度)为10μm的多孔金属层41时,形成具有0.2μm的厚度的金属膜43。
此外,当半导体基板2的连接焊盘150侧设置有凸块4(参照图2D)时,金属膜42可以形成为使得金属膜42的膜厚度与凸块4的高度的比率被设定为小于10%,优选小于5%。例如,当形成高度(厚度)为10μm的多孔金属层41时,形成具有0.2μm的厚度的金属膜42。
上述的金属膜43可以形成为对于其中芯片3被图案化以形成凸块4a的光刻胶层52(参照图3B)的微细结构提供更大的刚性。利用这种构成,可以实现厚度为大约10μm的凸块4a的微细间距,使得间距被设定为20μm以下。
虽然部分的说明假设半导体基板2侧的连接焊盘150的成分是类似于多孔金属层41的Au,但是当连接焊盘150的成分是Au以外时,连接焊盘150的表面设置有由Au制成的膜,而该膜具有与多孔金属层41的成分相同的成分。利用这种构成,可以提高连接焊盘150和多孔金属层41之间的连接强度。
当将要连接芯片3和半导体基板2时,如图9A所示,首先,可以将芯片3安装在半导体基板2上,以使安装在半导体基板2的上表面上的连接焊盘150与安装在芯片3侧的用作阳极的电极142上的凸块4a对准。
随后,如图9B所示,可以降低芯片3,以使凸块4a的下表面抵接在连接焊盘150的上表面上,从而对其施加一定压力。之后,芯片3可以被加热到大约100℃的相对较低的温度,并且在不会熔化凸块4a中的由Au制成的多孔金属层41的情况下,连接焊盘150和用作阳极的电极142通过凸块4a连接。
此时,多孔金属层41可以根据升高的温度和施加在其上的压力而在厚度方向上被略微挤压,并且减小其高度(厚度)。结果,在芯片3和半导体基板2通过凸块4a连接之后的状态下,金属膜43使得金属膜43的膜厚度与凸块4a的高度的比率被设定为小于20%。
类似地,当将凸块4(参照图2D)安装在半导体基板2的连接焊盘150侧上时,在芯片3和半导体基板2通过凸块4连接之后的状态下,金属膜42可以使得金属膜42的膜厚度与凸块4的高度的比率小于20%。
安装在芯片3上的发光元件321的侧表面以及安装在发光元件321的阳极上的用作阳极的电极142的侧表面和下表面的周缘部可以被绝缘膜144覆盖。例如,绝缘膜144可以包含二氧化硅(SiO2)和氮化硅(SiN)中的至少一种。
安装在半导体基板2的上表面上的连接焊盘150的侧表面和上表面的周缘部可以被绝缘膜155覆盖。例如,绝缘膜155可以包含SiO2和SiN中的至少一种。连接焊盘150的上表面上未被绝缘膜155覆盖的部分,换句话说,绝缘膜155的上部开口部的直径可以形成为大于凸块4a的直径。
利用这种构成,即使连接焊盘150和凸块4a之间的位置存在一些差异,也能够确实地将连接焊盘150和发光元件321的用作阳极的电极142通过凸块4a连接。
之后,如图9C所示,将绝缘树脂102填充在半导体基板2和芯片3之间以及用于连接半导体基板2和芯片3的连接部之间,相邻的凸块4a之间建立绝缘,并且完成光源装置110的组装。
利用这种构成,光源装置110可以使相邻的凸块4a通过绝缘树脂102彼此绝缘,从而防止凸块4a之间的短路故障以及由于冲击力造成的凸块4a的开路故障。
3.效果
电子设备1包括半导体基板2、芯片3和连接部(以凸块4为例)。芯片3可以具有与半导体基板2的热膨胀率不同的热膨胀率。凸块4可以包括用于连接配置在半导体基板2和芯片3的相对的主表面上的连接焊盘21和31的多孔金属层41。
利用这种构成,与半导体基板2和芯片3的连接焊盘21和31通过块状的金属凸块连接的情况相比,电子设备1能够通过在较低温度和较低压力下的处理来连接半导体基板2和芯片3的连接焊盘21和31。因此,电子装置100能够减少由于高温高压造成的损坏,从而可以提高可靠性。
此外,例如,芯片3和半导体基板2的热膨胀率之间的差可以为0.1ppm/℃以上。因此,例如,即使当芯片3产生热量并且以与半导体基板2的热膨胀率不同的热膨胀率膨胀时,由于多孔金属层41发生弹性变形,所以电子设备1也能够防止凸块4处开路故障的发生。
此外,芯片3是半导体激光器,并且半导体基板2包括驱动所述半导体激光器的驱动电路22。因此,即使当芯片3由于半导体激光器的发光产生的热量而以与半导体基板2的热膨胀率不同的热膨胀率膨胀时,由于多孔金属层41发生弹性变形,所以电子设备1也能够防止在凸块4处开路故障的发生。
芯片3可以是或者可以包括半导体激光器。所述半导体基板可以包括温度传感器。利用这种构成,驱动半导体激光器的驱动电路22根据利用温度传感器检测到的发光部32附近的温度向发光部32提供驱动控制,从而能够防止由于温度的变化造成的发光部32的发光特性的变化。
所述半导体激光器包括发光元件321。发光元件321可以二维地排列,各个发光元件发出激光。发光元件321可以具有设置在同一平面上的用作阳极的电极142和用作阴极的电极143。利用这种构成,半导体激光器可以容易地与驱动电路22连接。
半导体基板2可以包括开关154。开关154与用作阳极的相应电极142或用作阴极的相应电极143连接。因此,当测距装置100使用STL方式执行距离测量时,驱动电路22可以通过单独地控制各个开关154来用具有各种类型的点状图案的图案光照射被摄体S。
开关154分别与相应组的发光元件321连接。针对各组而对发光元件321进行发光控制。因此,例如,测距装置100可以通过针对各组的发光元件321改变发光图案来用具有各种类型的图案的图案光照射被摄体S。
此外,开关154与相应的发光元件321连接。各个发光元件321被单独地进行发光控制。因此,测距装置100可以用具有任何期望的发光图案的图案光照射被摄体S。
发光元件321可以形成在共用的基板上。利用这种构成,对于半导体激光器,各发光元件321可以共享一个用作阳极的电极142或用作阴极的电极143。
各个用作阳极的电极142或用作阴极的电极143与各个开关154通过相应的连接部(凸块4)连接。利用这种构成,与半导体基板2和芯片3通过块状的金属凸点连接的情况相比,光源装置110能够通过在较低温度和较低压力下的处理来连接半导体基板2和芯片3。因此,光源装置110能够减少由于高温高压造成的损坏,从而可以提高可靠性。
发光元件321可以具有VCSEL结构。利用这种结构,光源装置110可以减小其功耗,从而能够进行批量生产。
绝缘树脂102可以填充在半导体基板2和芯片3之间以及所述连接部(凸块4)之间。利用这种构成,光源装置110可以使相邻的凸块4通过绝缘树脂102彼此绝缘,从而防止凸块4之间的短路故障和由于冲击力造成的凸块4的开路故障。
此外,多孔金属层41可以包含粒径为0.005μm~1.0μm的金属粒子。由于粒径的尺寸效应,如上所述的多孔金属层41能够在比块状金属的熔点更低的温度下接合金属。因此,半导体基板2和芯片3的连接焊盘21和31可以通过能够在相对较低的温度下使金属接合的多孔金属层41连接,从而使电子设备1能够减少由于热量造成的损坏并提高可靠性。
此外,凸块4可以至少在多孔金属层41和半导体基板2侧的连接焊盘21之间或者在多孔金属层41和芯片3侧的连接焊盘31之间包括具有与多孔金属层41的成分相同成分的金属膜42和43。
因此,即使当连接焊盘21和31的成分与多孔金属层41的成分不同时,使用金属膜42和43以及多孔金属层41也可以牢固地连接连接焊盘21和31。
此外,金属膜42和43可以是被形成为使在形成凸块4和4a的过程中使用的图案化后的光刻胶层51和52的表面硬化的薄膜。因此,可以形成具有微细结构的凸块4和4a,从而可以实现凸块4和4a的微细间距。
此外,金属膜42可以形成为使金属膜42的膜厚度与凸块4在垂直于半导体基板2的主表面的方向上的高度的比率被设定为小于10%,优选小于5%。此外,金属膜43形成为使金属膜43的膜厚度与凸块4a在垂直于芯片3的主表面的方向上的高度的比率被设定为10%以下,优选小于5%。
因此,可以防止在光刻胶层51和52上被图案化的用于形成凸块4和4a的通孔由于金属膜42和43的形成而变窄。结果,可以用包含作为凸块4和4a的材料的金属粒子的糊剂40适当地填充在光刻胶层51和52上被图案化的通孔。
此外,在其中半导体基板2和芯片3通过凸块4和凸块4a连接的电子设备中,金属膜42和43可以形成为使得膜厚度与凸块4和4a的层叠体在垂直于半导体基板2和芯片3的主表面的方向上的厚度的一半的比率被设定为10%以下,优选小于5%。
因此,可以防止在光刻胶层51和52上被图案化的用于形成凸块4和4a的通孔由于金属膜42和43的形成而变窄。结果,可以用包含作为凸块4和4a的材料的金属粒子的糊剂40适当地填充在光刻胶层51和52上被图案化的通孔。
此外,电子设备1包括半导体基板2和凸块4。凸块4可以包括顺次沉积在配置于半导体基板2的主表面上的连接焊盘21的表面上的金属膜42和多孔金属层41。例如,金属膜42可以形成为使得膜厚度与凸块4在垂直于半导体基板2的主表面的方向上的厚度的比率被设定为10%以下。
因此,与使用由块状金属制成的凸块的情况相比,半导体基板2能够通过较低温度和较低压力下的处理来实现凸块4的微细间距,并且实现热膨胀率与半导体基板2的热膨胀率不同的芯片3的倒装芯片安装。
例如,半导体基板2可以包括驱动通过倒装芯片安装而安装在半导体基板2上的半导体激光器的驱动电路22。通过控制将发光元件321中的用作阳极的各电极142和电流源连接的各个开关154,驱动电路22能够以独立的方式控制包括在半导体激光器中的发光元件。利用这种构成,当测距装置100使用STL方式执行距离测量时,驱动电路22可以通过光源装置110用具有各种类型的点状图案的图案光照射被摄体S。
此外,电子设备1包括芯片3和凸块4a。凸块4a可以包括顺次沉积在配置于芯片3的主表面上的连接焊盘31上的金属膜43和多孔金属层41。金属膜43可以形成为使得膜厚度与凸块4a在垂直于芯片3的主表面的方向上的比率被设定为10%以下。
因此,与使用由块状金属制成的凸块的情况相比,芯片3能够通过较低温度和较低压力下的处理来实现凸块4a的微细间距,并且实现热膨胀率与芯片3的热膨胀率不同的半导体基板2的倒装芯片安装。
芯片3可以是半导体激光器。所述半导体激光器包括发光元件321。发光元件321可以二维地排列,各个发光元件发出激光。发光元件321可以具有安装在同一平面上的用作阳极的电极142和用作阴极的电极143。利用这种构成,半导体激光器可以容易地与驱动电路22连接。
芯片3可以通过配置在其间的凸块4接合在驱动电路22上,从而可以减小安装基板101的面积。
本说明书中记载的效果仅仅是说明性或示例性的,而非限制性的。即,可以实现其他效果。
以下构成也落在本公开的技术范围内。
(1)一种电子设备,包括:
半导体基板;
芯片,其具有与所述半导体基板的热膨胀率不同的热膨胀率;和
连接部,其包括用于连接配置在所述半导体基板和所述芯片的相对的主表面上的连接焊盘的多孔金属层。
(2)根据上述(1)所述的电子设备,其中,所述芯片与所述半导体基板的热膨胀率之间的差为0.1ppm/℃以上。
(3)根据上述(1)或(2)所述的电子设备,其中,
所述芯片是半导体激光器,并且
所述半导体基板包括驱动所述半导体激光器的驱动电路。
(4)根据上述(1)至(3)中任一项所述的电子设备,其中,
所述芯片是半导体激光器,并且
所述半导体基板包括温度传感器。
(5)根据上述(3)或(4)所述的电子设备,其中,
所述半导体激光器包括二维排列的多个发光元件,各个所述发光元件发出激光,并且
各个所述发光元件具有设置在同一平面上的用作阳极的电极和用作阴极的电极。
(6)根据上述(5)所述的电子设备,其中,
所述半导体基板包括开关,并且
所述开关与所述用作阳极的电极或所述用作阴极的电极连接。
(7)根据上述(6)所述的电子设备,其中,
所述开关与相应组的发光元件连接,并且
针对所述相应组而对所述发光元件进行发光控制。
(8)根据上述(6)所述的电子设备,其中,
多个所述开关与相应的发光元件连接,并且
各个所述发光元件被单独地进行发光控制。
(9)根据上述(6)至(8)中任一项所述的电子设备,其中,各个所述用作阳极的电极或各个所述用作阴极的电极与各个所述开关通过所述连接部连接。
(10)根据上述(5)至(9)中任一项所述的电子设备,其中,所述发光元件形成在共用的基板上。
(11)根据上述(5)至(10)中任一项所述的电子设备,其中,所述发光元件具有垂直腔面发射激光器(VCSEL)结构。
(12)根据上述(1)至(11)中任一项所述的电子设备,其中,绝缘树脂填充在所述半导体基板和所述芯片之间以及所述连接部之间。
(13)根据上述(1)至(12)中任一项所述的电子设备,其中,所述多孔金属层包括粒径为0.005μm~1.0μm的金属粒子。
(14)根据上述(1)至(13)中任一项所述的电子设备,其中,
所述连接部至少在所述多孔金属层和所述半导体基板侧的连接焊盘之间或者在所述多孔金属层和所述芯片侧的连接焊盘之间包括具有与所述多孔金属层的成分相同成分的金属膜。
(15)根据上述(14)所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的比率被设定为10%以下。
(16)根据上述(15)所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的比率被设定为小于5%。
(17)根据上述(14)所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的一半的比率被设定为10%以下。
(18)根据上述(17)所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的一半的比率被设定为小于5%。
(19)根据上述(1)至(18)中任一项所述的电子设备,其中,所述多孔金属层与所述连接部之间在垂直于所述主表面的方向上的高度比大于90%。
(20)一种电子设备,包括:
半导体基板;和
凸块,其包括顺次沉积在配置于所述半导体基板的主表面上的连接焊盘的表面上的金属膜和多孔金属层,其中,
所述金属膜形成为使得膜厚度与所述凸块在垂直于所述主表面的方向上的厚度的比率被设定为10%以下。
(21)根据上述(20)所述的电子设备,其中,
所述半导体基板包括驱动通过倒装芯片安装而安装在所述半导体基板上的半导体激光器的驱动电路,并且
通过相应地控制将包括在所述半导体激光器中的多个发光元件和电流源连接的各个开关,所述驱动电路以独立的方式控制各个所述发光元件。
(22)一种电子设备,包括:
芯片;和
凸块,其包括顺次沉积在配置于所述芯片的主表面上的连接焊盘的表面上的金属膜和多孔金属层,其中,
所述金属膜形成为使得膜厚度与所述凸块在垂直于所述主表面的方向上的厚度的比率被设定为10%以下。
(23)根据上述(22)所述的电子设备,其中,
所述芯片是半导体激光器,
所述半导体激光器包括二维排列的多个发光元件,各个所述发光元件发出激光,并且
各个所述发光元件具有设置在同一平面上的用作阳极的电极和用作阴极的电极。
尽管为了完整和清楚的公开,已经相对于具体的实施方案说明了本发明,但所附权利要求不应因此受到限制,而是应当被解释为体现落入本文所说明的基本教示之内的本领域技术人员可能想到的所有变形和替代结构。上面与一个或多个先前所述的示例和附图一起提到和说明的各方面和特征也可以与一个或多个其他示例组合,以替代其他示例的类似特征或为了额外地将该特征引入另一个示例。例如,上述详细说明中提供的结构和/或功能细节同样适用于参照构成(19)~(23)所述构成的电子设备。
Claims (23)
1.一种电子设备,包括:
半导体基板;
芯片,其具有与所述半导体基板的热膨胀率不同的热膨胀率;和
连接部,其包括用于连接配置在所述半导体基板和所述芯片的相对的主表面上的连接焊盘的多孔金属层。
2.根据权利要求1所述的电子设备,其中,所述芯片与所述半导体基板的热膨胀率之间的差为0.1ppm/℃以上。
3.根据权利要求1所述的电子设备,其中,
所述芯片是半导体激光器,并且
所述半导体基板包括驱动所述半导体激光器的驱动电路。
4.根据权利要求1所述的电子设备,其中,
所述芯片是半导体激光器,并且
所述半导体基板包括温度传感器。
5.根据权利要求3所述的电子设备,其中,
所述半导体激光器包括二维排列的多个发光元件,各个所述发光元件发出激光,并且
各个所述发光元件具有设置在同一平面上的用作阳极的电极和用作阴极的电极。
6.根据权利要求5所述的电子设备,其中,
所述半导体基板包括开关,并且
所述开关与所述用作阳极的电极或所述用作阴极的电极连接。
7.根据权利要求6所述的电子设备,其中,
所述开关与相应组的发光元件连接,并且
针对所述相应组而对所述发光元件进行发光控制。
8.根据权利要求6所述的电子设备,其中,
多个所述开关与相应的发光元件连接,并且
各个所述发光元件被单独地进行发光控制。
9.根据权利要求6所述的电子设备,其中,各个所述用作阳极的电极或各个所述用作阴极的电极与各个所述开关通过所述连接部连接。
10.根据权利要求5所述的电子设备,其中,所述发光元件形成在共用的基板上。
11.根据权利要求5所述的电子设备,其中,所述发光元件具有垂直腔面发射激光器(VCSEL)结构。
12.根据权利要求1所述的电子设备,其中,绝缘树脂填充在所述半导体基板和所述芯片之间以及所述连接部之间。
13.根据权利要求1所述的电子设备,其中,所述多孔金属层包含粒径为0.005μm~1.0μm的金属粒子。
14.根据权利要求1所述的电子设备,其中,
所述连接部至少在所述多孔金属层和所述半导体基板侧的连接焊盘之间或者在所述多孔金属层和所述芯片侧的连接焊盘之间包括具有与所述多孔金属层的成分相同成分的金属膜。
15.根据权利要求14所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的比率被设定为10%以下。
16.根据权利要求15所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的比率被设定为小于5%。
17.根据权利要求14所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的一半的比率被设定为10%以下。
18.根据权利要求17所述的电子设备,其中,所述金属膜形成为使膜厚度与所述连接部在垂直于所述主表面的方向上的厚度的一半的比率被设定为小于5%。
19.根据权利要求1所述的电子设备,其中,所述多孔金属层与所述连接部之间在垂直于所述主表面的方向上的高度比大于90%。
20.一种电子设备,包括:
半导体基板;和
凸块,其包括顺次沉积在配置于所述半导体基板的主表面上的连接焊盘的表面上的金属膜和多孔金属层,其中,
所述金属膜形成为使得膜厚度与所述凸块在垂直于所述主表面的方向上的厚度的比率被设定为10%以下。
21.根据权利要求20所述的电子设备,其中,
所述半导体基板包括驱动通过倒装芯片安装而安装在所述半导体基板上的半导体激光器的驱动电路,并且
通过相应地控制将包括在所述半导体激光器中的多个发光元件和电流源连接的各个开关,所述驱动电路以独立的方式控制各个所述发光元件。
22.一种电子设备,包括:
芯片;和
凸块,其包括顺次沉积在配置于所述芯片的主表面上的连接焊盘的表面上的金属膜和多孔金属层,其中,
所述金属膜形成为使得膜厚度与所述凸块在垂直于所述主表面的方向上的厚度的比率被设定为10%以下。
23.根据权利要求22所述的电子设备,其中,
所述芯片是半导体激光器,
所述半导体激光器包括二维排列的多个发光元件,各个所述发光元件发出激光,并且
各个所述发光元件具有设置在同一平面上的用作阳极的电极和用作阴极的电极。
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WO2022130825A1 (ja) * | 2020-12-15 | 2022-06-23 | ソニーグループ株式会社 | 面発光レーザ装置 |
CN117059637A (zh) * | 2022-05-13 | 2023-11-14 | 印正有限公司 | 驱动芯片 |
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