CN113299750A - 半导体功率器件 - Google Patents

半导体功率器件 Download PDF

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CN113299750A
CN113299750A CN202010106676.4A CN202010106676A CN113299750A CN 113299750 A CN113299750 A CN 113299750A CN 202010106676 A CN202010106676 A CN 202010106676A CN 113299750 A CN113299750 A CN 113299750A
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drift region
type
gate
type drift
semiconductor power
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龚轶
刘磊
刘伟
毛振东
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Suzhou Dongwei Semiconductor Co ltd
Suzhou Oriental Semiconductor Co Ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to PCT/CN2020/116681 priority patent/WO2021164246A1/zh
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Abstract

本发明属于半导体功率器件技术领域，具体公开了一种半导体功率器件，包括：n型外延层，以及位于所述n型外延层内的：自下而上的第一n型漂移区、第二n型漂移区和第三n型漂移区，所述第一n型漂移区的掺杂浓度和所述第三n型漂移区的掺杂浓度均大于所述第二n型漂移区的掺杂浓度；至少一个栅沟槽以及位于所述栅沟槽内的栅极结构，所述栅沟槽的底部不高于所述第二n型漂移区的上表面；位于所述栅沟槽的两侧且位于所述第三n型漂移区之上的p型体区，以及位于所述p型体区中的n型源区。本发明可以提高半导体功率器件的击穿电压并降低半导体功率器件的导通电阻。

Description

半导体功率器件
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种包含多层n型漂移区的半导体功率器件。
背景技术
现有技术的半导体功率器件通常是通过深沟槽工艺在外延层内形成沟槽，通过在沟槽内填充介质层与多晶硅屏蔽栅形成垂直方向的RESURF(Reduced Surface Field，降低表面电场)结构，从而改善半导体功率器件的击穿电压和导通电阻等性能。通过提高外延层的掺杂浓度可以降低半导体功率器件的导通电阻，但是外延层的掺杂浓度的提高会使得沟槽底部位置处的电荷难以耗尽，而沟槽底部位置处的电场比较集中，使得半导体功率器件无法得到更高的击穿电压。
发明内容
有鉴于此，本发明的目的是提供一种半导体功率器件，以解决现有技术的半导体功率器件的导通电阻和击穿电压难以同时调整的问题。
为达到本发明的上述目的，本发明提供了一种半导体功率器件，包括：
n型外延层，以及位于所述n型外延层内的：
自下而上的第一n型漂移区、第二n型漂移区和第三n型漂移区，所述第一n型漂移区的掺杂浓度和所述第三n型漂移区的掺杂浓度均大于所述第二n型漂移区的掺杂浓度；
至少一个栅沟槽以及位于所述栅沟槽内的栅极结构，所述栅沟槽的底部不高于所述第二n型漂移区的上表面；
位于所述栅沟槽的两侧且位于所述第三n型漂移区之上的p型体区，以及位于所述p型体区中的n型源区。
可选的，所述栅沟槽的底部不低于所述第二n型漂移区的下表面。
可选的，所述栅沟槽的底部低于所述第二n型漂移区的下表面，所述栅沟槽的底部位于所述第一n型漂移区内。
可选的，还包括位于所述第三n型漂移区内的n型电场调制层，所述n型电场调制层的掺杂浓度大于所述第三n型漂移区的掺杂浓度。
可选的，所述栅极结构包括屏蔽栅和栅极，所述栅极、所述屏蔽栅和所述n型外延层两两之间由绝缘介质层隔离。
可选的，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
可选的，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内且所述屏蔽栅向上延伸至所述栅沟槽的上部内。
可选的，在所述栅沟槽的上部内，所述栅极位于所述屏蔽栅的两侧。
可选的，在所述栅沟槽的上部内，所述栅极环绕包围所述屏蔽栅。
可选的，还包括n型漏区，所述第一n型漂移区位于所述n型漏区之上。
本发明提供的一种半导体功率器件在降低半导体功率器件的导通电阻的同时还可以提高半导体功率器件的击穿电压。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明提供的一种半导体功率器件的第一个实施例的剖面结构示意图；
图2是本发明提供的一种半导体功率器件的第二个实施例的剖面结构示意图；
图3是本发明提供的一种半导体功率器件的第三个实施例的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1是本发明提供的一种半导体功率器件的第一个实施例的剖面结构示意图，图2是本发明提供的一种半导体功率器件的第二个实施例的剖面结构示意图。如图1和图2所示，本发明实施列提供的一种半导体功率器件包括：n型外延层，n型外延层的材质通常为硅，位于所述n型外延层内且自下而上的第一n型漂移区21、第二n型漂移区22和第三n型漂移区23，第一n型漂移区21的掺杂浓度和第三n型漂移区23的掺杂浓度均大于第二n型漂移区22的掺杂浓度。
凹陷在所述n型外延层内的至少一个栅沟槽，图1中仅示例性的示出了3个栅沟槽，位于所述栅沟槽内的栅极结构，所述栅极结构包括栅极25、屏蔽栅27，栅极25通过栅介质层24与n型外延层隔离，屏蔽栅27通过场氧化层26与n型外延层和栅极25隔离。可选的，在栅沟槽内，栅极25位于栅沟槽上部内，屏蔽栅27仅位于栅沟槽下部内，由此栅极25和屏蔽栅27为上下结构关系(该结构在本发明实施例中未示出)；进一步可选的，在栅沟槽内，栅极25位于栅沟槽的上部内，屏蔽栅27位于栅沟槽的下部内且屏蔽栅27向上延伸至栅沟槽的上部内，如图1所示。当屏蔽栅27向上延伸至栅沟槽的上部内时，在栅沟槽的上部内，栅极25可以是位于屏蔽栅27两侧，也可以是栅极25环绕包围屏蔽栅27，该结构在本发明实施例中不再详细展示。
栅沟槽的底部不高于第二n型漂移区22的上表面，具体可以是栅沟槽的底部与第二n型漂移区22的上表面齐平(图中未示出)；也可以是栅沟槽的底部可以低于第二n型漂移区22的上表面并高于或等于第二n型漂移区22的下表面，即栅沟槽的底部位于第二n型漂移区22内(如图1所示)或者栅沟槽的底部与第二n型漂移区22的下表面持平；栅沟槽的底部也可以是低于第二n型漂移区22的下表面，使得栅沟槽的底部位于第一n型漂移区21内，如图2所示。
位于所述栅沟槽的两侧且位于第三n型漂移区23之上的p型体区28，以及位于p型体区28中的n型源区29。
本发明的半导体功率器件还包括n型漏区20，第一n型漂移区21位于n型漏区20之上，n型漏区20通过漏极金属层外接漏极电压。
本发明的半导体功率器件，使栅沟槽的底部不高于第二n型漂移区的上表面，例如使栅沟槽的底部位于第二n型漂移区内或者位于第二n型漂移区的附近，由于第二n型漂移区具有低的掺杂浓度，因此电荷容易耗尽，可以提高半导体功率器件的击穿电压。同时，由于第一n型漂移区的掺杂浓度和第三n型漂移区的掺杂浓度均大于第二n型漂移区的掺杂浓度，这可以降低半导体功率器件的导通电阻。
需要说明的是，本发明实施例对第一n型漂移区的掺杂浓度和第三n型漂移区的掺杂浓度的大小不进行限定，可以是第一n型漂移区的掺杂浓度大于第三n型漂移区的掺杂浓度，也可以是第三n型漂移区的掺杂浓度大于第一n型漂移区的掺杂浓度，还可以是第三n型漂移区的掺杂浓度等于第一n型漂移区的掺杂浓度，本发明实施例对此不进行限定，只需保证第一n型漂移区的掺杂浓度和第三n型漂移区的掺杂浓度均大于第二n型漂移区的掺杂浓度，保证可以降低半导体功率器件的导通电阻即可。
图3是本发明提供的一种半导体功率器件的第三个实施例的剖面结构示意图，在该实施例中，在第三n型漂移区23内的还形成有n型电场调制层30，n型电场调制层30的掺杂浓度大于第三n型漂移区23的掺杂浓度，用以提升第三n型漂移区23的电场均值，这可以进一步降低半导体功率器件的导通电阻。
以上具体实施方式及实施例是对本发明提出的一种半导体功率器件的技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (10)

1.半导体功率器件，其特征在于，包括：
n型外延层，以及位于所述n型外延层内的：
自下而上的第一n型漂移区、第二n型漂移区和第三n型漂移区，所述第一n型漂移区的掺杂浓度和所述第三n型漂移区的掺杂浓度均大于所述第二n型漂移区的掺杂浓度；
至少一个栅沟槽以及位于所述栅沟槽内的栅极结构，所述栅沟槽的底部不高于所述第二n型漂移区的上表面；
位于所述栅沟槽的两侧且位于所述第三n型漂移区之上的p型体区，以及位于所述p型体区中的n型源区。
2.如权利要求1所述的半导体功率器件，其特征在于，所述栅沟槽的底部不低于所述第二n型漂移区的下表面。
3.如权利要求1所述的半导体功率器件，其特征在于，所述栅沟槽的底部低于所述第二n型漂移区的下表面，所述栅沟槽的底部位于所述第一n型漂移区内。
4.如权利要求1所述的半导体功率器件，其特征在于，还包括位于所述第三n型漂移区内的n型电场调制层，所述n型电场调制层的掺杂浓度大于所述第三n型漂移区的掺杂浓度。
5.如权利要求1所述的半导体功率器件，其特征在于，所述栅极结构包括屏蔽栅和栅极，所述栅极、所述屏蔽栅和所述n型外延层两两之间由绝缘介质层隔离。
6.如权利要求5所述的半导体功率器件，其特征在于，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内。
7.如权利要求5所述的半导体功率器件，其特征在于，所述栅极位于所述栅沟槽的上部内，所述屏蔽栅位于所述栅沟槽的下部内且所述屏蔽栅向上延伸至所述栅沟槽的上部内。
8.如权利要求7所述的半导体功率器件，其特征在于，在所述栅沟槽的上部内，所述栅极位于所述屏蔽栅的两侧。
9.如权利要求7所述的半导体功率器件，其特征在于，在所述栅沟槽的上部内，所述栅极环绕包围所述屏蔽栅。
10.如权利要求1所述的半导体功率器件，其特征在于，还包括n型漏区，所述第一n型漂移区位于所述n型漏区之上。
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