CN1132188C - 具有多个存储体的半导体存储器 - Google Patents
具有多个存储体的半导体存储器 Download PDFInfo
- Publication number
- CN1132188C CN1132188C CN98124964A CN98124964A CN1132188C CN 1132188 C CN1132188 C CN 1132188C CN 98124964 A CN98124964 A CN 98124964A CN 98124964 A CN98124964 A CN 98124964A CN 1132188 C CN1132188 C CN 1132188C
- Authority
- CN
- China
- Prior art keywords
- signal
- bank
- word line
- sensor amplifier
- precharging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 230000003213 activating effect Effects 0.000 claims abstract description 16
- 230000004913 activation Effects 0.000 claims description 105
- 238000000034 method Methods 0.000 claims description 6
- 238000007600 charging Methods 0.000 claims description 5
- 230000008859 change Effects 0.000 description 8
- 230000008520 organization Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000014509 gene expression Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 241000193935 Araneus diadematus Species 0.000 description 1
- 101150064138 MAP1 gene Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005039 memory span Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (7)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP328827/1997 | 1997-11-28 | ||
JP328827/97 | 1997-11-28 | ||
JP32882797A JP3259764B2 (ja) | 1997-11-28 | 1997-11-28 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1222738A CN1222738A (zh) | 1999-07-14 |
CN1132188C true CN1132188C (zh) | 2003-12-24 |
Family
ID=18214534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN98124964A Expired - Lifetime CN1132188C (zh) | 1997-11-28 | 1998-11-25 | 具有多个存储体的半导体存储器 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6088292A (zh) |
EP (1) | EP0920024B1 (zh) |
JP (1) | JP3259764B2 (zh) |
KR (1) | KR100304771B1 (zh) |
CN (1) | CN1132188C (zh) |
DE (1) | DE69828021T2 (zh) |
TW (1) | TW434879B (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6526471B1 (en) * | 1998-09-18 | 2003-02-25 | Digeo, Inc. | Method and apparatus for a high-speed memory subsystem |
JP2000195262A (ja) * | 1998-12-25 | 2000-07-14 | Internatl Business Mach Corp <Ibm> | Sdram及びsdramのデ―タ・アクセス方法 |
US6229744B1 (en) * | 1999-10-28 | 2001-05-08 | Vangard International Semiconductor Corp. | Semiconductor memory device with function of equalizing voltage of dataline pair |
JP4514945B2 (ja) * | 2000-12-22 | 2010-07-28 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP4808856B2 (ja) * | 2001-04-06 | 2011-11-02 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
KR100813525B1 (ko) | 2005-12-27 | 2008-03-17 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 센스 앰프 제어 회로 및 방법 |
KR100838364B1 (ko) * | 2006-12-27 | 2008-06-13 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 감지증폭 인에이블 신호 생성회로 |
KR100884761B1 (ko) * | 2007-02-22 | 2009-02-20 | 엠텍비젼 주식회사 | 센스 엠프 인에이블 신호 발생 회로, 이를 가지는 메모리장치 및 센스 엠프 인에이블 신호 발생 방법 |
DE102007036989B4 (de) * | 2007-08-06 | 2015-02-26 | Qimonda Ag | Verfahren zum Betrieb einer Speichervorrichtung, Speichereinrichtung und Speichervorrichtung |
KR100967111B1 (ko) | 2008-11-06 | 2010-07-05 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR101043731B1 (ko) | 2008-12-30 | 2011-06-24 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR101633399B1 (ko) * | 2009-04-27 | 2016-06-27 | 삼성전자주식회사 | 뱅크 프리차지 동작 시에 각 뱅크별 프리차지 동작 시점을 조절할 수 있는 반도체 메모리 장치의 프리차지 방법 및 이 방법을 이용하는 반도체 메모리 장치 |
KR101136984B1 (ko) * | 2010-03-29 | 2012-04-19 | 에스케이하이닉스 주식회사 | 전압 공급 제어회로 및 이를 이용한 반도체 장치 |
JP5404584B2 (ja) * | 2010-11-19 | 2014-02-05 | 株式会社東芝 | 半導体記憶装置 |
KR20130139066A (ko) * | 2012-06-12 | 2013-12-20 | 삼성전자주식회사 | 소스라인 전압 발생기를 포함하는 자기 저항 메모리 장치 |
US11361815B1 (en) * | 2020-12-24 | 2022-06-14 | Winbond Electronics Corp. | Method and memory device including plurality of memory banks and having shared delay circuit |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5036493A (en) * | 1990-03-15 | 1991-07-30 | Digital Equipment Corporation | System and method for reducing power usage by multiple memory modules |
JP2739802B2 (ja) * | 1992-12-01 | 1998-04-15 | 日本電気株式会社 | ダイナミックram装置 |
JP2988804B2 (ja) * | 1993-03-19 | 1999-12-13 | 株式会社東芝 | 半導体メモリ装置 |
US5559752A (en) * | 1995-08-14 | 1996-09-24 | Alliance Semiconductor Corporation | Timing control circuit for synchronous static random access memory |
JPH09288614A (ja) * | 1996-04-22 | 1997-11-04 | Mitsubishi Electric Corp | 半導体集積回路装置、半導体記憶装置およびそのための制御回路 |
TW340262B (en) * | 1996-08-13 | 1998-09-11 | Fujitsu Ltd | Semiconductor device, system consisting of semiconductor devices and digital delay circuit |
US6115318A (en) * | 1996-12-03 | 2000-09-05 | Micron Technology, Inc. | Clock vernier adjustment |
JP3255282B2 (ja) * | 1998-01-13 | 2002-02-12 | 日本電気株式会社 | 半導体記憶装置 |
JP3221483B2 (ja) * | 1998-02-25 | 2001-10-22 | 日本電気株式会社 | 半導体記憶装置 |
-
1997
- 1997-11-28 JP JP32882797A patent/JP3259764B2/ja not_active Expired - Fee Related
-
1998
- 1998-11-24 TW TW087119516A patent/TW434879B/zh not_active IP Right Cessation
- 1998-11-24 US US09/199,052 patent/US6088292A/en not_active Expired - Lifetime
- 1998-11-25 CN CN98124964A patent/CN1132188C/zh not_active Expired - Lifetime
- 1998-11-27 KR KR1019980051390A patent/KR100304771B1/ko not_active IP Right Cessation
- 1998-11-28 EP EP98250416A patent/EP0920024B1/en not_active Expired - Lifetime
- 1998-11-28 DE DE69828021T patent/DE69828021T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP3259764B2 (ja) | 2002-02-25 |
EP0920024A3 (en) | 1999-06-30 |
CN1222738A (zh) | 1999-07-14 |
KR100304771B1 (ko) | 2001-09-24 |
JPH11162161A (ja) | 1999-06-18 |
DE69828021D1 (de) | 2005-01-13 |
DE69828021T2 (de) | 2005-12-01 |
TW434879B (en) | 2001-05-16 |
US6088292A (en) | 2000-07-11 |
EP0920024A2 (en) | 1999-06-02 |
KR19990045665A (ko) | 1999-06-25 |
EP0920024B1 (en) | 2004-12-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NONE Effective date: 20030523 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20030523 Address after: Tokyo, Japan Applicant after: NEC Corp. Co-applicant after: NEC ELECTRONICS Corp. Address before: Tokyo, Japan Applicant before: NEC Corp. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: ERBIDA MEMORY CO., LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD.; NEC ELECTRONICS TAIWAN LTD. Effective date: 20070209 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20070209 Address after: Tokyo, Japan Patentee after: Elpida Memory, Inc. Address before: Tokyo, Japan Co-patentee before: NEC ELECTRONICS Corp. Patentee before: NEC Corp. |
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ASS | Succession or assignment of patent right |
Owner name: PS4 LASCO CO., LTD. Free format text: FORMER OWNER: ELPIDA MEMORY INC. Effective date: 20130905 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20130905 Address after: Luxemburg Luxemburg Patentee after: PS4 Russport Co.,Ltd. Address before: Tokyo, Japan Patentee before: Elpida Memory, Inc. |
|
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Luxemburg Luxemburg Patentee after: Longitude Semiconductor Co.,Ltd. Address before: Luxemburg Luxemburg Patentee before: PS5 Laskou Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20171114 Address after: Luxemburg Luxemburg Patentee after: PS5 Laskou Co.,Ltd. Address before: Luxemburg City Patentee before: PS4 Russport Co.,Ltd. |
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CX01 | Expiry of patent term |
Granted publication date: 20031224 |
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CX01 | Expiry of patent term |