TW434879B - Semiconductor memory device having a plurality of storage units - Google Patents

Semiconductor memory device having a plurality of storage units Download PDF

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Publication number
TW434879B
TW434879B TW087119516A TW87119516A TW434879B TW 434879 B TW434879 B TW 434879B TW 087119516 A TW087119516 A TW 087119516A TW 87119516 A TW87119516 A TW 87119516A TW 434879 B TW434879 B TW 434879B
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Taiwan
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signal
storage group
activated
output
circuit
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TW087119516A
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Chinese (zh)
Inventor
Hiroki Takahashi
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Nippon Electric Co
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

A semiconductor memory device comprises a plurality of storage units, a timing control circuit and latch circuits. The timing control circuit connects those storage units and outputs a signal for initializing each storage units, and a signal to pre-charge each storage units in predetermined sequence in predetermined timing. Each latch circuit connects each storage unit for latching the output signal status of the timing control circuit.

Description

434870 " Λ*? Η ? 經濟部中央標隼局貝工消费合作社印聚 五、發明説明（1 ) — 本發明是有關於一種半導體記憶裝置，且特別是有關 於一種半導體記憶裝置，其記憶區由複數儲存組構成。 通常’在習知半導體記憶裝置（如DRAM)中，記憶胞 是形成於複數位元線對及複數字元線的交點。目標記憶 胞的記憶資訊則以列位址選擇字元線及以行位址選擇位 元線對以讀出。 在習知半導體記憶裝置（如dram)中，記憶區會根據 記憶容量的增加及位元線對的長度限制而分成複數個區 塊。 為讀出由複數個區塊所構成的半導體記憶裝置中記憶 胞所儲存的記憶資訊，首先指派列位址，然後指派行位 址及區塊位址。待位址指派後，各種動作（如資料寫入及 讀取）便根據外部命令之接收以進行。 第1圖（第一習知技術）係由複數區塊所構成之半導體 記憶裝置之方塊圖。 在這種習知半導體記憶裝置中，記憶區是由兩區塊121 及122所構成。 半導體記憶裝置包括區塊121反122，位址緩衝器91， 及時序控制電路93 〇 當列位址啟動信號30啟動時，時序控制電路93啟動 位址致能信號100 ’並在預定時序以預定順序她將字元 線驅動信號97、預充電信號98、感應放大器致能信號99 由高位址（H)改變至低位準（L)或由低位準（L)改變至高位 準（H)。 本紙張尺度適用中國國家標準（CNS Μ心見柏（2丨0Χ 297公# ) 諳 Λ 閱· 讀 背 面 之 注 再 裝 訂 __R? 五、發明説明（2) 列位址啟動信號30是由外部命令啟動。 當列位址致能信號100啟動時，位址緩衝器91閂鎖 及輸出包含於位址信號32之列位址以作為列位址信號， 並改變區塊選擇信號90!或902以啟動位址信號32之區 塊位址所指派的區塊。 區塊121是由位元線對41广41„、字元線' SAP、SAN、複數記憶胞17(分別排列於位元線對41广4ίη 及字元線40广40m的交界）、預充電電路分別排 列於位元線對41广41n)、預充電電路19(排列於SAP及 SAN之間）、感應放大器29广29n(分別排列於位元線對 41广41n)、列解碼器115,、AND電路101、OR電路102、 反相器103、AND電路104、反相器42、p通道MOS電 晶體38、η通道MOS電晶體39所構成。 AND電路1〇1對字元線驅動信號97及區塊選擇信號 9〇ι進行AND運算，並輸出其結果以作為字元線驅動信 號7'。 當字元線驅動信號7,改變至Η時，列解碼器1151會 由字元線40,-4(^地啟動列位址信號33所指派的字元 線。 如第2圖所示，列解碼器115,由於位址解碼器 140,〜140mm構成。 位址解碼器140^14(^分別排列於字元線40广40, 在位址解碼器140^14(^中，對應字元線的位址係設定。 當字元線驅動信號7,改變至Η時’位址解碼器140广140m 本紙張尺度適用中國國家標準（CMS ) Μ現栴（210X297々>t ) 請 閱. η 背 $3 之 注* 意 事 項- 再 裝 ，訂 經濟部中央標率局頁工消费合作社印製 434879 Λ7 Η7 五、發明説明（3) 便動作。若列位址信號33表示的位址為設定位址，各位 址解碼器便啟動對應的字元線。 反相器103將區塊選擇信號90,的邏輯狀態反相，並 輸出其反相結果。 OR電路102對反相器1〇3的輸出信號及預充電信號 98進行OR運算，並輸出其結果。 當OR電路102的輸出信號改變至η時，預充電電路 181〜18η會預充電位元線對411〜4in，固定其電位，並維 持於相同位準《同樣地，當〇R電路1 〇2的輸出信號改 變至Η時’預充電電路19會預充電SAP及SAN，固定 其電位，並維持於相同位準。 AND電路i〇4對感應放大器致能信號99及區塊選擇 信號90!進行AND運算，並輸出其結果以作為感應放大 器致能信號\。 反相器42將感應放大器致能信號9!的邏輯狀態反 相。 反相器42的輸出信號輸入至p通道MOS電晶體38 的閘極。當反相器42的輸出信號改變至l時，p通道MOS 電晶體38會導通以施加電壓vDD至SAP。 感應放大器致能信號1輸入至n通道]y[〇S電晶體39 的閘極。當感應放大器致能信號9,改變至η時.，n通道 MOS電晶體會導通以施加地點電壓至san。 當Ρ通道MOS電晶體38及η通道MOS電晶體同時 導通時’感應放大器29广29„會動作以放大位元線對 本紙張尺度適用中國國家標车（CNS) Λ视格（2]οχ297公垃） 請 先 閲， 之 :主， 意 事 項- 再 經濟部中夾標準局員工消费合作社印^ 434879 ^ Λ? ________— ΙΠ五、發明説明（4 ) 經濟部中央標準局員工消费合作社印裝 1广41n的輸出電壓，並經由行選擇電路及輸入/輸出電 路（均未圖示）以輸出放大信號。 區塊122的排列與區塊121相同，除了輸入區塊選擇 L遽9〇2而非區ί鬼選擇信號9〇]，故其描述將予省略。 習知半導體記憶裝置的動作將配合第id圖及第3圖 時序以說明。 以下說明係有關讀取動作，至於寫入動作則非常類 似。 自區塊121中形成於位元線對4lt&字元線4(^交界 之記憶胞17讀出資料的動作將說明如下。 當外部命令及位址信號32在t41輸入時，外部命令會 啟動列位址啟動信號30，時序控制電路93則啟動位址 致能信號100°位址缓衝器91閂鎖及輸出位址信號32 之列位址以作為列位址信號32。第3圖位址信號32的 空白部分表示列位址讀取的位置。由於區塊位址表示區 塊121，位址緩衝器91改變區塊選擇信號901至H。 在t42，時序控制電路93改變預充電信號98至L，藉 以改變預充電信號1至L，並中斷預充電電路18ι〜18n 及預充電電路19。時序控制電路93改變字元線驅動信 號97至Η，藉以改變字元線驅動信號7!至Η，並啟動 字元線40!。在t43 ’時序控制電路93改變感應放大器致 能信號\至H，藉以導通p通道MOS電晶體38及n通 道MOS電晶體39 ’並啟動感應放大器29广29η。 因此，形成於位元線對41t及字元線4(^交界之記憶 本紙張尺度適用中酬家標導（CNS ) ’鐵格（210x297公没） 請 先 閱 讀 背 1¾ 之 注- 意 事 項- 再 填 % ri % 434879 Λ7 五、發明説明（5) 胞17所儲存之資料’經由位元線對411輸出及放大，並 輸出其放大結果。 在資料讀出後，區塊121 #中斷。特別是，在t44， 時序控制電路93改變字元線驅動信號97至L，藉以改 變字元線驅動信號71至L，並中斷字元線40!。在t45， 時序控制電路93改變感應放大器致能信號99至L，藉 以改變感應放大器致能信號至L，並中斷感應放大器 29广29n。在t46 ’時序控制電路93改變預充電信號98至 Η，藉以改變預充電信號8ι至η，並啟動預充電電路 18广18„及19。也就是，位元線對、SAP、SAN係充 電至給定電壓，且橫跨位元線之電壓設為相同位準p 不過’若半導韙記_憶裝置由複數區塊巍成.，且信號是 由時-序控制.電路93控制，當特定區塊處理時，其他區_塊 便不能處理。當記憶容量及區塊數目增加時，讀出記憶 内容乃花去更多時間。 為解決這個問題，半導體記憶裝置便不以複數區塊構 成，而以複數可獨立動作之错存組構成。 經濟部中央標準局員工消资合作社印製 第4圖（第二習知技術）係由複數儲存組構成之半導體 記憶裝置。與第1圖相同的部分是以相同標號表示。 在這種半導體記憶裝置中，記憶區是由四個儲存組 171〜174構成。 . 這種習知半導體記憶裝置是由儲存組171〜174、時序 控制雷路110广11〇4(分別排列於儲存組171〜174)、閃鎖 電路111广1114(分別排列於時序控制電路llOfUOj、列 本紙張尺度適用中國國家標準（CMS ) 格（210X297公垃} 434879 Λ7 經濟部中央標隼局貝工消费合作社印^ 五、發明説明（ό ) …—_— —- 位址緩衝器45、儲存組解碼器M3所構成。 列位址緩衝器45輪出位址信號32之列位址以作為列 位址信號33。 儲存組解碼器143啟動儲存組選擇信號Ui〜U4預定 時間以啟動位址信號32之儲存组位址表示之儲存組。 閂鎖電路111广Ilk只在對應的儲存組選擇信號 11广1U啟動時讀取列位址啟動信號3〇及列位址中斷信 號3卜若列位址啟動信號3〇啟動時，閂鎖電路m广η、 啟動列位址啟動信號112^若列位址中斷信號31啟動 時，閂鎖電路ill广π、中斷列位址啟動信號112ι。 時序控制電路110广11〇4與第丨圖的時序控制電路93 進行相同動作，除了不輸出位址致能信號1〇〇外。時序 控制電路110广11〇4輸出字元線驅動信號7广7彳而非字元 線驅動號97、預充電信號8广84而非預充電信號98、 感應放大器致能信號9丨〜94而非感應放大器致能信號99 , 並接收列位址啟動信號112!而非列位址啟動信號3〇。 儲存組171是由位元線對41〖〜41n、字元線40广40m、 SAP、SAN、複數記胞17(分別形成於位元線對41广41n 及字元線40广4(^交界）、預充電電路ι8ι〜18η(分別排列 於位元線對40广40n、預充電電路19(排列於SAp及San 之間）、感應放大器29^29/分別排列於位元線對 40广40n)、列解碼器135丨、反相器42、p通道MOS電晶 體38、η通道MOS電晶體39所構成。 當字元線驅動信號7!改變至Η時，列解碼器135,根 本紙張尺度適用中國國家標隼（CNS ) Λ衫见格（21〇Χ297^#_ 請 先 間' 讀 背 之 注* 意 事 項- 再 裝 一肓 .訂 線 434879 A7 n? 五、發明説明（7) —~ 據儲存組選擇信號11,閂鎖列位址信號33，並自字元線 40!至40„依序地啟動列位址信號33字元線所指派的二 如第5圖所示，列解碼器135ι是由位址解碼器 140广140m及閂鎖電路141[所構成。 閂鎖電路1411根據儲存組選擇信號丨！ i閂鎖及輸出列 位址信號33。位址解碼器140广l40m接收閂鎖電路141 所閂鎖及輸出的列位址信號33。 以下將說明第二習知技術半導體記憶裝置之動作。 自儲存組171中形成於位元線對及字元線4〇ι交 界之記憶胞17讀出資料的動作將說明如下。 首先’啟動列位址啟動信號，並由外部輸入位址信號 32(具有表不字元線4(^位址的列位址及表示儲存組pi 的儲存組位址）。然後，列位址緩衝器45輸出位址信號 的列位址以作為列位址信號33，且儲存組解碼器143啟 動儲存組選擇信號llt。 由於儲存組選擇信號11,及列位址啟動信號30係啟 動，閂鎖電路111啟動列位址啟動信號112J。 經濟部中央標準局負工消费合作社印製 由於列位址啟動信號112,係啟動，時序控制電路110 控制字元線驅動信號 '、預充電信號8!、感應放大器致 能信號9,以進行記憶胞17的讀取動作並在讀取後中斷。 此時，由於儲存組選擇信號11!係啟動，列解碼器1351 閂鎖列位址信號33並啟動閂鎖的列位址信號33表示的 字元線4〇i。 本纸張尺度適用中國國家標準（CNS )以规松（21〇Χ25ΠΆ处〉 434Β79 Λ7 _______ in 五、發明説明（8) ' 自儲存組171中讀出記憶胞17的儲存資料時，指派 儲存組172中斷的動作將說明如下。 包含於外部輸入之位址信號32之儲存組位址係切換 以指派儲存組172。儲存組解碼器143中斷儲存組選擇 信號及啟動儲存組選擇信號。閃鎖電路ηΐι維持 列位址啟動彳自號112,的啟動，無論列位址啟動信號 及列位址中斷信號31因中斷儲存組選擇信號Ui所產生 的任何改變。列解碼器1351亦維持字元線4〇ι的啟動， 無論列位址信號33因中斷儲存組選擇信號丨丨1所產生的 任何改變。同樣地，儲存組17i的資料可以讀出，無論 列位址信號的任何改變。 由於儲存組選擇信號ns及列位址中斷信號31係啟 動，儲存組1了2係中斷c 同時讀取儲存組m及中斷儲存組172的動作說明如 下。同樣地，在習知半導體記憶裝置中，某儲存組的資 _料讀取及中斷可與其他儲存組的資料讀取及中斷一起進 行。 锼濟部中央標準局貝工消费合作社印繁 - 不過，第二習知半導體記憶裝覃需要與儲存組相同數 目的時序控制電路。當儲存組的數目增加時，時庠控制 電路的數目亦會隨之增加。 第6圖係一般時序控制電路的例子。 第6圖的時序控制電路192是由延遲電路ΐ9ι广Μ。 及驅動器19〇广19〇3所構成。時序控制電路m接收輸 入^號194 ’並在不同時序輸出控制信號193广19 ______ 11 7紙張尺度適财關家料（CNS )鐵 3 經濟部中央標準局員工消f合作社印製 4879 : 五、發明説明（9) 一 各延遲電路191卜1913是由複數串連反相器所構成。 延遲電路191〗~1913亦彼此串連。延遲電路191ι的輸出 經由驅動器190,輸出作為控制信號193ι。延遲電路1912 的輸出經由驅動器19〇2輸出作為控制信號丨93】。延遲電 路1913的輸出經由驅動器19〇3輸出作為控制、信號π%。 控制信號193广1933對應於字元線驅動信號7ι、預充 電信號8,、感應放大器致能信號 由於驅動器190广19〇3供應延遲電路延遲 的h號至各電路以作為控制信號193广193 3，時序控制電 路192必須使用大反相器。因此，時序控制電路的佔用 面積通常大於其他電路的佔用面積。當儲存組的數目隨 半導體記憶裝置之記憶容量而增加至4、8、16、..，，時 序控制電路的電路面積亦會增加。 第二習知技術半導體記憶裝置需要與儲存組數目相同 的時序控制電路。因此’當儲存組的數目增加，時序控 制電路的電路面積亦會大幅增加。 為解決上述及其他目的，本發明的目的便是提供一種 半導體記憶裝置’其時序控制電路之電路面積不會隨著 ,儲存組的數目增加而增加。 為達上述目的，根據本發明的第一個特徵，半導體記 憶裝罝包括： 複數儲存組； 一時序控制電路，連接該些儲存組，並輪出一信號以 啟動各儲存組及一信號以在預定時序以預定順序預充電 本紙張尺度適用中國國家標準（CIVS ) Λ4况格（210X 297公兑） 經濟部中央標準局貞工消费合作社印製 48 7仔 Λ7 五、發明説明（一 各儲存組；以及 閂鎖電路，連接各儲存組，並閂鎖該時序控制電路之 輸出信號狀態β 根據第一個特徵，閂鎖該時序控制電路之輸出信號狀 態之閃鎖電路係排列於各儲存組，且一個時序控制可分 享於複數儲存組。 即使儲存組的數目增加，該時序控制電路的電路面積 亦不會隨之增加。 根據本發明的第二個特徵，在半導體記憶裝置中，各 閂鎖電路之輸出信號係一控制字元線啟動之字元線驅動 信號’ 一控制預充電之預充電信號，及一控制感應放大 器動作之感應放大器致能信號， 啟動各儲存組之該信號具有一字元線驅動信號之設定 信號以啟動該字元線驅動信號，一預充電重設信號以中 斷該預充電信號’及一感應放大器致能信號設定信號以 啟動該感應放大器致能信號，以及 預充電各儲存组之該信號具有一字元線信號重設信號 以中斷該字元線驅動信號’ 一預充電設定信號以啟動該 預充電信號’及一感應放大器致能信號重設信號以中斷 該感應放大器致能信號。 根據本發明的第三個特徵，半導體記憶裝置.包括： 複數儲存組’各具有複數記憶胞，其分別形成於複數 位元線對及複數字元線的交點，複數预充電電路，其連 接各位元線對並在一預充電信號啟動時預充電各位元線 13 本纸張尺度適用中國國家標率（CNS ) Λ4说推（210X297公郑)~~ (請先k讀背面之注意事項再填頁) .裝· *1Τ 線 434879 Λ Λ7 B7 經濟部中央標卒局貝工消f合作社印袈 五、發明説明（1 對，複數感應放大器，其連接各位元線對並在一感應放 大器致能k號啟動時放大各儲存組，及一列解碼器’其 連接一列閂鎖電路，藉以在各儲存組啟動時閂鎖一列位 址表示之字元線之選擇/未選擇狀態及在一字元線驅動信 號啟動時啟動該列閂鎖電路表示之字元線； 一時序控制電路，具有一啟動時序鏈以在一列位址啟 動仏號啟動時在預定時序以預定順序控制一字元線驅動 信號設定信號、一預充電信號重設信號、一感應放大器 致能信號設定信號，及在一列位址中斷信號啟動時在預 疋時序以預定順序控制一字元線驅動信號重設信號、一 預充電信號設定信號、一感應放大器致能信號重設信號； 一儲存组解碼器，啟動一儲存組選擇信號以選擇一包 括於一位址信號之儲存组位址表示之儲存組； 一列位址緩衝器’輸出一列位址以作為包括於該位址 信號之一列位址信號；以及 複數阿鎖電路，連接各儲存組，接收該儲存組選擇信 號，在一對應儲存組選擇信號及該位元線驅動信號設定 信號啟動時啟動該位元線驅動信號，在該位元線驅動信 號重設號啟動時中斷該位元線驅動信號，在該預充電 信號設定信號啟動時啟動該預充電信號，在該預充電信 號重設信號啟動時中斷該預充電信號，在該感應放大器 致能信號設定信號啟動時啟動該感應放大器致能信號， 及在該感應放大器致能信號重設信號啟動時中斷該感應 放大器致能信號。 諳 先 讀 背 之 注· 再 裝 訂 線 14 本紙張尺度適用中國國家標準（CNS )以故格（2i〇x 297公及） 434879 Λ7 經濟部中央標嗥局貝工消費合作社印製 五、發明説明（！2) 根據第二個特徵，根據儲存組選擇信號以閂鎖該時序 控制電路之輪出信號狀態之問鎖電路係排列於各儲存 組，且一個時序控制可分享於複數儲存組。 即使儲存組的數目增加，該時序控制電路的電路面積 亦不會隨之增加。 根據本發明的第四個特徵，在半導體記憶裝置中，各 閂鎖電路包括： 一第一邏輯電路，在該字元線驅動信號設定信號及該 儲存組選擇信號均啟動時啟動—輸出信號； 一第二邏輯電路，在該字元線驅動信號重設信號及該 儲存組選擇信號均啟動時啟動一輸出信號； ，一第三邏輯電路，在該預充電信號設定信號及該儲存 组選擇信號均啟動時啟動一輸出信號； 一第四邏輯電路，在該預充電信號重設信號及該儲存 組選擇信號均啟動時啟動一輸出信號； —第五邏輯電路，在該感應放大器致能信號設定信 及該儲存組選擇信號均啟動時啟動一輸出信號； 一第六邏輯電路，在該感應放大器致能信號重設信 及該儲存組選擇信號均啟動時啟動一輸出信號； —第一正反電路’由該第一邏輯電路之輸出信號設定 及該第二邏輯電路之輸出信號重設，並輪出一，輸出信號 以作為該字元線驅動信號； 一第二正反電路，由該第三邏輯電路之輪出信號設定 及該第四邏輯電路之輸出信號重設，並輪出—輸出信號 號 號 請 先 閱 讀 背 面434870 " Λ *? Η 印? Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the Invention (1) — The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device. The area is composed of plural storage groups. Generally, in a conventional semiconductor memory device (such as DRAM), a memory cell is formed at the intersection of a complex bit line pair and a complex bit line. The memory information of the target memory cell is read out by selecting word lines with row addresses and bit line pairs with row addresses. In a conventional semiconductor memory device (such as a dram), the memory area is divided into a plurality of blocks according to the increase of the memory capacity and the length limitation of the bit line pair. In order to read out the memory information stored in a memory cell in a semiconductor memory device composed of a plurality of blocks, a row address is first assigned, and then a row address and a block address are assigned. After the address is assigned, various actions (such as data writing and reading) are performed according to the reception of external commands. Fig. 1 (first conventional technique) is a block diagram of a semiconductor memory device composed of a plurality of blocks. In this conventional semiconductor memory device, the memory area is composed of two blocks 121 and 122. The semiconductor memory device includes blocks 121 to 122, an address buffer 91, and a time sequence control circuit 93. When the column address enable signal 30 is activated, the sequence control circuit 93 activates the address enable signal 100 'and performs a predetermined sequence at a predetermined timing. In sequence, she changed the word line drive signal 97, precharge signal 98, and sense amplifier enable signal 99 from high address (H) to low level (L) or from low level (L) to high level (H). This paper size is applicable to Chinese national standard (CNS Ｍ 心 见 柏 (2 丨 0Χ 297 公 #) 谙 Λ Read and read the note on the back and re-binding __R? V. Description of the invention (2) The column address start signal 30 is external Command start. When the column address enable signal 100 is activated, the address buffer 91 latches and outputs the column address contained in the address signal 32 as the column address signal, and changes the block selection signal 90! Or 902 The block designated by the block address of the start address signal 32. The block 121 is composed of bit line pairs 41 to 41, word line 'SAP, SAN, and plural memory cells 17 (arranged on the bit line, respectively). To the boundary of 41 to 4 η and the character line 40 to 40 m), the pre-charging circuit is arranged at the bit line pair 41 to 41 n), the pre-charging circuit 19 (between SAP and SAN), and the sense amplifier 29 to 29n ( Arranged in bit line pairs (41 to 41n), column decoder 115, AND circuit 101, OR circuit 102, inverter 103, AND circuit 104, inverter 42, p-channel MOS transistor 38, n-channel MOS The transistor 39 is formed. The AND circuit 101 performs an AND operation on the word line drive signal 97 and the block selection signal 90, and The result is used as the word line driving signal 7 '. When the word line driving signal 7 is changed to Η, the column decoder 1151 will be assigned by the word line 40, -4 (^ to activate the column address signal 33). As shown in Fig. 2, the column decoder 115 is composed of the address decoder 140 and 140 mm. The address decoders 140 ^ 14 (^ are respectively arranged on the character lines 40 to 40, and are located at the addresses. Decoder 140 ^ 14 (^, the address of the corresponding character line is set. When the character line drive signal 7 is changed to Η ', the address decoder is 140 to 140m wide. This paper standard applies to the Chinese National Standard (CMS) Μ Now (210X297々 &t; t) Please read. Η Note of $ 3 * Remarks-Reload, order printed by the Pager Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, printed 434879 Λ7 五 7 V. Description of the invention (3) It will act. If the address indicated by the column address signal 33 is the set address, each address decoder activates the corresponding word line. The inverter 103 inverts the logic state of the block selection signal 90, and outputs the inverted result. The OR circuit 102 performs an OR operation on the output signal of the inverter 103 and the precharge signal 98, and outputs the result. When the OR circuit When the output signal of 102 changes to η, the pre-charging circuits 181 ~ 18η will pre-charge the bit line pairs 411 ~ 4in, fix their potential, and maintain the same level. Similarly, when the output signal of 〇R circuit 1 〇2 When it is changed to “Time”, the pre-charging circuit 19 pre-charges SAP and SAN, fixes their potentials, and maintains the same level. The AND circuit 104 performs an AND operation on the inductive amplifier enable signal 99 and the block selection signal 90 !, and outputs the result as an inductive amplifier enable signal \. The inverter 42 inverts the logic state of the sense amplifier enable signal 9 !. An output signal of the inverter 42 is input to a gate of a p-channel MOS transistor 38. When the output signal of the inverter 42 is changed to 1, the p-channel MOS transistor 38 is turned on to apply the voltage vDD to SAP. The sense amplifier enable signal 1 is input to the gate of the n-channel] y [0S transistor 39]. When the sense amplifier enable signal 9 is changed to η, the n-channel MOS transistor will be turned on to apply the spot voltage to san. When the P-channel MOS transistor 38 and the n-channel MOS transistor are turned on at the same time, the inductive amplifier 29 to 29 will act to amplify the bit line. The Chinese National Standard Car (CNS) is applicable to this paper scale. ) Please read first, main: Italian matter-Printed by the Consumers 'Cooperative of the Standards Bureau of the Ministry of Economic Affairs ^ 434879 ^ Λ? ________ — ΙΠ 5. Invention Description (4) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economics The output voltage of 41n is output through the row selection circuit and the input / output circuit (both not shown). The arrangement of block 122 is the same as that of block 121, except that the input block selects L 遽 902 instead of the block. The ghost selection signal is 9], so its description will be omitted. The operation of the conventional semiconductor memory device will be explained in conjunction with the timing diagrams in Figure id and Figure 3. The following description is about the reading action, and the writing action is very similar. The operation of reading data from the memory cell 17 at the bit line pair 4lt & character line 4 (^ boundary) formed in block 121 will be described below. When the external command and address signal 32 are input at t41, the external command will Startup column The address start signal 30, and the timing control circuit 93 activates the address enable signal 100 °, the address buffer 91 latches, and the column address of the output address signal 32 is used as the column address signal 32. Figure 3 address signal The blank portion of 32 indicates the position where the column address is read. Since the block address indicates block 121, the address buffer 91 changes the block selection signals 901 to H. At t42, the timing control circuit 93 changes the precharge signal 98 to L to change the precharge signals 1 to L, and to interrupt the precharge circuits 18 to 18n and the precharge circuit 19. The timing control circuit 93 changes the word line drive signals 97 to Η, thereby changing the word line drive signals 7! To Η And activate the word line 40 !. At t43 ', the timing control circuit 93 changes the sense amplifier enable signal \ to H, thereby turning on the p-channel MOS transistor 38 and the n-channel MOS transistor 39' and activating the sense amplifier 29 to 29n. Therefore, the memory formed at the bit line pair 41t and the character line 4 (^ the boundary of the memory of this paper is applicable to the CNS) 'Tiege (210x297). Please read the note of 1¾-Note- Fill in% ri% 434879 Λ7 V. Description of the invention (5) The data stored in cell 17 is output and amplified via bit line pair 411, and the amplified result is output. After the data is read, block 121 # is interrupted. In particular, at t44, the timing control circuit 93 changes the word The element line driving signals 97 to L are used to change the character line driving signals 71 to L and interrupt the character line 40! At t45, the timing control circuit 93 changes the sense amplifier enable signals 99 to L to change the sense amplifier enable Signal to L and interrupt the sense amplifier 29 to 29n. At t46 ', the timing control circuit 93 changes the precharge signals 98 to Η, thereby changing the precharge signals 8m to η, and activates the precharge circuits 18 to 18, and 19. That is, the bit line pairs, SAP, and SAN are charged to A given voltage, and the voltage across the bit line is set to the same level p, but 'if the semiconducting device is remembered, the memory device is made up of plural blocks, and the signal is controlled by time-sequence. Circuit 93 controls, When a specific block is processed, other blocks cannot be processed. When the memory capacity and the number of blocks increase, it takes more time to read the memory content. In order to solve this problem, semiconductor memory devices do not consist of multiple blocks. It is composed of plural storage groups that can operate independently. Figure 4 (Second Known Technology) printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is a semiconductor memory device composed of multiple storage groups. The same as in Figure 1. Parts are indicated by the same reference numerals. In this type of semiconductor memory device, the memory area is composed of four storage groups 171 to 174. This conventional semiconductor memory device is composed of storage groups 171 to 174, and the timing control circuit 110 is wide. 11〇4 (Respectively arranged in storage groups 171 to 174), flash lock circuits 111 to 1114 (respectively arranged in timing control circuits llOfUOj, and the paper size of the paper are applicable to the Chinese National Standard (CMS) grid (210X297)} 434879 Λ7 Central Standard of the Ministry of Economic Affairs Printed by the Bureau Cooperative Consumer Cooperative Co., Ltd. 5. Description of the invention (—) —- Address buffer 45 and storage group decoder M3. Column address buffer 45 round out address signal 32 column address As the column address signal 33. The storage group decoder 143 activates the storage group selection signals Ui ~ U4 for a predetermined time by the storage group indicated by the storage group address of the startup address signal 32. The latch circuit 111 and Ilk only store the corresponding storage. The group selection signal 11 is read from the column address start signal 30 and the column address interruption signal 3 at the start of the column address. When the column address start signal 30 is started, the latch circuit m is wide and the column address start signal 112 is started. ^ If the column address interrupt signal 31 is activated, the latch circuit ill is wide and the column address start signal is interrupted 112. The timing control circuit 110 to 110 performs the same operation as the timing control circuit 93 in FIG. 1 except that it does not output Address enable signal 100 In addition, the timing control circuit 110 to 110 outputs the word line driving signal 7 to 7 instead of the word line driving number 97, the precharge signal 8 to 84 instead of the precharge signal 98, and the sense amplifier enable signal 9 丨 ~ 94 is a non-inductive amplifier enable signal 99, and receives a column address start signal 112! Instead of a column address start signal 30. The storage group 171 is composed of a bit line pair 41 〖~ 41n, a word line 40 to 40 m, SAP, SAN, plural cells 17 (formed on bit line pairs 41 to 41 n and character lines 40 to 4 4 (^ junction), pre-charging circuits ι8 to 18 η (arranged on bit line pairs 40 to 40 n, Charging circuit 19 (arranged between SAp and San), inductive amplifier 29 ^ 29 / arranged on bit line pair 40 to 40n respectively), column decoder 135 丨, inverter 42, p-channel MOS transistor 38, η The channel MOS transistor 39 is configured. When the word line drive signal 7! Is changed to Η, the column decoder 135, the basic paper size applies the Chinese National Standard CN (CNS) Λshirt see the grid (21〇 × 297 ^ # _ Please read the note before reading * Matters-Reload. Thread 434879 A7 n? V. Description of the invention (7) — ~ According to the storage group selection signal 11, latch column address signal 33, and from the character line 40! To 40 „in order As shown in Fig. 5, the column address signal 33 word line is assigned. The column decoder 135 is composed of the address decoder 140 to 140m and the latch circuit 141 [. The latch circuit 1411 is selected according to the storage group. Signal 丨! Latch and output column address signal 33. The address decoder 140-140m receives the column address signal 33 latched and output by the latch circuit 141. The second conventional semiconductor memory device will be described below. The operation of reading data from the memory cell 17 formed at the boundary of the bit line pair and the word line 40m in the storage group 171 will be described below. First, the column address start signal is activated, and the address signal is input from the outside. 32 (column address with table line 4 (^ address) and storage group address representing storage group pi Then, the column address buffer 45 outputs the column address of the address signal as the column address signal 33, and the storage group decoder 143 activates the storage group selection signal llt. Because the storage group selection signal 11 and the column address The start signal 30 is activated, and the latch circuit 111 activates the column address enable signal 112J. Printed by the Central Laboratories of the Ministry of Economic Affairs and the Consumer Cooperatives, due to the column address enable signal 112, the sequence control circuit 110 controls the word line drive signal ', Pre-charge signal 8 !, inductive amplifier enable signal 9, to perform the reading operation of memory cell 17 and interrupt after reading. At this time, because storage group selection signal 11! Is activated, column decoder 1351 latches The column address signal 33 and the word line 40i indicated by the latched column address signal 33. This paper standard applies the Chinese National Standard (CNS) to regulate looseness (21〇 × 25ΠΆ Office) 434B79 Λ7 _______ in V. Description of the Invention (8) 'When reading out the stored data of the memory cell 17 from the storage group 171, the operation of assigning the storage group 172 to interrupt will be described below. The storage group address included in the externally inputted address signal 32 is switched to assign Storage group 172. Storage group decoder 143 interrupts the storage group selection signal and starts the storage group selection signal. The flash lock circuit ηΐι maintains the start of the column address starting from number 112, regardless of the column address start signal and the column address interrupt signal 31. Any change caused by interruption of the bank selection signal Ui. The column decoder 1351 also maintains the activation of the word line 40m, regardless of any changes in the column address signal 33 caused by the interruption of the bank selection signal. Similarly, the data of the storage group 17i can be read out regardless of any change in the column address signal. Since the storage group selection signal ns and the column address interruption signal 31 are activated, the storage group 1 has 2 series interrupts c and simultaneously reads the storage group m and the interrupt storage group 172. The operation is described below. Similarly, in the conventional semiconductor memory device, data reading and interruption of a storage group can be performed together with data reading and interruption of other storage groups. The Central Standards Bureau of the Ministry of Economic Affairs, Peugeot Consumer Cooperative, India Fan-However, the second conventional semiconductor memory device requires the same number of sequential control circuits as the storage group. As the number of storage banks increases, the number of time control circuits also increases. Fig. 6 is an example of a general timing control circuit. The timing control circuit 192 shown in FIG. And the driver is composed of 190 and 193. The timing control circuit m receives the input number 194 'and outputs control signals at different timings 193 to 19 ______ 11 7 Paper size suitable for financial and household materials (CNS) Iron 3 Printed by the staff of the Central Standards Bureau of the Ministry of Economy 4879: Description of the Invention (9) A delay circuit 191 to 1913 is composed of a plurality of inverters connected in series. The delay circuits 191 to 1913 are also connected in series with each other. The output of the delay circuit 191m is output as a control signal 193m via the driver 190. The output of the delay circuit 1912 is output as a control signal via the driver 19202]. The output of the delay circuit 1913 is output as a control and signal π% via the driver 1903. The control signals 193 to 1933 correspond to the word line drive signal 7m, the precharge signal 8, and the inductive amplifier enable signal. As the driver 190 to 193 supplies the delay number h of the delay circuit to each circuit as the control signal 193 to 193 3 The timing control circuit 192 must use a large inverter. Therefore, the area occupied by the timing control circuit is usually larger than that occupied by other circuits. When the number of storage banks increases to 4, 8, 16, and .. with the memory capacity of the semiconductor memory device, the circuit area of the timing control circuit also increases. The second prior art semiconductor memory device requires the same number of timing control circuits as the number of storage banks. Therefore, as the number of storage banks increases, the circuit area of the timing control circuit also increases significantly. In order to solve the above and other objects, an object of the present invention is to provide a semiconductor memory device 'whose circuit area of the timing control circuit does not increase as the number of storage groups increases. In order to achieve the above object, according to a first feature of the present invention, a semiconductor memory device includes: a plurality of storage groups; a timing control circuit connected to the storage groups, and rotating a signal to activate each storage group and a signal to Pre-scheduled and pre-charged in a predetermined sequence. This paper size applies Chinese National Standards (CIVS). Λ4 condition (210X 297). Printed by Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. ; And a latch circuit that connects each storage group and latches the output signal state of the timing control circuit β According to the first feature, a flash lock circuit that latches the output signal state of the timing control circuit is arranged in each storage group, And a timing control can be shared in a plurality of storage groups. Even if the number of storage groups increases, the circuit area of the timing control circuit will not increase accordingly. According to the second feature of the present invention, in the semiconductor memory device, each latch The output signal of the circuit is a character line drive signal that controls the activation of the word line, a precharge signal that controls precharging, and a control In response to the amplifier's inductive amplifier enable signal, the signal that activates each storage bank has a word line drive signal setting signal to activate the word line drive signal, a precharge reset signal to interrupt the precharge signal 'and An inductive amplifier enable signal setting signal is used to activate the inductive amplifier enable signal, and the signal for pre-charging each storage group has a word line signal reset signal to interrupt the word line drive signal. Activating the pre-charging signal 'and an inductive amplifier enabling signal reset signal to interrupt the inductive amplifier enabling signal. According to a third feature of the present invention, a semiconductor memory device includes: a plurality of storage groups' each having a plurality of memory cells, It is formed at the intersection of the multiple bit line pair and the multiple digital line, respectively. The multiple pre-charging circuit is connected to each bit line and pre-charges each bit line when a pre-charge signal is activated. Rate (CNS) Λ4 said push (210X297 Gong Zheng) ~~ (please read the precautions on the back before filling in the page). * 1Τ line 434879 Λ Λ7 B7 Central Government Bureau of the Ministry of Economic Affairs, Bei Gong Xiao Cooperative Cooperative Association, Fifth, the description of the invention (1 pair, a plurality of inductive amplifiers, which are connected to each element pair and amplify each storage group when an inductive amplifier enables k, and A row of decoders is connected to a row of latch circuits to latch the selected / unselected state of a word line indicated by a row address when each storage bank is activated and to activate the row of latch circuits when a word line drive signal is activated A character line indicated; a timing control circuit having a startup timing chain to control a word line drive signal setting signal, a precharge signal reset signal, A sense amplifier enable signal setting signal, and a word line drive signal reset signal, a precharge signal setting signal, and a sense amplifier enable signal reset are controlled in a predetermined sequence in a predetermined sequence when an address interrupt signal is activated in a column. Set a signal; a storage group decoder, activate a storage group selection signal to select a storage group included in a storage group address indication included in a one-bit signal; Column address buffer 'outputs a column address as a column address signal included in the address signal; and a plurality of lock circuits connected to each storage group, receiving the storage group selection signal, a corresponding storage group selection signal and The bit line driving signal setting signal is activated when the bit line driving signal is activated, the bit line driving signal is interrupted when the bit line driving signal reset number is activated, and the pre-charging signal is activated when the pre-charging signal setting signal is activated. A charging signal, interrupting the precharge signal when the precharge signal reset signal is activated, activating the inductive amplifier enable signal when the inductive amplifier enable signal set signal is activated, and initiating when the inductive amplifier enable signal reset signal is activated The sense amplifier enable signal is interrupted from time to time.谙 Read Back Note · Rebinding Line 14 This paper size is in accordance with Chinese National Standard (CNS) with the old format (2i0x 297 and 434) 434879 Λ7 Printed by Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs (! 2) According to the second feature, the interlocking circuits for latching the state of the turn-out signal of the timing control circuit according to the storage group selection signal are arranged in each storage group, and one timing control can be shared in the plurality of storage groups. Even if the number of storage banks increases, the circuit area of the timing control circuit does not increase accordingly. According to a fourth feature of the present invention, in the semiconductor memory device, each of the latch circuits includes: a first logic circuit, a start-output signal when the word line drive signal setting signal and the storage group selection signal are both activated; A second logic circuit that activates an output signal when the word line drive signal reset signal and the storage group selection signal are both activated; and a third logic circuit that sets the precharge signal and the storage group selection signal An output signal is activated when both are started; a fourth logic circuit is activated when both the precharge signal reset signal and the storage group selection signal are activated; a fifth logic circuit is set when the sense amplifier enable signal is set An output signal is activated when the signal and the storage group selection signal are both activated; a sixth logic circuit, an output signal is activated when both the sense amplifier enable signal reset signal and the storage group selection signal are activated;-the first positive and negative The circuit is set by the output signal of the first logic circuit and the output signal of the second logic circuit is reset, and one is output in turn to output a signal. As the word line drive signal; a second positive and negative circuit, set by the output signal of the third logic circuit and reset the output signal of the fourth logic circuit, and output by rotation-please read the output signal number first back

I 頁 15 本紙張尺度適用中國國家標準（CNS ) /\4現格（210X29·?公兑） 3487@;f ΑΊ R7 經濟部中央標率局貝工消费合作社印製 五、發明説明（13) ^ ~ 以作為該預充電信號；以及 一第二正反電路，由該第五邏輯電路之輸出信號設定 及該第六邏輯電路之輸出信號重設，並輸出一輸出信號 以作為該感應放大器致能信號。 根據本發明的第五個特徵，在半導體記憶裝置中，該 裝置更包括一預充電儲存組解碼器，其啟動一預充電儲 存組選擇信號以選擇一包括於該位址信號之一預充電儲 存組位址表示之儲存組’且該問鎖電路只在該預充電儲 存組選擇信號啟動時’啟動該字元線驅動信號重設信號、 該預充電信號設定信號、該感應放大器致能信號重設信 號以作為進行預充電之信號。 根據第五個特徵，預充電儲存組解碼器的排列更允許 以預充電儲存組位址（而非儲存組位址）指派儲存组。 在給定儲存組之設定序列期間，可進行其他儲存组之 重設序列》 根據本發明的第六個特徵，在半導體記憶裝置中，各 閂鎖電路包括： 一第一邏輯電路，在該字元線驅動信號設定信號及該 預充電儲存組選擇信號均啟動時啟動一輸出信號； 一第二邏輯電路，在該字元線驅動信號重設信號及該 預充電儲存組選擇信號均啟動時啟動一輸出信號； 一第三邏輯電路，在該預充電信號設定信號及該預充 電儲存組選擇信號均啟動時啟動一輸出信號； 一第四邏輯電路，在該預充電信號重設信號及該預充 本紙張尺度適用中國國家標卑（CMS ) Λ4Αί格（210Χ 297公说） 請 先 閲. 讀 背 面 之 注* t 裝 -訂 線 434870 ^ Λ7 _ — ΙΠ 經濟部中央標隼局員工消资合作社印製 五、發明説明（14) 電儲存組選擇信號均啟動時啟動一輸出信號； 一第五邏輯電路，在該感應放大器致能信號設定信號 及該預充電儲存組選擇信號均啟動時啟動一輸出信號； .一第六邏輯電路’在該感應放大器致能信號重設信號 及該預充電儲存組選擇信號均啟動時啟動一輸出信號； 一第一正反電路，由該第一邏輯電路之輸出信號設定 及該第二邏輯電路之輸出信號重設’並輸出一輸出信號 以作為該字元線驅動信號； 一第二正反電路，由該第三邏輯電路之輸出信號設定 及該第四邏輯電路之輸出信號重設，並輸出一輸出信號 以作為該預充電信號；以及 一第二正反電路，由該第五邏輯電路之輸出信號設定 及該第六邏輯電路之輸出信號重設，並輸出一輸出信號 以作為該感應放大器致能信號。 根據本發明的第七個特徵，半導體記憶裝置包括： 複數儲存組，各具有複數記憶胞，其分別形成於複數 位元線對及複數字元線的交點，複數預充電電路，其連 接各位元線對並在一預充電信號啟動時預充電各位元線 對複數感應放大器’其連接各位元線對並在—感應放 大窃致能信號啟動時放大一電壓輸出至該位元線對，及 一列解碼器，其只在一儲存組選擇信號啟動時，閂鎖一 列位址信號以啟動該列位址信號表示之位元線； 一時序控制電路’具有一啟動時序鏈’藉以在—列位 址啟動彳S號啟動時’在預定時序以預定順序控制—感鹿I Page 15 This paper size is in accordance with Chinese National Standard (CNS) / \ 4 present grid (210X29 ·? Committee) 3487 @; f ΑΊ R7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (13) ^ ~ As the precharge signal; and a second forward and reverse circuit, the output signal of the fifth logic circuit is set and the output signal of the sixth logic circuit is reset, and an output signal is output as the induction amplifier. Can signal. According to a fifth feature of the present invention, in the semiconductor memory device, the device further includes a precharge storage group decoder, which activates a precharge storage group selection signal to select a precharge storage included in the address signal. The storage group indicated by the group address, and the interlock circuit only activates the word line drive signal reset signal, the precharge signal setting signal, and the sense amplifier enable signal reset when the precharge storage group selection signal is activated. Set the signal as the signal for pre-charging. According to the fifth feature, the arrangement of the pre-charged storage bank decoder allows the storage bank to be assigned with a pre-charged storage bank address instead of the storage bank address. During the set sequence of a given storage group, the reset sequence of other storage groups can be performed. According to the sixth feature of the present invention, in the semiconductor memory device, each latch circuit includes: a first logic circuit, in which An output signal is activated when the element line drive signal setting signal and the precharge storage group selection signal are both activated; a second logic circuit is activated when the word line drive signal reset signal and the precharge storage group selection signal are both activated An output signal; a third logic circuit that activates an output signal when both the precharge signal setting signal and the precharge storage group selection signal are activated; a fourth logic circuit that resets the precharge signal and the precharge signal The size of this paper is applicable to Chinese National Standards (CMS) Λ4Αί (210 × 297). Please read it first. Read the note on the back * t gutter-binding line 434870 ^ Λ7 _ — ΙΠ Staff Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Printed 5. Description of the invention (14) When the selection signals of the electric storage group are all activated, an output signal is activated; a fifth logic circuit is enabled when the induction amplifier is enabled. An output signal is activated when the setting signal and the pre-charge storage group selection signal are both activated; a sixth logic circuit 'activates an output signal when the sense amplifier enable signal reset signal and the pre-charge storage group selection signal are both activated A first forward and reverse circuit, the output signal of the first logic circuit is set and the output signal of the second logic circuit is reset, and an output signal is output as the word line drive signal; a second forward and reverse circuit Setting the output signal of the third logic circuit and resetting the output signal of the fourth logic circuit, and outputting an output signal as the precharge signal; and a second positive and negative circuit by the fifth logic circuit. The output signal is set and the output signal of the sixth logic circuit is reset, and an output signal is output as the enable signal of the sense amplifier. According to a seventh feature of the present invention, the semiconductor memory device includes: a plurality of storage groups, each having a plurality of memory cells, which are respectively formed at the intersections of the plurality of bit line pairs and the plurality of digital element lines, and a plurality of pre-charging circuits connected to each element The pair is pre-charged when a pre-charge signal is activated. Each element pair is a plurality of inductive amplifiers, which is connected to each element pair and amplifies a voltage output to the bit pair when the inductive amplifying enable signal is activated, and a column A decoder that latches a column of address signals to activate the bit line indicated by the column address signal only when a storage group selection signal is activated; a timing control circuit 'has an activation timing chain' whereby the column address Start 彳 When the S number is started, 'control in a predetermined sequence in a predetermined sequence-sense deer

-(請先聞讀背面之；出意事項弃填寫U 裝 、1Τ 綉 本纸張尺度適用中國國家掠隼（CNS ) Λ4規相（210X297公对） 铢肩48791? 五、發明説明（15) 致能信號以控制啟動該字元線驅動信號設定信號及該感 應放大器致能信號之時序，及一預充電時序鏈，藉以在 一列位址中斷信號啟動時，在預定時序以預定順序控制 一預充電信號設定信號及一感應放大器致能信號重設信 號； 一儲存組解碼器’啟動一儲存組選擇信號以選擇一包 括於一位址信號之儲存組位址表示之儲存組； 一預充電儲存組解碼器，啟動一預充電儲存組選擇信 號以選擇一包括於該位址信號之一預充電儲存組位址之 儲存組； 一列位址緩衝器’輸出一列位址以作為包括於該位址 "is號之該列位址信號；以及 % 經濟部中央標隼局員工消费合作社印製 複數問鎖電路’連接各儲存組，接收該儲存組選擇信 號’在一對應儲存组選擇信號及該位元線驅動信號設定 信號啟動時啟動該位元線驅動信號，在該預充電儲存組 選擇信號啟動時中斷該位元線驅動信號，在該預充電儲 存組選擇信號及該預充電信號設定信號啟動時啟動該預 充電彳§號，在該預充電儲存組選擇信號啟動時中斷該預 充電信號，在該儲存組選擇信號及該感應放大器致能信 號啟動時啟動該感應放大器致能信號，及在該預充電儲 存組選擇信號及該感應放大器致能信號重設信號啟動時 中斷該感應放大器致能信號。 根據第七個特徵’該預充電儲存組選擇信號係用以作 為一重設該字元線驅動信號之信號。該儲存組選擇信號-(Please read the back; please note that you should not fill in the U package, 1T embroidery paper. The size of the paper is applicable to the Chinese National Rapporteur (CNS) Λ4 gauge (210X297 male pairs) Baht shoulder 48791?) 5. Description of the invention (15) The enable signal controls the timing of activating the word line drive signal setting signal and the inductive amplifier enable signal, and a pre-charging timing chain, so that when a sequence of address interrupt signals is activated, a pre-control is controlled in a predetermined sequence in a predetermined sequence. A charging signal setting signal and an inductive amplifier enabling signal reset signal; a storage group decoder 'activates a storage group selection signal to select a storage group including a storage group address indication included in a single-bit signal; a precharge storage A bank decoder activates a precharge storage bank selection signal to select a storage bank including a precharge storage bank address of one of the address signals; a row of address buffers outputs a row of addresses for inclusion in the address " is the address signal of this column; and% printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs of the consumer co-operative circuit 'connect each storage group and receive the storage group selection letter No. 'a corresponding storage group selection signal and the bit line driving signal setting signal are activated when the bit line driving signal is activated, the bit line driving signal is interrupted when the pre-charge storage group selection signal is activated, and the pre-charging The pre-charge signal is activated when the storage group selection signal and the pre-charge signal setting signal are activated, the pre-charge signal is interrupted when the pre-charge storage group selection signal is activated, the storage group selection signal and the induction amplifier enable signal are activated The inductive amplifier enable signal is activated at startup, and the inductive amplifier enable signal is interrupted when the precharge storage group selection signal and the inductive amplifier enable signal reset signal are activated. According to the seventh feature, the precharge storage group The selection signal is used as a signal to reset the word line driving signal. The storage group selection signal

1S 本紙張尺i適用中國國.^7#專{ CNS ) Λ视格（210X297-^ ) ~ ~ ~ 434879 Λ7 厂____________ΒΊ ________ 五、發明説明（ 係用以作為一重設該預充電信號之信號及一設定該感應 放大器致能信號之信號。該感應放大器致能信號之啟動 時序是由該感應致能信號控制。 由該時序控制電路至各閂鎖電路的輸出信號數目減少 時’該時序控制電路及該閂鎖電路之内連接亦減少，且 時序控制電路的電路面積亦減少β 根據本發明的第八個特徵，在半導體記憶裝置中，各 問鎖電路包括： 一第一邏輯電路，在該字元線驅動信號設定信號及該 儲存组選擇信號均啟動時啟動一輸出信號； 一第二邏輯電路，在該預充電信號設定信號及該儲存 組選擇信號均啟動時啟動—輸出信號； 一第二邏輯電路’在該感應放大器致能信號重設信號 及該儲存組選擇信號均啟動時啟動一輸出信號； 一第一正反電路，由該第一邏輯電路之輸出信號設定 及該預充電儲存组選擇信號重設，並輸出一輸出信號以 作為該字元線驅動信號； 一第二正反電路，由該第二邏輯電路之輸出信號設定 經濟部中央標嗥局貝工消费合作社印聚 及該儲存組選擇信號重設，並輸出一輸出信號以作為該 預充電信號； ’Λ 一苐二正反電路，由該健存組選擇信號設定及該第二 邏輯電路之輸出信號重設·，以及 一電路，問鎖該第三正反電路之輸出信號，並在該感 應致能信號啟動時輸出該輸出信號以作為該感應放大器 本紙張尺度適用中國國家摞準（CNS ) 格（2】0Χ 297公处） 434879 Λ7 H? --------------— 五、發明説明（17) ~~ 致能信號。 由上述特徵可知，本發明具有下列效用。 (1) 由於複數儲存組分享一個時序控制電路，時序控 制電路的電路面積可免於增加’即使儲存組的數目增加。 (2) 由於複數儲存組分享一個時序控制電路，各儲存 組設定及重設序列的時序可以同步。 (3) 當各儲存组的時序略為調整時，可藉由增加小延 遲元件至閂鎖電路的輸出以自參考時序進行相當精確的 調整。 (4) 藉由在時序控制電路準備設定及重設時序鏈，各 儲存組可同時進行啟動及預充電動作，故晶片效能可以 提高。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式說明 第1圖（第一習知技術）係半導體記憶裝置之排列之方 塊圖； 經濟部中央標隼局貝工消贤合作社印製 第2圖係第1圖閂鎖電路96ι之排列之方塊圖； 第3圖係第1圖半導體記憶裝置之動作之時序圖； 第4圖（第二習知技術）係半導體記憶裝置之排列之方 塊^園， 第5圖係第4圖列解碼器135|之排列之方塊圖； 第6圖係習知時序控制電路之排列之電路圖； ^348 7 ；：： Λ7 五、發明説明（18) 第7圖係本發明第一實施例之半導體記憶裝置之排列 之方塊圖； 第8圖係第7圖閂鎖電路&之排列之方塊圖； 第9圖係第7圖列解碼器5,之排列之電路圖； 第1〇圖係第7圖半導體記憶裝置之動作之時序圖； 第11圖係第7圖半導體記憶裝置中儲存组丨之設定 序列及儲存组2之重設序列之時序圖； 第12圖係本發明第二實施例之半導體記憶裝置之排 列之方塊圖； 第13圖係第12圖閃鎖電路之排列之電路圖； 第14圖係第12圖列解碼器65ι之排列之電路圖； 第15圖係第12圓半導體記憶裝置中儲存組61之設 疋序列及儲存組62之重設序列之時序圖： 第16圖係第12圖半導體記憶裝置之動作之時序圖； 第17圖係本發明第三實施例之半導體記憶裝置之排 列之方塊圖； 第18圖係第17圖閂鎖電路96ι之排列之方塊圖；以 及 經濟部中央標隼局員工消費合作社印製 第19圖係第17圖半導體記憶裝置之動作之時序圖。 實施例 本發明的數個實施例將配合圖式說明如下。 第7圖係本發明第一實施例半導體記憶敦置之排列之 方塊圖。與第4圖相同的部分是以相同標號表示。 第一實施例的半導體記憶裝置是由儲存組i〜4、閂鎖 本紙張尺度適用中國國家標隼（CNS) Λ4ί兄将（210x297^位） 434879 ^ 五、發明説明（19) 電路6广64(分別排列於儲存組丨〜釣、儲存組解碼器43、 時序控制電路35所構成。 時序控制電路35是由啟動時序鏈37及預充電時序鏈 36所構成。 當列位址啟動信號30啟動時，啟動時序鏈37在預定 時序以預定順序地控制字元線驅動信號設定信號1 〇、預 充電信號重設信號14、感應放大器致能信號設定信號 15 〇 當列位址中斷信號31啟動時，預充電時序鏈36在預 定時序以預定順序地控制字元線驅動信號重設信號12、 預充電信號設定信號13、感應放大器致能信號重設信號 16 ° 當列位址啟動信號30或列位址中斷信號31啟動時， 時序控制電路35便會啟動位址致能信號34。 當列位址致能信號34啟動時，儲存組解碼器43係動 作’藉以啟動任何儲存组選擇信號11广114,並啟動包括 於位址信號32之儲存組位址表示的儲存組。 經濟部中央標芈局貝工消资合作社印裝 閂鎖電路6广64分別接收儲存組選擇信號〜ll4。當 對應的儲存组選擇信號11广114啟動時，閂鎖電路6广64 改變字元線驅動信號71至Η以使字元線驅動信號設定信 號10改變至Η ’改變字元線驅動信號7,至L以使字元 線驅動信號設定信號10改變至Η，字元線驅動信號重設 信號12改變至Η ’改變預充電信號8!至L以使預充電 信號重設信號14改變至Η，改變預充電信號8l至L以 22 本紙张尺度適用中國國家標準（CNS >Λ4規搞（2Ι0Χ 297·公ft ) 434879 Α7 Β7 五、發明説明（2〇) 使預充電信號設定信號13改變至Η，改變感應放大器致 能信號9!至Η以使感應放大器致能信號設定信號15改 變至Η，及改變感應放大器致能信號9,至L以使感應放 大器致能信號重設信號16改變至Η。 如第8圖所示，閂鎖電路6是由正反電路20〜22及AND 電路23~28所構成。 AND電路23對字元線驅動信號設定信號10及儲存 組選擇信號111進行AND運算，並輸出其結果。 AND電路24對字元線驅動信號重設信號12及儲存 組選擇信號1U進行AND運算，並輸出其結果。 AND電路25對預充電信號設定信號13及儲存組選 擇信號進行AND運算，並輸出其結果。 AND電路26對預充電信號重設信號14及儲存組選 擇信號11,進行AND運算，並輸出其結果。 AND電路27對感應放大器致能信號設定信號15及 儲存組選擇信號llt進行AND運算，並輸出其結果。 AND電路28對感應放大器致能信號重設信號16及 儲存組選擇信號1U進行AND運算，並輸出其結果。 正反電路20是由AND電路23的輸出信號設定及AND 電路24的輸出信號重設，並輸出一輸出信號以作為位元 線驅動信號7!。 . 正反電路21是由AND電路25的輸出信號設定及AND 電路26的輸出信號重設，並輸出一輸出信號以作為預充 電信號8,。 23 本紙张尺度適用中國國家糅準（CNS )以現枯（210Χ297公垃） 請 先 間 讀 背 1¾ 之 注" ί 經濟部中央栋準局貝工消费合作社印製 43 4 8 7 9 五、發明説明（21) 正反電路22是由AND電路27的輸出信號設定及and 電路28的輸出信號重設，並輸出一輸出信號以作為感應 放大器致能信號\。 正反電路20〜22是在輸入信號由l改變至Η時進行 設定及重設。 閂鎖電路〜64具有與61相同的排列。這些電路分別 接收儲存組選擇信號II2〜1“(均未圖示）而非儲存組選擇 信號11】，且分別輸出字元線驅動信號7广74而非字元線 驅動信號、預充電信號8ι〜％而非預充電信號8丨、感 應放大器致能信號\〜、而非感應放大器致能信號\。 在儲存组1〜4中，列解碼器5广\取代第4圖儲存組 171〜174之列解碼器135广1354。 如第9圖所示，列位址編碼器5ι是由位址解碼器 56广56m、η通道MOS電晶體54广54m、反相器52广5、、 NAND電路55、p通道MOS電晶體53所構成。 在位址解碼器56r56m中，對應字元線4〇i〜4〇m的位 址係設定。當列位址信號33表示的位址為設定位址時， 各位址解碼器輸出L輸出信號。 經濟部中央標準局員工消费合作社印黎 η通道MOS電晶體$4广54m接收儲存組選擇信號、 而汲極則接收位址解碼器56广56„的輸出信號。當儲存 組選擇信號Hi改變至Η時，η通道m〇S電晶體54广5 4 輸出位址解碼器的輸出信號至源極。 NAND電路55將字元線驅動信號重設信號12及儲存 組選擇信號11的AND值反相，並輸出其反相結果。 本紙張尺度適用中國國家標準（CNS ) Λ4現格（2Ι0χ：^7公处） — 434879 Λ7 五、發明説明（22) P通道MOS電晶體53的閘極接收NAND電路55的 輪出信號D當NAND電路55的輸出電路改變至L時，· 通道MOS電晶體53係導通以設定n通道则電晶P 54广54m的源極至電壓vDD。 反相器對51广51m& 52广52m分別構成閂鎖電路，益 閂鎖及輸出n通道M0S電晶體54广的源極電壓。’ AND電路50广50„^別對反相器對51广5、及52广52 構成之閂鎖電路所閂鎖之信號及字元線驅動信號乃進行m AND運算，並輸出AND值至字元線4〇ι〜4〇ro。 第一實施例的動作將配合第7〜9圖及第1〇圖之時序 說明如下。 自儲存組1中形成於位元線對41ι及字元線4〇ι交界 之s己憶胞17，讀取資料的設定序列將說明如下。， 在in ’當外部命令由外部輸入，且具有表示字元線4〇ι 位址之列位址位址信號32及表示儲存組i位址之儲存组 位址輸入時，列位址啟動信號3會啟動預定時間。 由於列位址啟動信號30係啟動，時序控制電路35啟 動位址致能信號34預定時間。在接收位址信號32時， 列位址緩衝器45輸出列位址信號33，而儲存組解碼器43 則啟動儲存組選擇信號Ui預定時間。 在tu，時序控制電路35的啟動時序鏈37 .啟動預充 電G號重没“號14預定時間。此時，由於儲存組選擇信 號11】係啟動’問鎖電路6〗的正反電路21係重設，且預 充電信號8,由Η改變至L。隨後，預充電電路18ι〜18n 25 本紙張尺度適用中國國家標率（CNS )八4说枋（2丨) 請 先 間 讀 背 之 注'1S This paper rule is applicable to China. ^ 7 # 专 {CNS) Λ Sight (210X297- ^) ~ ~ ~ 434879 Λ7 Factory ____________ ΒΊ ________ 5. Description of the invention (It is used as a signal to reset the precharge signal And a signal for setting the enable signal of the inductive amplifier. The start timing of the enable signal of the inductive amplifier is controlled by the inductive enable signal. When the number of output signals from the sequence control circuit to each latch circuit decreases, the sequence control The internal connection of the circuit and the latch circuit is also reduced, and the circuit area of the timing control circuit is also reduced. According to the eighth feature of the present invention, in the semiconductor memory device, each interlock circuit includes: a first logic circuit, in An output signal is activated when the word line drive signal setting signal and the storage group selection signal are both activated; a second logic circuit is activated when the precharge signal setting signal and the storage group selection signal are both activated-an output signal; The second logic circuit 'activates an output signal when both the reset signal of the sense amplifier enable signal and the storage group selection signal are activated; a first An inverting circuit is set by the output signal of the first logic circuit and the pre-charge storage group selection signal is reset, and an output signal is output as the word line driving signal; a second forward and inverting circuit is provided by the second logic The output signal of the circuit is set by the Central Standards Bureau of the Ministry of Economic Affairs, Peigong Consumer Cooperative, and the storage group selection signal is reset, and an output signal is used as the pre-charge signal; Saves the group selection signal setting and resets the output signal of the second logic circuit, and a circuit that interrogates the output signal of the third positive and negative circuit, and outputs the output signal as the inductive enable signal when it is activated The paper size of the sensor amplifier is applicable to the Chinese National Standards (CNS) standard (2) 0 × 297 public place 434879 Λ7 H? ---------------- V. Description of the invention (17) ~~ Enable signal. From the above characteristics, it can be known that the present invention has the following effects. (1) Since the plurality of storage groups share a timing control circuit, the circuit area of the timing control circuit can be prevented from increasing, even if the number of storage groups is increased. (2) Share a timing control circuit in the multiple storage groups, the timing of each storage group setting and reset sequence can be synchronized. (3) When the timing of each storage group is slightly adjusted, you can add a small delay element to the output of the latch circuit to The self-reference timing is adjusted quite accurately. (4) By preparing the setting and resetting the timing chain in the timing control circuit, each storage group can start and precharge at the same time, so the chip performance can be improved. And other purposes, features, and advantages can be more clearly understood. The following is a detailed description of a preferred embodiment, in conjunction with the accompanying drawings, as follows: Schematic illustration Figure 1 (first conventional technology) is a semiconductor Block diagram of the arrangement of the memory device; Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Bei Gong Xiaoxian Cooperative, Figure 2 is a block diagram of the arrangement of the latch circuit 96m in Figure 1, and Figure 3 is the operation of the semiconductor memory device in Figure 1. Timing chart; Figure 4 (second conventional technique) is a block diagram of the arrangement of semiconductor memory devices, Figure 5 is a block diagram of the arrangement of the fourth column decoder 135 | Circuit diagram of the arrangement of the timing control circuit; ^ 348 7;: Λ7 V. Description of the invention (18) Figure 7 is a block diagram of the arrangement of the semiconductor memory device according to the first embodiment of the present invention; Figure 8 is the latch of Figure 7 Block diagram of the arrangement of the lock circuit & FIG. 9 is a circuit diagram of the arrangement of the decoder 5 in FIG. 7; FIG. 10 is a timing chart of the operation of the semiconductor memory device in FIG. 7; FIG. 12 is a timing diagram of a setting sequence of a storage group in the semiconductor memory device and a reset sequence of the storage group 2. FIG. 12 is a block diagram of an arrangement of the semiconductor memory device according to the second embodiment of the present invention; FIG. 13 is a view of FIG. 12 Circuit diagram of the arrangement of the flash lock circuit; Figure 14 is the circuit diagram of the array of the decoder 65m in Figure 12; Figure 15 is the setup sequence of the storage group 61 and the reset sequence of the storage group 62 in the twelfth round semiconductor memory device Timing chart: Fig. 16 is a timing chart of the operation of the semiconductor memory device of Fig. 12; Fig. 17 is a block diagram of the arrangement of the semiconductor memory device of the third embodiment of the present invention; Fig. 18 is a latch circuit of Fig. 17 96ι arranged block diagram; Central Bureau of Ministry of Economic Affairs marked Falcon 19 employees consumer cooperatives printed diagram line chart showing the operation of the semiconductor memory device of Fig. 17. Examples Several examples of the present invention will be described below with reference to the drawings. Fig. 7 is a block diagram showing the arrangement of semiconductor memory placement in the first embodiment of the present invention. The same parts as those in FIG. 4 are denoted by the same reference numerals. The semiconductor memory device of the first embodiment is composed of a storage group i ~ 4, and the paper size of the latch is applicable to the Chinese National Standard (CNS) Λ4ί Brother General (210x297 ^ bit) 434879 ^ V. Description of the Invention (19) Circuit 6-64 (Arranged separately in the storage group, the fishing group, the storage group decoder 43, and the timing control circuit 35. The timing control circuit 35 is composed of a start timing chain 37 and a precharge timing chain 36. When the column address start signal 30 is activated At time, the start timing chain 37 controls the word line drive signal setting signal 1 〇, the precharge signal reset signal 14 and the sense amplifier enable signal setting signal 15 at a predetermined timing in a predetermined sequence 〇 When the column address interrupt signal 31 is activated The pre-charging timing chain 36 controls the word line driving signal reset signal 12, the pre-charging signal setting signal 13, the sense amplifier enable signal reset signal 16 at a predetermined timing in a predetermined sequence. When the column address start signal 30 or column When the address interrupt signal 31 is activated, the timing control circuit 35 will activate the address enable signal 34. When the column address enable signal 34 is activated, the storage group decoder 43 will act 'to start Any storage group selects signals 11 to 114, and activates the storage group indicated by the storage group address included in the address signal 32. The Central Standards Bureau of the Ministry of Economic Affairs, Beigong Consumer Cooperative Co., Ltd. prints latch circuits 6 to 64 to receive the storage groups respectively. Selection signal ~ ll4. When the corresponding storage group selection signal 11 to 114 is activated, the latch circuit 6 to 64 changes the word line drive signal 71 to Η to change the word line drive signal setting signal 10 to Η 'change character Line drive signals 7, to L to change the word line drive signal setting signal 10 to Η, word line drive signal reset signal 12 to Η 'Change precharge signal 8! To L to make precharge signal reset signal 14 Change to Η, change the precharge signal 8l to L to 22 This paper size applies the Chinese National Standard (CNS > Λ4 Regulations (2Ι0χ 297 · mm ft) 434879 Α7 Β7 V. Description of the invention (2) Make the precharge signal The setting signal 13 is changed to Η, the inductive amplifier enable signal 9! Is changed to Η so that the inductive amplifier enable signal setting signal 15 is changed to Η, and the inductive amplifier enable signal 9 is changed to L to make the inductive amplifier enable signal repeat. Set signal 16 Change to 第. As shown in FIG. 8, the latch circuit 6 is composed of the forward and reverse circuits 20 to 22 and the AND circuits 23 to 28. The AND circuit 23 sets the word line drive signal setting signal 10 and the storage group selection signal 111 An AND operation is performed and the result is output. The AND circuit 24 performs an AND operation on the word line drive signal reset signal 12 and the storage group selection signal 1U and outputs the result. The AND circuit 25 sets the precharge signal setting signal 13 and the storage group. The selection signal performs an AND operation and outputs the result. The AND circuit 26 performs an AND operation on the precharge signal reset signal 14 and the storage bank selection signal 11 and outputs the result. The AND circuit 27 performs an AND operation on the sense amplifier enable signal setting signal 15 and the storage bank selection signal 11t, and outputs the result. The AND circuit 28 performs an AND operation on the sense amplifier enable signal reset signal 16 and the storage bank selection signal 1U, and outputs the result. The forward and reverse circuit 20 is set by the output signal of the AND circuit 23 and reset by the output signal of the AND circuit 24, and outputs an output signal as a bit line drive signal 7 !. The positive and negative circuit 21 is set by the output signal of the AND circuit 25 and reset by the output signal of the AND circuit 26, and outputs an output signal as a precharge signal 8 ,. 23 This paper size applies to the Chinese National Standards Standard (CNS) and is now dry (210 × 297 liters) Please read the note of 1¾ " ί Printed by the Shell Construction Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs 43 4 8 7 9 V. Description of the invention (21) The forward and reverse circuit 22 is set by the output signal of the AND circuit 27 and reset by the output signal of the and circuit 28, and outputs an output signal as an inductive amplifier enable signal. The positive and negative circuits 20 to 22 are set and reset when the input signal is changed from l to Η. The latch circuits ~ 64 have the same arrangement as 61. These circuits respectively receive the storage group selection signal II2 ~ 1 "(both not shown) instead of the storage group selection signal 11], and output the word line driving signals 7 to 74 instead of the word line driving signals and the precharge signal 8m. ~% Instead of pre-charge signal 8 丨, inductive amplifier enable signal \ ~, but not inductive amplifier enable signal. In storage group 1 ~ 4, column decoder 5 is used instead of storage group 171 ~ 174 in Fig. 4 The column decoder 135 to 1354. As shown in Figure 9, the column address encoder 5m is composed of an address decoder 56 to 56m, an n-channel MOS transistor 54 to 54m, an inverter 52 to 5, and a NAND circuit. 55, composed of p-channel MOS transistor 53. In the address decoder 56r56m, the address corresponding to the word line 40i ~ 40m is set. When the address indicated by the column address signal 33 is the set address At the same time, each address decoder outputs an L output signal. The Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the Consumer Electronics Co., Ltd., India ’s channel MOS transistor $ 4 to 54m receives the storage group selection signal, and the drain receives the address decoder ’s 56 to 56 outputs. signal. When the storage group selection signal Hi changes to Η, the n-channel MOS transistor 54-54 outputs the output signal of the address decoder to the source. The NAND circuit 55 inverts the AND values of the word line drive signal reset signal 12 and the bank select signal 11 and outputs the inverted results. This paper size applies the Chinese National Standard (CNS) Λ4 is present (2Ι0χ: ^ 7 common place) — 434879 Λ7 V. Description of the invention (22) The gate of the P-channel MOS transistor 53 receives the wheel-out signal D of the NAND circuit 55. When the output circuit of the NAND circuit 55 is changed to L, the channel MOS transistor 53 is turned on to set the source of the transistor P 54 to 54 m to the voltage vDD. The pair of inverters 51 to 51m & 52 to 52m respectively constitute a latch circuit, and the latch and the output source voltage of the n-channel M0S transistor 54 are widely used. 'AND circuit 50 to 50 „^ Do not pair the inverters 51 to 5 and 52 to 52 and the signal latched by the latch circuit and the word line drive signal are m ANDed and output the AND value to the word The element line 4〇ι ～ ４〇ro. The operation of the first embodiment will be described in conjunction with the timing diagrams of FIGS. 7-9 and 10. The bit line pair 41ι and the character line 4 formed in the storage group 1 are as follows. The memory of the junction 17 has a set sequence of reading data as follows. At in ', when an external command is input from the outside, and it has a column address address signal 32 which represents the word line 40 address. When the storage group address input of the storage group i address is input, the column address enable signal 3 is activated for a predetermined time. Since the column address enable signal 30 is activated, the timing control circuit 35 activates the address enable signal 34 for a predetermined time. When receiving the address signal 32, the column address buffer 45 outputs the column address signal 33, and the storage group decoder 43 starts the storage group selection signal Ui for a predetermined time. At tu, the start timing chain 37 of the timing control circuit 35. Start pre-charging G No. "No. 14 scheduled time. At this time, since the storage bank selection signal 11] is activated and the interlock circuit 21 of the question lock circuit 6 is reset, and the precharge signal 8 is changed from Η to L. Subsequently, the pre-charging circuit 18ι ~ 18n 25 This paper standard is applicable to China National Standards (CNS) 8: 4 枋 (2 丨) Please read the note below

(S 經濟部中央標车局員工消费合作社印製 434b / έ? Λ7 五、發明説明（23) 及19停止預充電。 在t13，啟動時序鏈37啟動字元線驅動信號設定信號 1〇預定時間。此時，由於儲存組選擇信號11係啟動， 閂鎖電路的正反電路係重設，且字元線驅動信號7,由 L改變至Η。在列解碼器中，由於列位址信號33表示 字元線4(^的位址，位址解碼器56!輸出啟動的L輸出 信號。由於儲存組選擇信號11,為Η，η通道MOS電晶 體54!係導通’且位址解碼器56,的L輸出信號係輸出 至反相器51,。因此’ Η信號輸入AND電路50!。由於 字元線驅動信號7〖為H，字元線4(^係啟動。由於字元 線驅動信號重設信號12為L，NAND電路55輸出Η輸 出信號’且ρ通道MOS電晶體53維持關閉。 在t14 ’啟動時序鏈37啟動感應放大器致能信號設定 信號15預定時間。由於儲存組信號Ui係啟動，正反電 路22係設定，且感應放大器致能信號9ι改變至η。隨 後’將輸出至位元線對41!的記憶胞17内容放大及輸出。 在tis ’儲存組信號11改變至L以完成設定序列。 在完成記憶胞之資料讀取後，中斷儲存組1的重設序 列將說明如下。 在、5，列位址中斷信號31由上述狀態啟動預定時間。 利用與讀取動作相同的動作，位址致能信號34係啟動預 定時間，且儲存組選擇信號Ui亦啟動預定時間。時序 控制電路35的預充電時序鏈36啟動字元線驅動信.號重 叹k號12預定時間。隨後，閂鎖電路6 ^的正反電路2〇 26 銪 閱- 讀 背 之 注(S printed by the Consumer Cooperatives of the Central Standard Vehicle Bureau of the Ministry of Economic Affairs 434b / Λ7 V. The invention description (23) and 19 stop pre-charging. At t13, the start timing chain 37 starts the character line drive signal setting signal 10 for a predetermined time. At this time, because the bank select signal 11 is activated, the positive and negative circuits of the latch circuit are reset, and the word line drive signal 7 is changed from L to Η. In the column decoder, due to the column address signal 33 Represents the address of word line 4 (^, address decoder 56! Outputs the activated L output signal. Since the storage group selection signal 11, is Η, n-channel MOS transistor 54! Is on and address decoder 56 The L output signal is output to the inverter 51. Therefore, the 'Η signal is input to the AND circuit 50 !. Since the word line drive signal 7 is H, the word line 4 (^ is activated. Because the word line drive signal The reset signal 12 is L, the NAND circuit 55 outputs a “output signal” and the p-channel MOS transistor 53 remains turned off. At t14, the startup timing chain 37 starts the sense amplifier enable signal setting signal 15 for a predetermined time. Because the storage group signal Ui is Start, the positive and negative circuit 22 is set, and the induction amplification The enable signal 9m is changed to η. Subsequently, the content of the memory cell 17 output to the bit line pair 41! Is amplified and output. In the tis' storage group signal 11 is changed to L to complete the setting sequence. After the data reading of the memory cell is completed, After the removal, the reset sequence of the interrupt storage group 1 will be described as follows. At 5, 5, the column address interrupt signal 31 is activated for the predetermined time from the above state. Using the same action as the read action, the address enable signal 34 is activated to be scheduled. Time, and the storage group selection signal Ui is also activated for a predetermined time. The pre-charging timing chain 36 of the timing control circuit 35 activates the word line driving signal. The number re-sighs the k number 12 for a predetermined time. Subsequently, the latch circuit 6 ^ positive and negative circuits 2〇26 Reading-Reading Notes

I 經濟部中央標準局員工消费合作社印製 本紙張尺度朗巾咖家料（CNS) ( --~~— ___ 扪_______________ 五、發明説明（24 ) ~ 係重設’字元線驅動信號7,改變至L，且字元線4〇1係 中斷。 (請先吣讀背面之·注意事^-再填办 在預充電時序鏈36啟動感應放大器致能信號重 設信號〗6預定時間。因此，閂鎖電路6ι的正反電路22 係重設’感應放大器致能信號9,改變至L，且感應放大 器29广29„係關閉。 在tu ’預充電時序鏈36啟動預充電信號設定信號13 預疋時間。問鎖電路h的正反電路21係設定，預充電 信號81改變至H，且預充電電路“广丨夂及19開始預充: 電在tl9’儲存組選擇信號11〗改變至L以完成重設序 列。 訂 在第一實施例的半導體記憶裝置中，時序控制電路35 輸出的命令信號是由問鎖電路心〜从分別排列於儲存組 1〜個鎖。如第u圖所示，舉例來說當儲存組丄進行 設定動作時，儲存組2的重設序列亦可以進行，即使在 练 儲存組1的讀，寫動作完成前，與第4圖之習知半導體記 憶裝置相同。 經濟部中央標率局員工消贽合作社印製 如上所述，在第-實施例中，—個時序控制電路％ 、 I以控制獨立地控制儲存组卜4的動作。即使儲存組的 數目增加’-個時序控制電路（具有大電路面積^乃可藉 由排綱電路(對應於加入的儲存組)而逹成因此； 時序控制電路的電路面積不备陆神六，& 槓不曰隨儲存組數目的增加而增 加。 第二實施例：I Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, Paper Size Longskin Coffee Materials (CNS) (-~~ — ___ 扪 _______________ V. Description of the Invention (24) ~ Reset the character line drive signal 7 , Change to L, and the character line 401 is interrupted. (Please read the note on the back side ^-and then fill in the pre-charge timing chain 36 to activate the sensor amplifier enable signal reset signal [6] for a predetermined time. Therefore, the positive and negative circuit 22 of the latch circuit 6m resets the 'induction amplifier enable signal 9, changes to L, and the inductive amplifier 29, 29, 29' are turned off. The precharge timing setting signal 36 is activated at tu 'precharge timing chain 36. 13 Pre-lock time. The positive and negative circuit 21 of the lock circuit h is set. The pre-charge signal 81 is changed to H, and the pre-charge circuit "Guangzhou and 19 starts pre-charging: the electricity is changed at t9 'storage group selection signal 11". To L to complete the reset sequence. Ordered in the semiconductor memory device of the first embodiment, the command signal output by the timing control circuit 35 is from the lock circuit core ~ arranged from the storage group 1 ~ locks respectively. As shown in Figure u Shown, for example, when the storage group is set In operation, the reset sequence of storage group 2 can also be performed, even before the reading and writing operations of storage group 1 are completed, it is the same as the conventional semiconductor memory device in Fig. 4. The Ministry of Economic Affairs, Central Standards Bureau, Staff Consumption Cooperative As described above, in the first embodiment, a timing control circuit%, I is used to control the operation of the storage bank 4 independently. Even if the number of storage banks is increased, a timing control circuit (having a large circuit area) ^ This can be achieved by arranging the outline circuits (corresponding to the added storage group); the circuit area of the timing control circuit is not prepared for Lushen VI, and the number will increase with the increase of the number of storage groups. Second implementation example:

43487P 經满部中央標隼局員工消费合作社印製 Λ7 ]〇 五、發明説明（25〉 — 本發明第二實施例之半導體記憶裝置將說明如下。 第12圖係第二實施例半導體記憶裂置之排列之方塊 圖。與第7圖相同的部分是使用相同的標號。 第二實施例半導體記憶裝置與第7圖第一實施例半導 體記憶裝置的差別在於，閂鎖電路^〜心由66广664取代、 儲存組1〜4由儲存組61〜64取代、預充電儲存組解碼器 44則新加入。也就是，啟動儲存組及預充電儲存組可獨 立動作。 預充電儲存組解碼器44改變預充電儲存組選擇信號 47广47J其對應於位址信號32之預充電儲存組位址所表 示的儲存組及指派儲存组），至H，藉以進行預充電。 與閂鎖電路6广64相較，閂鎖電路66ι〜μ#分別接收 預充電儲存組選擇信號47广474。若預充電儲存組選擇信 號47广474在儲存組選擇信號Ui〜il4保持L時為H，則 田字元線驅動信號重設信號〗2、預充電信號設定信號 13、感應放大器致能信號重設信號16改變至Η，且正反 電路20〜22係重設。 如第13圖所示，閂鎖電路66广664分別接收預充電儲 存組選擇信號47〖’而非第8圖中輸入閂鎖電路6,〜64之 AND電路24、25、μ的儲存組選擇信號…。 在儲存組01〜64中’列解碼器65广654分別取代儲存 組1〜4的列解碼器5广54。 如第Η圖所示’在列解碼器65广654中，相較於列解 碼器5广54 ’ NAND電路55輸出字元線驅動信號重設信 '(請先間讀背面之注意事項再填) -裝- 訂 線 本紙張尺度適用中國國家標準 (CNS ) Λ视柏（210x297公处） 4348?y W A7 ______ H7 經濟部中央摞準局員工消费合作社印製 五、發明説明（26) 號12及預充電儲存組選擇信號471的NAND值。 第二實施例的動作將配合第12〜16圖說明如下。 如第15圖所示，儲存組62重設序列在儲存組61設 定序列期間開始的例子將說明如下。 在’列位址啟動信號3 〇係啟動，且時序控制電路 35啟動位址致能信號34。隨後，儲存組解碼器43改變 儲存組選擇信號11】至Η，且列位址緩衝器45輸出包括 於位址信號32之列位址以作為列位址信號％。第16圖 時序之位址信號32之部□表示讀取作為列位址信號33之 列位址。時序控制電路35之啟動時序鏈37以預定時序 改變預充電信號重設信號14(在t^)、字元線驅動信號設 疋k號10(在I；23)、感應放大器致能信號設定信號（t^)， 至Η，達預定時間。這個動作可由第16圖時序之啟動序 列57表示《«在ία，儲存組選擇信號丨卜改變至[以完成 設定序列。 在儲存組61中，在〖Μ ’由於預充電信號重設信號14 及儲存組選擇信號Ul以上述動作改變至H，閂鎖電路6心 的正反電路21係重設以改變預充電信號8丨至L。在， 由於字元線驅動信號設定信號10改變至H ’字元線驅動 信號7〗改變至Η，且字元線40,由列解碼器65ι啟動。 在’由於感應放大器致能信號設定信號1 $改^變至η， 感應放大器致能信號9l改變至Η。在tS8，選擇信號Ui 改變至Η以完成儲存組61的啟動序列。這個動作可由 第16圖時序之儲存組61之内部信號59表示。 (請先閱讀背面之·注意事見存填^^ 裝· 訂 -線_ 本紙张尺度適用中國國家標準（CNS ) W規枋（2i〇X297.:.># ) A? 434879 五、發明説明（27) ' 在儲存組61的啟動序列期間，位址信號32之儲存組 位址改變以指派儲存組62，並啟動列位址中斷信號31。 第16圖位址信號32的部□表示改變的儲存組位址及列位 址β隨後，預充電儲存組解碼器44改變預充電儲存組選 擇h號47a至Η。時序控制電路35的預充電時序鏈％ 以預定時序改變字元線驅動信號重設信號12(在t2j、感 應放大器致能信號重設信號16(在t27)、預充電信號設定 信號13(在I；29)，至Η，達預定時間。這個動作可由第16 圖時序之重設序列58表示。 由於子元線驅動信號重設信號12及預充電儲存組選 擇信號472均以上述動作改變至η ,閂鎖電路的正反 電路20係重設以改變字元線驅動信號乙至L。因此， 排列於儲存組62的列解碼器652(未示）中斷儲存組62的 字元線4(^。由於感應放大器致能信號重設信號16及預 充電儲存组選擇信號472改變至H，閂鎖電路662的正反 電路22係重設以改變感應放大器致能信號92至j^由 於預充電信號設定信號13改變至Η，閂鎖電路662的正 反電路21係設定以改變預充電信號I至η，藉以完成 儲存組62的重設序列。這個動作可由第16圖時序之儲 存組62之内部信號60表示。 在第二實施例中，排列預充電儲存組解碼器44可使 彼此平行的儲存組同時進行設定序列及重設序列。也就 是’由於給定儲存組的資料可在其他儲存組之重設序列 時被讀出’處理速度可以增加。這些序列並不會同時開 本紙張尺度適用中國國家標準（CNS) Λ心見格（2!0><297公^ (請先閱讀背面之注意事項再填) -裝· 線 經濟部中央標準局負工消费合作社印^ Λ7 五、發明説明（28) 始，因為位址信號32同時指派一儲存組進行設定序列， 及一儲存組進行重設序列。不過，若指派欲預充電之儲 存組位址之預充電信號亦與位址信號32同樣地設定，以 利用不同命令獨立控制列位址啟動信號30及列位址中斷 信號31，則設定序列及重設序列便可以完全獨立地動 作。換句話說，設定序列及重設序列便可以同時進行。 對應位址致能信號34(與列位址中斷信號31同步）的 信號可輸出至預充電儲存組解碼器44以遮罩解碼的輸 出。 第三實施例： 本發明第三實施例的半導體記憶裝置說明如下。 第17圓係第三實施例半導體記憶裝置之排列之方塊 圖。與第12圖相同的部分是以相同標號表示β 第三實施例半導體記憶裝置與第12圖第二實施例半 導體記憶裝置的差別在於，閂鎖電路66广664由96(〜964 取代、時序控制電路135取代時序控制電路35。 經濟部中央標率局負工消贽合作社印製 在時序控控制電路135中，啟動時序鏈137取代時序 控制電路35之啟動時序鏈37、預充電時序鏈136取代 預充電時序鏈36。 啟動時序鏈137的動作與啟動時序鏈37相同，除了 啟動時序鏈137不會輸出任何預充電信號重設信號14及 感應放大器致能信號15，而是輸出感應致能信號97以 控制感應放大器致能信號9 i的輸出時序。 在第三實施例中，位址致能信號34只有在列位址啟 表紙乐尺度適用中國國家標本Γ^Τ^ίΓ( 31 434879 A 7 五、發明説明（29) 動仏號30啟動時啟動，而不會在列位址中斷信號31敌 動時輸出。儲存組選擇信號ηι〜114與位址致能信號34 同步輸出。不過，在重設序列中，這些信號並不需要與 位址致能信號34同步，因為在感應放大器致能信號重設 仏號13及預充電信號設定信號I]啟動前、位址中斷信 號31啟動後存在一間隔。因此，在第三實施例中，位址 致能信號34只在啟動序列輪出。 預充電時序鏈136的動作與預充電時序鏈36相同， 除了預充電時序鏈136不輸出任何字元線驅動信號重設 信號12。 如第18圖所示’在閂鎖電路96广964中，相較於第二 實施例之問鎖電路66广664 ’感應致能信號97係輸入， 且AND電路24、26、27係省略。當儲存組選擇信號11( 改變至Η時’正反電路21係重設且正反電路22係設定。 當預充電儲存組選擇信號47!改變至Η時，正反電路20 係重設。閂鎖電路96广964分別增加反相器71、72、75、 76 ’ ρ通道MOS電晶體73，η通道MOS電晶體74。 經濟部中央標準局員工消费合作社印製 (请先成讀背面之注項-S填1頁) 反相器71將正反電路22的輸出信號反相，並輸出其 反相結果。 η通道MOS電晶體74的閘極接收感應致能信號97， 汲極則連接反相器71的輸出。當感應致能信號97改變 至Η時，η通道MOS電晶體74係導通以輸出反相器71 之輸出信號至源極。反相器72將反相器71的反相結果 反相’並輸出其反相結果至ρ通道MOS電晶體73的閘43487P Printed by the Consumers' Cooperative of the Central Bureau of Standards of the People's Republic of China Λ7] 05. Description of the Invention (25) — The semiconductor memory device according to the second embodiment of the present invention will be described below. Block diagram of the arrangement. The same parts as in FIG. 7 are assigned the same reference numerals. The difference between the semiconductor memory device of the second embodiment and the semiconductor memory device of the first embodiment of FIG. 7 is that the latch circuit 664 replaced, storage group 1 ~ 4 replaced by storage group 61 ~ 64, pre-charged storage group decoder 44 was newly added. That is, starting storage group and pre-charged storage group can operate independently. Pre-charged storage group decoder 44 changed The pre-charged storage group selection signals 47 to 47J correspond to the storage group indicated by the pre-charged storage group address of the address signal 32 and the assigned storage group) to H to perform pre-charging. Compared with the latch circuits 6 to 64, the latch circuits 66 to 64 # respectively receive the precharge storage group selection signals 47 to 474. If the precharge storage group selection signals 47 to 474 are H when the storage group selection signals Ui ~ il4 remain L, then the field character line drive signal reset signal〗 2, the precharge signal setting signal 13, the sensor amplifier enable signal is reset It is assumed that the signal 16 is changed to Η, and the forward and reverse circuits 20 to 22 are reset. As shown in FIG. 13, the latch circuits 66 to 664 respectively receive the precharge storage bank selection signal 47 ″ ′ instead of the input of the latch circuits 6 to 64 in FIG. 8 and the storage circuits 24, 25, and μ of the bank selection. signal…. In the storage groups 01 to 64, the column decoders 65 to 654 respectively replace the column decoders 5 to 54 of the storage groups 1 to 4. As shown in the second figure, 'in the column decoder 65 to 654, compared to the column decoder 5 to 54', the NAND circuit 55 outputs the word line drive signal reset letter '(please read the precautions on the back before filling in )-Binding-Threading This paper size is in accordance with Chinese National Standards (CNS) ΛShibo (210x297) 4348? Y W A7 ______ H7 Printed by the Consumers' Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs V. Invention Description (26) 12 and the NAND value of the precharge storage bank selection signal 471. The operation of the second embodiment will be described below with reference to FIGS. 12 to 16. As shown in Fig. 15, an example in which the reset sequence of the storage group 62 is started during the setting sequence of the storage group 61 will be described below. The 'column address start signal 30' is activated, and the timing control circuit 35 activates the address enable signal 34. Subsequently, the storage bank decoder 43 changes the storage bank selection signals 11] to Η, and the column address buffer 45 outputs the column address included in the address signal 32 as the column address signal%. Fig. 16 The part □ of the sequential address signal 32 indicates that the column address which is the column address signal 33 is read. The start-up timing chain 37 of the timing control circuit 35 changes the precharge signal reset signal 14 (at t ^) at predetermined timing, the word line drive signal set at k number 10 (at I; 23), and the sense amplifier enable signal setting signal. (T ^), to Η for a predetermined time. This action can be shown by the starting sequence 57 in the sequence of FIG. 16 to indicate that “« in ία, the storage group selection signal is changed to [to complete the setting sequence. In the storage group 61, in [M ', the precharge signal reset signal 14 and the storage group selection signal Ul are changed to H as described above. The positive and negative circuits 21 of the latch circuit 6 are reset to change the precharge signal 8丨 to L. Here, since the word line driving signal setting signal 10 is changed to H ', the word line driving signal 7 is changed to Η, and the word line 40 is activated by the column decoder 65m. At ′, the inductive amplifier enable signal setting signal 1 $ is changed to η, and the inductive amplifier enable signal 9l is changed to Η. At tS8, the selection signal Ui is changed to Η to complete the startup sequence of the storage group 61. This action can be represented by the internal signal 59 of the storage group 61 at the timing of FIG. (Please read the note at the back first, see the deposit ^^ Binding, binding-line _ This paper size applies Chinese National Standard (CNS) W Regulations (2i〇X297.:. ≫#) A? 434879 V. Invention Explanation (27) 'During the startup sequence of the storage group 61, the storage group address of the address signal 32 is changed to assign the storage group 62, and the column address interrupt signal 31 is activated. Part 16 of the address signal 32 in FIG. 16 indicates Changed bank address and column address β Subsequently, the precharge bank decoder 44 changes the precharge bank selection h 47a to Η. The precharge timing chain of the timing control circuit 35 changes the word line drive at a predetermined timing Signal reset signal 12 (at t2j, inductive amplifier enable signal reset signal 16 (at t27), pre-charge signal set signal 13 (at I; 29), to Η, for a predetermined time. This action can be shown in Figure 16 timing The reset sequence 58 is shown. Since the sub-line drive signal reset signal 12 and the precharge storage group selection signal 472 are both changed to η by the above-mentioned actions, the positive and negative circuits 20 of the latch circuit are reset to change the word line drive. The signals B to L. Therefore, the column decoders 6 arranged in the storage group 62 52 (not shown) interrupts the character line 4 of the storage group 62 (^. Because the sense amplifier enable signal reset signal 16 and the precharge storage group selection signal 472 are changed to H, the positive and negative circuits 22 of the latch circuit 662 are reset. It is assumed that the induction amplifier enable signals 92 to j ^ are changed. As the precharge signal setting signal 13 is changed to Η, the positive and negative circuits 21 of the latch circuit 662 are set to change the precharge signals I to η, so as to complete the reset of the storage group 62. Set the sequence. This action can be represented by the internal signal 60 of the storage group 62 at the timing shown in Figure 16. In the second embodiment, the arrangement of the pre-charged storage group decoder 44 allows the storage groups parallel to each other to perform the setting sequence and the reset sequence at the same time. . That is, 'Because the data of a given storage group can be read out during the reset sequence of other storage groups', the processing speed can be increased. These sequences will not be printed at the same time. The paper size applies the Chinese National Standard (CNS). Grid (2! 0 > < 297 public ^ (please read the precautions on the back before filling)-installed · printed by the Central Standards Bureau of the Ministry of Economic Affairs and the Consumers' Cooperatives ^ 7 V. Description of the invention (28), because of the address Signal 32 at the same time A storage group is assigned for the setting sequence, and a storage group is for the reset sequence. However, if the address of the precharge signal for the address of the storage group to be precharged is also set in the same way as the address signal 32, the columns can be controlled independently using different commands. Address start signal 30 and column address interrupt signal 31, the setting sequence and reset sequence can operate completely independently. In other words, the setting sequence and reset sequence can be performed simultaneously. Corresponding to the address enable signal 34 ( The signal synchronized with the column address interruption signal 31) may be output to the precharge storage bank decoder 44 to mask the decoded output. Third Embodiment A semiconductor memory device according to a third embodiment of the present invention will be described below. The 17th circle is a block diagram of the arrangement of the semiconductor memory device of the third embodiment. The same parts as in FIG. 12 are denoted by the same reference numerals. The difference between the third embodiment semiconductor memory device and the second embodiment semiconductor memory device of FIG. 12 is that the latch circuits 66 to 664 are replaced by 96 (~ 964, timing control). The circuit 135 replaces the timing control circuit 35. The Central Standards Bureau of the Ministry of Economic Affairs has printed the sequence in the timing control control circuit 135, and the startup timing chain 137 replaces the startup timing chain 37 of the timing control circuit 35 and the precharge timing chain 136 replaces Pre-charging timing chain 36. The operation of starting timing chain 137 is the same as that of starting timing chain 37, except that starting timing chain 137 does not output any pre-charge signal reset signal 14 and induction amplifier enable signal 15, but outputs the induction enable signal. 97 to control the output timing of the inductive amplifier enable signal 9 i. In the third embodiment, the address enable signal 34 is only available at the column address. The paper scale is applicable to the Chinese national specimen Γ ^ Τ ^ ίΓ (31 434879 A 7 V. Description of the invention (29) It will start at the time of starting 30, but will not be output when the column address interruption signal 31 is activated. Storage group selection signal η ~ 114 and address enable signal 3 4 Synchronous output. However, in the reset sequence, these signals do not need to be synchronized with the address enable signal 34, because before the sensor amplifier enable signal reset signal No. 13 and the precharge signal setting signal I] are activated, There is a gap after the address interrupt signal 31 is activated. Therefore, in the third embodiment, the address enable signal 34 is only rotated out during the startup sequence. The action of the precharge timing chain 136 is the same as the precharge timing chain 36, except for the precharge The timing chain 136 does not output any word line driving signal reset signal 12. As shown in FIG. 18, 'in the latch circuits 96 to 964, compared with the interlock circuits 66 to 664 of the second embodiment, induction is enabled. Signal 97 is input, and AND circuits 24, 26, and 27 are omitted. When the storage group selection signal 11 (is changed to ', the positive and negative circuits 21 are reset and the positive and negative circuits 22 are set. When the precharge storage group selection signal 47! When changing to Η, the positive and negative circuits 20 are reset. The latch circuits 96-964 add inverters 71, 72, 75, and 76 'ρ channel MOS transistor 73 and η channel MOS transistor 74. Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards (Note on the back-fill in 1 on S)) The inverter 71 inverts the output signal of the positive and negative circuit 22 and outputs the inverted result. The gate of the n-channel MOS transistor 74 receives the induction enable signal 97 and the drain Then, the output of the inverter 71 is connected. When the sensing enable signal 97 changes to Η, the n-channel MOS transistor 74 is turned on to output the output signal of the inverter 71 to the source. The inverter 72 turns the inverter 71 The inversion result is inverted 'and outputs its inversion result to the gate of the p-channel MOS transistor 73

本紙張尺度適用中國國家標牟（CNS〉Λ4况格（2H)X29"UUM 經濟部中央標隼局貝工消費合作社印製 43'4b / 五、發明説明（30) 極。 當反相器72的輸出信號改變至L時’ p通道M〇s電 晶體73係導通以設定n通道M〇s電晶體％的源極至電 壓 VDD。 反相器75、76構成閂鎖電路，其閂鎖輸出至n通道 MOS電晶體74之源極之電壓，並將其輸出作為感應放 大器致能信號％。 第三實施例的動作將配合第17〜1S圖及第19圖時序 說明如下。 將儲存組61中位元線對字元線40交界之記憶 胞資料讀出的設定序列將說明如下。 在hi ’列位址啟動信號30啟動預定時間，時序控制 電路135則啟動位址致能信號34。隨後，儲存組解碼器 43改變儲存組選擇信號ηι至η，且列位址緩衝器45輸 出列位址信號33。這個動作與第一及第二實施例相同。 時序控制電路135的啟動時序鏈137則改變字元線驅動 信號設定信號1〇(在t3I)及感應致能信號97(在t33)，至Η。 在’由於儲存組選擇信號Ui改變至η，閂鎖電路 96,的正反電路係重設以改變預充電信號8ϊ至l。 在t32 ’由於字元線驅動信號設定信號1〇改變至η， 閂鎖電路96t的正反電路20係設定以改變字元線驅動信 號7!至Η 〇 在t33，由於感應致能信號97為Η，η通道MOS電晶 體74係導通。此時，由於儲存組選擇信號Ui為η，且 本紙张尺度適用中國國家標準（CNS ) Λ4規梢（21〇x 297々>A' > (請先間讀背面之注意事項再填ί,κ) •裝. 訂This paper scale is applicable to China National Standards (CNS> Λ4 Condition (2H) X29 " UUM Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 43'4b / V. Description of the invention (30). When inverter 72 When the output signal is changed to L, the p-channel Mos transistor 73 is turned on to set the source of the n-channel Mos transistor to the voltage VDD. The inverters 75 and 76 constitute a latch circuit and its latch output The voltage to the source of the n-channel MOS transistor 74 and its output is used as the sensing amplifier enable signal%. The operation of the third embodiment will be explained with reference to the timing of Figures 17 to 1S and Figure 19 as follows. Storage group 61 The setting sequence for reading out the memory cell data at the boundary of the median line to the character line 40 will be described as follows. The address start signal 30 at the hi 'column is activated for a predetermined time, and the timing control circuit 135 activates the address enable signal 34. Then The storage group decoder 43 changes the storage group selection signals η to η, and the column address buffer 45 outputs a column address signal 33. This operation is the same as the first and second embodiments. The start timing chain 137 of the timing control circuit 135 Change the word line drive signal setting The signal 10 (at t3I) and the induction enable signal 97 (at t33), to Η. At 'Because the storage group selection signal Ui changes to η, the positive and negative circuits of the latch circuit 96, are reset to change the precharge signal 8ϊ to l. At t32 ', as the word line drive signal setting signal 10 changes to η, the positive and negative circuit 20 of the latch circuit 96t is set to change the word line drive signal 7! To Η 〇 At t33, due to the induction The energy signal 97 is Η, and the n-channel MOS transistor 74 is turned on. At this time, because the storage group selection signal Ui is η, and this paper size is in accordance with the Chinese National Standard (CNS) Λ4 gauge (21〇x 297々) A '> (Please read the precautions on the back before filling ί, κ) • Packing. Order

經濟部中央標準局員工消t合作社印製 五、發明説明（31) 正反電路22係設定，正反電路22輸出η輸出信號，如 第19圖所示。因此，反相器71輸出L輸出信號，且η 通道MOS電晶體74的源極接收L信號。L信號閂鎖於 反相器75、76 ’其邏輯值反相至Η。Η信號則輸出作為 感應放大器致能信號\。 重設序列的動作將說明如下。 第三實施例半導體記憶裝置的動作與第二實施例相 同’除了輸出重設序列信號；的預充電時序鏈不會輸出任 何字元線驅動信號重設信號12 〇相同的動作將予以省 略。 在第三實施例的閂鎖電路96!中，正反電路20是由 預充電儲存組選擇信號471重設（而非字元線驅動信號重 設信號12) ’藉以改變字元線驅動信號\至l。 第二實施例只使用四個由時序控制電路135輸出至閂 鎖電路96广964的信號。因此，内連線的數目會減少， 且時序控制電路135中產生不同時序信號的電路數目亦 會減少，使電路面積隨之減少。另外，時序設計亦可以 簡化，因為儲存組選擇信號111可在啟動序列維持於Η， 直到字元線驅動信號7,改變至Η。 第—至第二貫施例可以四個儲存組為例。不過，本發 明卻不限於四個儲存組，而可以應用於其他數目之儲^ 組。 „在第一至第三實施例中，信號（如預充電信號重設信 號14及子元線驅動信號設定信號1〇)是由閂鎖電路 __ 34 本纸狀度 —---—~~—-——. -I------I -肿衣 i n I n n n n II n I 绍 、 ' -請先閱讀背面之注意事iji*再填} , _ 4 3^879 1 Λ, jn 五、發明説明（32 ) 6广64、66广664、96广964所閂鎖。另外，只有在啟動序 列及重設序列起始時之信號會被閂鎖，其餘信號則可藉 由排列閂鎖電路6广64 ' 66广664、96广964中的信號產生 器而產生。舉例來說’當偵測到閂鎖之預充電信號重設 信號14後，字元線驅動信號設定信號便可在延遲預 定時間後得到。這種排列可以降低内連線面積，相較於 第三實施例，並達成多工處理。 第一至第三實施例係簡化的半導體記憶裝置，其具有 複數記憶胞17形成於字元線40广40m及位元線對41广41„ 的交界。不過，允許排列字元線的長度卻有限制。因此， 在其他半導體記憶裝置中，上述實施例之字元線4心〜4〇m 形成作為主字元線’其不必直接連接記憶胞丨7。分割主 字元線至複數次字元線的次列解碼器則排列。記憶胞17 形成於次字元線及位元線對41ι〜41η的交界。在這個例 子中，控制次列解碼器的信號可利用列解碼器或其他電 路產生。通常，”字元線"表示所有次字元線、主字元線、 字元線4〇1〜4〇m，如上述實施例所提及。本發明可應用 於具有這種次字元線的半導體裝置。 經濟部中央標準局貝工消«合作社印¾ 本發明是有關於儲存組中列位址之啟動，中斷。由晶 片輸入/輸出資料的方法則與—般用途之DRam及 SDRAM相同。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内’當可做更動與潤飾’因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 本紙張尺度適用中國國家料Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs and cooperatives. V. Invention Description (31) The forward and reverse circuits 22 are set, and the forward and reverse circuits 22 output η output signals, as shown in Figure 19. Therefore, the inverter 71 outputs an L output signal, and the source of the n-channel MOS transistor 74 receives the L signal. The L signal is latched at inverters 75, 76 'and its logic value is inverted to Η. The Η signal is output as the enable signal of the sense amplifier. The operation of the reset sequence will be explained as follows. The operation of the semiconductor memory device of the third embodiment is the same as that of the second embodiment, except that a reset sequence signal is output; the precharge timing chain does not output any word line drive signal reset signal 120. The same operation will be omitted. In the latch circuit 96! Of the third embodiment, the flip-flop circuit 20 is reset by the precharge storage bank selection signal 471 (instead of the word line drive signal reset signal 12) 'to change the word line drive signal \ To l. The second embodiment uses only four signals output from the timing control circuit 135 to the latch circuits 96-964. Therefore, the number of interconnects will be reduced, and the number of circuits generating different timing signals in the timing control circuit 135 will be reduced, so that the circuit area will be reduced accordingly. In addition, the timing design can be simplified because the bank select signal 111 can be maintained at Η during the startup sequence until the word line drive signal 7 is changed to Η. The first to second embodiments can be exemplified by four storage groups. However, the present invention is not limited to four storage groups, but can be applied to other numbers of storage groups. „In the first to third embodiments, the signals (such as the pre-charge signal reset signal 14 and the sub-line drive signal setting signal 10) are controlled by the latch circuit. ~ —-——. -I ------ I -Swelling in I nnnn II n I Shao, '-Please read the notes on the back iji * before filling}, _ 4 3 ^ 879 1 Λ, jn V. Description of the invention (32) latched by 6 broadcast 64, 66 broadcast 664, 96 broadcast 964. In addition, only the signals at the start of the start sequence and reset sequence will be latched, and the remaining signals can be latched by arrangement Generated by the signal generators in the lock circuits 6 to 64, 66 to 664, and 96 to 964. For example, when the latched precharge signal reset signal 14 is detected, the word line drive signal setting signal can be set. Obtained after a predetermined time delay. This arrangement can reduce the area of the interconnect, compared to the third embodiment, and achieve multiplexing. The first to third embodiments are simplified semiconductor memory devices with multiple memory cells 17 is formed at the junction of the word line 40 to 40m and the bit line pair 41 to 41. However, there is a limit to the length of the character lines that can be arranged. Therefore, in other semiconductor memory devices, the word lines 4 ~ 4m of the above embodiment are formed as main word lines', which need not be directly connected to the memory cells. Sub-column decoders that divide the main character line into plural sub-word lines are arranged. The memory cell 17 is formed at the boundary of the sub-word line and the bit line pair 41 ι to 41 η. In this example, the signal controlling the secondary column decoder can be generated using a column decoder or other circuit. In general, "character line" means all sub-character lines, main character lines, and character lines 401 to 40 m, as mentioned in the above embodiment. The present invention can be applied to having such sub-characters Line semiconductor device. The Central Standards Bureau of the Ministry of Economic Affairs, Bei Gong Xiao «Cooperative Society Seal» This invention relates to the activation and interruption of the addresses in the storage group. The method of inputting / outputting data from the chip is similar to the general-purpose DRam and SDRAM The same. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can be treated as "modifications and retouching" without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. The paper standards are applicable to Chinese materials

Claims (1)

良修正/更正/補充 87119516中文申請專利範圍修正頁 A8 E8 C8 D8 修正日期：89/10/17 經濟邨智慧財產局員工消費合作社印製 六、申請專利範圍 ; 1，一種半導體記憶裝罝，包括： i數儲存組； 一時序控制電路，連接該些儲存组，並輸出複數的啟 動信號以啟動各儲存組及複數的預充電電路信號以在預定 時序以預定順序預充電各儲存組；以及 閂鎖電路，連接各儲存组，並將該時序控制電路之複 數的輸出信號狀態閂鎖在位址信號所指派的儲存組内。 2.如申請專利範圍第1項所述的裝置，其中，各問鎖 電路之輸出信號係一控制字元線啟動之字元線驅動信號， 一控制預充電之預充電信號’及一控制感應放大器動作之 感應放大器致能信號， 啟動各儲存組之該信號具有一字元線驅動信號之設定 信號以啟動該字元線驅動信號，一預充電重設信號以中斷 該預充電信號，及一感應玫大器致能信號設定信號以啟動 該感應放大器致能信號，以及 預充電各儲存組之該信號具有一字元線信號重設信號 以中斷該字元線驅動信號’一預充電設定信號以啟動該預 充電信號，及一感應放大器致能信號重設信號以中斷該感 應放大器致能信號。 3· —種半導體記憶裝置，包括： 複數儲存組，各具有複數記憶胞，其分別形成於複 數位元線對及複數字元線的交點，複數預充電電路，其 連接各位元線對並在一預充電信號啟動時預充電各位元 線對，複數感應放大器，其連接各位元線對並在一感應放 ______36 (請先閲讀背面之注意事項再填寫本頁) /.1¾ . · -I I I L J I 1111111! i lllll — — — — — Mi- III. -I I ϋ f n * 本紙張尺度過用中國國家標準（CNS>A4規格（210 X 297公釐） A8 B8 C8 D8 4348 7 六、申請專利範園 (請先聞讀背面之注意事項再填寫ηΓΊ ) 大器致能信號啟動時放大各儲存組，及一列解碼器，其 連接一列閂鎖電路，藉以在各儲存組啟動時閂鎖一列位 址表示之字元線之選擇/未選擇狀態及在一字元線驅動信 號啟動時啟動該列閂鎖電路表示之字元線； 一時序控制電路，具有一啟動時序鏈以在一列位址啟 動信號啟動時在預定時序以預定順序控制一字元線驅動 信號設定信號、一預充電信號重設信號、一感應放大器 致能信號設定信號，及在一列位址中斷信號啟動時在預 定時序以預定順序控制一字元線驅動信號重設信號'一 預充電信號設定信號、一感應放大器致能信號重設信號； 一儲存組解碼器，啟動一儲存組選擇信號以選擇一包 括於一位址彳5號之儲存組位址表示之儲存組； 一列位址緩衝器，輸出一列位址以作為包括於該位址 信號之一列位址信號；以及 經濟部中央標準局貝工消合作社印製 複數閂鎖電路，連接各儲存組，接收該儲存組選擇信 號，在一對應儲存組選擇信號及該位元線驅動信號設定 信號啟動時啟動該位元線驅動信號，.在該位元線驅動信 號重設彳S號啟動時中斷該位元線驅動信號，在該預充電 信號設定信號啟動時啟動該預充電信號，在該預充電信 號重设k號啟動時中斷該預充電信號，在該感應放大器 致能信號設定信號啟動時啟動該感應放大器致，能信號， 及在該感應放大器致能信號重設信號啟動時中斷該感應 放大器致能信號。 4.如申請專利範圍第3項所述的裝置，其中，各閃鎖 本紙張尺度適用中國國家標牟（CNS > A4規格Υ^7〇χ297公釐） A8 B8 C8 D8 六、申請專利範圍 電路包括： 經 部 中 央 標 隼 員 X 消 合 作 社 印 製 第邏輯電路，在該字元線驅動信號設定信號及該 儲存組選擇信號均啟動時啟動一輸出信號； —第二邏輯電路，在該字元線驅動信號重設信號及該 儲存組選擇信號均啟動時啟動一輸出信號； 一第三邏輯電路’在該預充電信號設定信號及該儲存 組選擇信號均啟動時啟動一輸出信號； 一第四邏輯電路’在該預充電信號重設信鶄及該儲存 組選擇信號均啟動時啟動一輸出信號； 一第五邏輯電路，在該感應放大器致能信號設定信號 及該儲存組選擇信號均啟動時啟動一輸出信號； 一第六邏輯電路’在該感應放大器致能信號重設信號 及該儲存組選擇信號均啟動時啟動一輸出信號； 一第一正反電路’由該第一邏輯電路之輪出信號設定 及該第二邏輯電路之輸出信號重設，並輪出一輸出信號 以作為該字元線驅動信號； 一第二正反電路，由該第三邏輯電路之輪出信號設定 及該第四邏輯電路之輸出信號重設，並輪出—輸出作號 以作為該預充電信號；以及 一第三正反電路，由該第五邏輯電路之輪出信號役定 及該弟六邏輯電路之輸出信號重設，並輸出—輪_出^| 以作為該感應放大器致能信號。 5.如申請專利範圍第4項所述的裝置，其中，該f置 更包括一預充電儲存組解碼器，其啟動一預充電储存組 38 本紙張尺度逋用中國國家標隼（CNS ) A4規格（210X297公釐） 請 先 閲--Good amendments / corrections / additions 87115516 Chinese patent application scope revision page A8 E8 C8 D8 Revision date: 89/10/17 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Economic Village 6. Application scope of patents; 1. A semiconductor memory device, including : I-number storage groups; a timing control circuit connected to the storage groups and outputting a plurality of start signals to activate each storage group and a plurality of pre-charge circuit signals to pre-charge the storage groups in a predetermined sequence at a predetermined timing; and a latch The lock circuit is connected to each storage group, and latches a plurality of output signal states of the timing control circuit in the storage group designated by the address signal. 2. The device according to item 1 of the scope of patent application, wherein the output signal of each interlock circuit is a character line drive signal that controls the activation of the character line, a precharge signal that controls precharging 'and a control induction An inductive amplifier enabling signal for amplifier operation, the signal for activating each storage group has a set signal of a word line drive signal to activate the word line drive signal, a precharge reset signal to interrupt the precharge signal, and a The inductive amplifier enable signal setting signal is used to activate the inductive amplifier enable signal, and the signal pre-charging each storage group has a word line signal reset signal to interrupt the word line drive signal 'a pre-charge setting signal The pre-charging signal is activated, and a sense amplifier enable signal reset signal is used to interrupt the sense amplifier enable signal. 3. A semiconductor memory device, comprising: a plurality of storage units each having a plurality of memory cells, which are respectively formed at the intersections of a plurality of bit line pairs and a plurality of digital element lines, and a plurality of precharge circuits which are connected to each of the element line pairs and A pre-charging signal is pre-charged for each elementary pair, a plurality of inductive amplifiers, which are connected to each elementary pair and placed in an induction ______36 (Please read the precautions on the back before filling this page) /.1¾. · -IIILJI 1111111! I lllll — — — — — Mi- III. -II ϋ fn * This paper has been used in China National Standard (CNS > A4 size (210 X 297 mm) A8 B8 C8 D8 4348 7 (Please read the precautions on the back before filling in ηΓΊ.) When the enable signal of the amplifier is activated, each storage group is amplified, and a row of decoders is connected to a row of latch circuits, so that a row of address indications are latched when each storage group is activated. The selected / unselected state of the zigzag line and the zigzag line indicated by the row of latch circuits are activated when a word line drive signal is activated; a timing control circuit having a startup timing chain to When the address enable signal is activated, a word line drive signal setting signal, a precharge signal reset signal, an inductive amplifier enable signal setting signal are controlled at a predetermined timing and in a predetermined sequence. The timing controls a word line drive signal reset signal 'a pre-charge signal set signal, an inductive amplifier enable signal reset signal in a predetermined sequence; a storage bank decoder which activates a storage bank selection signal to select one included in a The storage group indicated by the storage group address of address 彳 5; a row of address buffers that output a row of addresses as one of the address signals included in the address signal; and printed by the Beiye Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A plurality of latching circuits are connected to each storage bank, receiving the storage bank selection signal, and activating the bit line driving signal when a corresponding storage bank selection signal and the bit line driving signal setting signal are activated. In the bit line Drive signal reset: The bit line drive signal is interrupted when S number is started, and the pre-charge is started when the precharge signal setting signal is started. Electrical signal, interrupt the precharge signal when the precharge signal reset k is activated, activate the inductive amplifier enable signal when the inductive amplifier enable signal setting signal is activated, and reset the inductive amplifier enable signal When the signal is activated, the induction amplifier enable signal is interrupted. 4. The device as described in item 3 of the scope of patent application, wherein the paper size of each flash lock is in accordance with China National Standards (CNS > A4 SpecificationΥ ^ 7〇χ297 公公(%) A8 B8 C8 D8 6. The scope of the patent application circuit includes: The logic circuit printed by the Ministry of Economics Central Standards X Consumer Cooperative Co., Ltd. will start an output when the word line drive signal setting signal and the storage group selection signal are both activated. Signals;-a second logic circuit that activates an output signal when both the word line drive signal reset signal and the storage group selection signal are activated; a third logic circuit 'sets the precharge signal setting signal and the storage group selection An output signal is activated when all the signals are activated; a fourth logic circuit resets the signal at the precharge signal and the storage group selection signal. An output signal is activated during operation; a fifth logic circuit activates an output signal when both the inductive amplifier enable signal setting signal and the storage group selection signal are activated; a sixth logic circuit 'reactivates the inductive amplifier enable signal An output signal is activated when both the set signal and the storage group selection signal are activated; a first positive and negative circuit is set by a round-out signal of the first logic circuit and an output signal of the second logic circuit is reset, and a The output signal is used as the word line driving signal; a second forward and reverse circuit is set by the round signal of the third logic circuit and the output signal of the fourth logic circuit is reset, and the output is output as a number as The pre-charge signal; and a third positive and negative circuit, which is determined by the output signal of the fifth logic circuit and the output signal of the sixth logic circuit is reset, and outputs -wheel_out ^ | as the induction amplifier Enable signal. 5. The device according to item 4 of the scope of patent application, wherein the device further includes a pre-charged storage group decoder, which activates a pre-charged storage group. The paper size is in accordance with China National Standard (CNS) A4. Specifications (210X297mm) Please read- 面 之 注. 意 事 項， 再Face note. ij 線 434879 A8 B8 C8 D8 夂、申請專利範圍 選擇信號以選擇一包括於該位址信號之一預充電儲存組 位址表示之儲存組’且該閂鎖電路只在該預充電儲存組 選擇信號啟動時’啟動該字元線驅動信號重設信號、該 預充電信號設定信號、該感應放大器致能信號重設信號 以作為進行預充電之信號。 6.如申請專利範圍第5項所述的裝置，其中，各閂鎖 電路包括： 一第一邏輯電路’在該字元線驅動信號設定信號及該 預充電儲存組選擇信號均啟動時啟動一輸出信號； 一第二邏輯電路’在該字元線驅動信號重設信號及該 預充電儲存組選擇信號均啟動時啟動一輸出信號； 一第三邏輯電路，在該預充電信號設定信號及該預充 電儲存組選擇信號均啟動時啟動一輸出信號； 一第四邏輯電路，在該預充電信號重設信號及該預充 電儲存組選擇信號均啟動時啟動一輸出信號； 經濟部中央標準局員工消費合作社印製 ---------裝— -· 『* '(請先¾讀背面之注$項再填 一第五邏輯電路’在該感應放大器致能信號設定信號 及該預充電儲存組選擇信號均啟動時啟動一輪出信號； 一第六邏輯電路’在該感應放大器致能信號重設信號 及該預充電儲存組選擇信號均啟動時啟動一輸出信號； —第一正反電路，由該第一邏輯電路之輸出信號設定 及該第二邏輯電路之輸出信號重設，並輸出一.輪出信號 以作為該字元線驅動信號； 一第二正反電路’由該第三邏輯電路之輸出信號設定 及該第四邏輯電路之輸出信號重設，並輸出一輸出信號 本纸張尺度逋用中國國家標準（CNS > A4規格（210X297公竣） 4348? A8 B8 C8 D8 經濟部令央標準局員工消費合作社印裝 六、申請專利範圍 以作為該預充電信號；以及 一第三正反電路’由該第五邏輯電路之輸出信號設定 及該第六邏輯電路之輸出信號重設，並輸出一輸出信號 以作為該感應放大器致能信號。 7.彳種半導體記憶裝置，包括·· 複數儲存组，各具有複數記憶胞，其分別形成於複數 位元線對及複數字元線的交點，複數預充電電路，其連 接各位元線對並在一預充電信號啟動時預充電各位元線 對，複數感應放大器，其連接各位元線對並在一感應放 大器致能信號啟動時放大一電壓輸出至該位元線對，及 一列解碼器，其只在一儲存組選擇信號啟動時，閂鎖一 列位址t说以啟動該列位址信號表示之位元線； 一時序控制電路’具有一啟動時序鏈，藉以在一列位 址啟動信號啟動時，在預定時序以預定順序控制一感應 致能信號以控制啟動該字元線驅動信號設定信號及該感 應放大器致能信號之時序，及一預充電時序鏈’藉以在 一列位址中斷信號啟動時，在預定時序以預定順序控制 一預充電信號設定信號及一感應放大器致能信號重設信 號； 一儲存組解碼器，啟動一儲存組選擇信號以選擇一包 括於一位址信號之儲存組位址表示之儲存組； 一預充電儲存組解碼器，啟動一預充電儲存組選擇信 號以選擇一包括於該位址信號之一預充電儲存組位址之 儲存組； 本紙張尺度適用中國國家標準（CNS)A4i[^7Tl 0X297^ ) ---------^------#--：----線 (請先閲貧背面之注意事項再填寫ο) 3 經濟部中央標率局員工消費合作社印裝 4 IB A8 BS C8 D& 申請專利範圍 列位址緩衝器’輸出一列位址以作為包括於該位址 信號之該列位址信號；以及 複數閂鎖電路，連接各儲存組，接收該儲存組選擇信 號在—對應儲存組選擇信號及該位元線驅動信號設定 信號啟動時啟動該位元線驅動信號，在該預充電儲存组 選擇彳S號啟動時中斷該位元線驅動信號，在該預充電儲 存/且選擇彳g號及該預充電信號設定信號啟動時啟動該預 充電信號，在該預充電儲存組環擇信號啟動時中斷該預 充電信號，在該儲存組選擇信號及該感應放大器致能信 號啟動時啟動該感應放大器致能信號，及在該預充電儲 存組選擇信號及該感應放大器致能信號重設信號啟動時 中斷該感應放大器致能信號。 8·如申請專利範圍第7項所述的裝置，其中，各閃鎖 電路包括： 一第一邏輯電路，在該字元線驅動信號設定信號及該 儲存組選擇信號均啟動時啟動一輸出信號； 一第二邏輯電路，在該預充電信號設定信號及該儲存 組選擇信號均啟動時啟動一輸出信號； 一第二邏輯電路，在該感應放大器致能信號重設信號 及該儲存組選擇信號均啟動時啟動一輸出信號； 一第一正反電路，由該第一邏輯電路之輸出·信號設定 及該預充電儲存組選擇信號重設，並輸出一輪出信號以 作為該字元線驅動信號； 一第二正反電路’由該第二邏輯電路之輸出信號設定 請 先 閲 讀 背 £r 之 注 I 、Λ 裝 -訂 41 本紙張尺度適用中國國家榇準（CNS ) Α4現格（2Ι0Χ297公着） A8 ^B7g；< ιι D8 六、申請專利範圍 及該儲存組選擇信號重設，並輸出一輸出信號以作為該 預充電信號； 一第三正反電路，由該儲存組選擇信號設定及該第三 邏輯電路之輸出信號重設；以及 一電路，閂鎖該第三正反電路之輸出信號，並在該感 應致能信號啟動時輸出該輸出信號以作為該感應放大器 致能信號。 ------Ί----^-- - (请先聞讀背面之注意事項存填) 4T 線 經濟部中央標率局員工消費合作社印製 本紙張尺度逋用中國國家標準（CNS ) ΑΊ規名（210X297公釐）ij line 434879 A8 B8 C8 D8 夂, patent application range selection signal to select a storage group represented by the address of a precharge storage group address included in one of the address signals, and the latch circuit selects the signal only in the precharge storage group At start-up, the word line drive signal reset signal, the pre-charge signal set signal, and the sense amplifier enable signal reset signal are activated as signals for pre-charging. 6. The device according to item 5 of the scope of patent application, wherein each latch circuit includes: a first logic circuit 'starts when the word line drive signal setting signal and the precharge storage group selection signal are both activated An output signal; a second logic circuit 'activates an output signal when the word line drive signal reset signal and the precharge storage group selection signal are both activated; a third logic circuit, the precharge signal setting signal and the An output signal is activated when the precharge storage group selection signal is activated; a fourth logic circuit activates an output signal when both the precharge signal reset signal and the precharge storage group selection signal are activated; an employee of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the consumer cooperative --------- installation--"" * (please read the note $ item on the back and fill in a fifth logic circuit first. When the charging storage group selection signal is activated, a round of output signal is started; a sixth logic circuit is when the induction amplifier enable signal reset signal and the pre-charge storage group selection signal are both activated Start an output signal;-a first positive and negative circuit, set by the output signal of the first logic circuit and reset the output signal of the second logic circuit, and output a .round out signal as the word line drive signal; A second positive and negative circuit is set by the output signal of the third logic circuit and the output signal of the fourth logic circuit is reset, and an output signal is output. This paper size uses the Chinese national standard (CNS > A4 specification ( 210X297 completed) 4348? A8 B8 C8 D8 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. The scope of patent application is used as the precharge signal; and a third positive and negative circuit is output by the fifth logic circuit The setting and the output signal of the sixth logic circuit are reset, and an output signal is output as the enabling signal of the induction amplifier. 7. A semiconductor memory device includes a plurality of storage groups each having a plurality of memory cells, which are respectively Formed at the intersection of the multiple bit line pair and the multiple digital line, a multiple precharge circuit is connected to each bit line pair and precharged when a precharge signal is activated Electrical element pairs, multiple inductive amplifiers, which are connected to each element pair and amplify a voltage output to the bit pair when an inductive amplifier enable signal is activated, and a column of decoders, which select signals only in one storage group At start-up, a column of address t is latched and the bit line indicated by the start of the column address signal is latched; a timing control circuit 'has a start-up timing chain, whereby when a start-up signal of a column of addresses is started, at a predetermined timing in a predetermined sequence Controlling an inductive enable signal to control the timing of activating the word line drive signal setting signal and the inductive amplifier enable signal, and a pre-charge timing chain to start a sequence of address interrupt signals at a predetermined timing in a predetermined sequence Controlling a pre-charging signal setting signal and an inductive amplifier enabling signal reset signal; a storage group decoder, activating a storage group selection signal to select a storage group included in a storage group address indication included in a bit address signal; a Precharge storage bank decoder, activate a precharge storage bank selection signal to select a precharge included in the address signal Storage group address of storage group; This paper size applies to Chinese National Standard (CNS) A4i [^ 7Tl 0X297 ^) --------- ^ ------ #-: ---- line (Please read the notes on the back of the poor before filling it out.) 3 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 IB A8 BS C8 D & Patent Application Scope List Address Buffer 'Output a list of addresses for inclusion in the The column address signal of the address signal; and a plurality of latch circuits connected to each storage group, receiving the storage group selection signal, the bit line is activated when the corresponding storage group selection signal and the bit line drive signal setting signal are activated The drive signal interrupts the bit line drive signal when the pre-charge storage group selects the 启动 S number to start, and starts the pre-charge signal when the pre-charge storage / and selects the 彳 g number and the pre-charge signal setting signal is started. The pre-charge storage group selection signal is interrupted when the pre-charge signal is activated, the induction amplifier enable signal is activated when the storage group selection signal and the sense amplifier enable signal are activated, and the pre-charge storage group selection signal and the Sense amplifier The interrupt enable signal when the sense amplifier enable signal reset signal. 8. The device according to item 7 of the scope of patent application, wherein each flash lock circuit includes: a first logic circuit that activates an output signal when the word line drive signal setting signal and the storage group selection signal are both activated A second logic circuit that activates an output signal when both the precharge signal setting signal and the storage group selection signal are activated; a second logic circuit that resets the signal of the inductive amplifier enable signal and the storage group selection signal When both are started, an output signal is started; a first positive and negative circuit is reset by the output and signal setting of the first logic circuit and the precharge storage group selection signal, and a round-out signal is output as the word line driving signal A second positive and negative circuit 'is set by the output signal of this second logic circuit. Please read the note of r. I, Λ binding-binding 41 This paper size is applicable to China National Standards (CNS) Α4 now (2Ι0 × 297) (Writing) A8 ^ B7g; < ιι D8 6. The scope of the patent application and the storage group selection signal are reset, and an output signal is output as the precharge signal; A third positive and negative circuit, which is set by the storage group selection signal and the output signal of the third logic circuit is reset; and a circuit that latches the output signal of the third positive and negative circuit and is activated by the induction enable signal The output signal is outputted as the enabling signal of the sense amplifier. ------ Ί ---- ^--(Please read and read the notes on the back first and fill it in) 4T Printed by the Central Standardization Bureau of the Ministry of Economic Affairs, Employees' Cooperatives, printed this paper standard, using Chinese National Standards (CNS ) ΑΊ regulatory name (210X297 mm)
TW087119516A 1997-11-28 1998-11-24 Semiconductor memory device having a plurality of storage units TW434879B (en)

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DE69828021T2 (en) 2005-12-01
KR19990045665A (en) 1999-06-25

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