CN112997285A - 制造电子设备的方法 - Google Patents

制造电子设备的方法 Download PDF

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Publication number
CN112997285A
CN112997285A CN202080006098.5A CN202080006098A CN112997285A CN 112997285 A CN112997285 A CN 112997285A CN 202080006098 A CN202080006098 A CN 202080006098A CN 112997285 A CN112997285 A CN 112997285A
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China
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region
resin
electrode
paste
electronic device
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CN202080006098.5A
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English (en)
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河野壮人
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Sumitomo Electric Device Innovations Inc
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Sumitomo Electric Device Innovations Inc
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Publication of CN112997285A publication Critical patent/CN112997285A/zh
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    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

制造电子部件的方法具有:准备安装基板的工序,该安装基板设置有用于安装电子部件的第1区域和导电性的第2区域;用树脂将所述第2区域包覆的工序;在所述第1区域对金属膏进行涂敷的工序;通过所述金属膏在所述第1区域对所述电子部件进行安装的工序;以及将包覆所述第2区域的所述树脂去除的工序。所述进行安装的工序包含加热工序,即,在涂敷于所述第1区域的所述金属膏上载置所述电子部件的状态下,对所述安装基板进行加热而使所述金属膏硬化。在所述去除的工序中,将通过所述加热工序从所述第2区域剥离的状态的所述树脂去除。

Description

制造电子设备的方法
技术领域
本发明涉及制造电子设备的方法。
本申请基于2019年6月19日申请的日本申请第2019-113595号而要求优先权,引用在上述日本申请中记载的全部记载内容。
背景技术
在专利文献1中公开了电路装置的制造方法,其包含下述工序:在金属箔形成芯片焊盘及键合焊盘;经由钎料将半导体元件固接于芯片焊盘;以及进行半导体元件和键合焊盘的导线键合。在该制造方法中,通过在金属箔形成分离槽,从而通过分离槽使芯片焊盘及键合焊盘彼此分离。同时以包围将半导体元件固接于芯片焊盘的预定的区域的方式形成比分离槽浅的槽。
专利文献2公开了半导体装置的制造方法,其包含下述工序:在非导电性的基台(Submount)的表面设置的金属膜附着钎料;用钎料将半导体发光元件芯片键合于金属膜;以及将导线在金属膜进行导线键合。上述的金属膜的表面包含金属膜露出区域和钎料附着区域,在金属膜露出区域内设置有使基台露出的金属去除部。金属去除部配置于导线键合部和钎料附着区域之间。
专利文献1:日本特开2004-71898号公报
专利文献2:日本特开2005-5681号公报
发明内容
本发明所涉及的制造电子设备的方法具有:准备安装基板的工序,该安装基板设置有用于安装电子部件的第1区域和导电性的第2区域;用树脂将所述第2区域包覆的工序;在所述第1区域对金属膏进行涂敷的工序;通过所述金属膏在所述第1区域对所述电子部件进行安装的工序;以及将包覆所述第2区域的所述树脂去除的工序,所述进行安装的工序包含加热工序,即,在涂敷于所述第1区域的所述金属膏上载置有所述电子部件的状态下,对所述安装基板进行加热而使所述金属膏硬化,在去除的工序中,将通过加热工序从第2区域剥离的状态的树脂去除。
附图说明
图1是表示第1实施方式所涉及的电子设备的结构的斜视图。
图2A是用于对第1实施方式所涉及的电子设备的制造方法进行说明的斜视图。
图2B是接着图2A,用于对第1实施方式所涉及的电子设备的制造方法进行说明的斜视图。
图2C是接着图2B,用于对第1实施方式所涉及的电子设备1的制造方法进行说明的斜视图。
图3A是接着图2C,用于对第1实施方式所涉及的电子设备的制造方法进行说明的斜视图。
图3B是接着图3A,用于对第1实施方式所涉及的电子设备的制造方法进行说明的斜视图。
图3C是接着图3B,用于对第1实施方式所涉及的电子设备的制造方法进行说明的斜视图。
图4A是接着图3C,用于对第1实施方式所涉及的电子设备的制造方法进行说明的斜视图。
图4B是接着图4A,用于对第1实施方式所涉及的电子设备1的制造方法进行说明的斜视图。
图5是表示第2实施方式所涉及的受光模块的结构的剖视图。
图6是将图5所示的受光模块的受光部的光电二极管附近的结构放大而表示的剖视图。
图7是将封装件及透镜去除后的受光部的俯视图。
图8是用于对第2实施方式所涉及的受光模块的制造方法进行说明的俯视图。
图9是接着图8,用于对第2实施方式所涉及的受光模块的制造方法进行说明的俯视图。
图10A是表示变形例所涉及的电子设备的结构的斜视图。
图10B是表示其他变形例所涉及的电子设备的结构的斜视图。
图11A是用于说明对比例所涉及的电子设备的制造方法的斜视图。
图11B是接着图11A,用于说明对比例所涉及的电子设备的制造方法的斜视图。
图11C是接着图11B,用于说明对比例所涉及的电子设备的制造方法的斜视图。
图11D是接着图11C,用于说明对比例所涉及的电子设备的制造方法的斜视图。
具体实施方式
[本发明所要解决的课题]
在将半导体元件等电子部件进行芯片键合时,有时取代钎料而使用银膏等金属膏。在如上述的情况下,有时银膏泄漏扩散至键合焊盘。但是,例如,如果在用于导线键合的区域附着银膏,则有可能由于附着的银膏而键合导线的密接性降低。如上所述,有可能由于金属膏泄漏扩散而在通过导线键合等进行的电连接时发生不良。
[本发明的效果]
根据本发明的一个实施方式所涉及的制造电子设备的方法,能够抑制在通过导线键合等进行的电连接时发生不良。
[本发明的实施方式的说明]
首先,本发明的实施方式的内容列举而进行说明。一个实施方式所涉及的制造电子设备的方法具有:准备安装基板的工序,该安装基板设置有用于安装电子部件的第1区域和导电性的第2区域;用树脂将第2区域包覆的工序;在第1区域对金属膏进行涂敷的工序;通过金属膏在第1区域对电子部件进行安装的工序;以及将包覆第2区域的树脂去除的工序。进行安装的工序包含加热工序,即,在涂敷于第1区域的金属膏上载置有电子部件的状态下,对安装基板进行加热而使金属膏硬化。在去除的工序中,将通过加热工序从第2区域剥离的状态的树脂去除。
在一个实施方式所涉及的制造电子设备的方法中,在向第1区域涂敷金属膏时,第2区域由树脂包覆。由此,即使在金属膏没有收容于第1区域内的情况下,试图附着于第2区域的金属膏也会附着于树脂。由此,抑制金属膏附着于第2区域。包覆了第2区域的树脂在安装电子部件后金属膏成为不易流动的状态后在去除的工序中被去除。在这里,在进行安装的工序中,利用用于使金属膏硬化的安装基板的加热而使树脂从第2区域剥离,因此在去除的工序中能够简单地将树脂去除。由此,金属膏中的附着于树脂的部分与树脂一起被去除。因此,在树脂的去除过程中及去除后,均会抑制金属膏向从树脂露出的第2区域附着的情况。通过以上方式,能够抑制在通过向第2区域的导线键合等进行的电连接时发生不良。
上述的方法也可以还具有将键合导线的一端与第2区域进行连接的工序。
在上述的方法中,也可以是电子部件包含形成有第1电极的第1面和朝向与第1面相反侧并形成有第2电极的第2面,第1区域是与第2区域电分离的导电性的区域,在进行安装的工序中,第2电极经由金属膏而与第1区域连接,由此在第1区域对电子部件进行安装。在该情况下,通过树脂防止涂敷于第1区域的金属膏到达第2区域。由此,能够避免第1区域和第2区域的绝缘性受损。
在上述的方法中,也可以将第1电极和第2区域通过导线键合进行连接。在该情况下,考虑到第1区域和第2区域配置于比较近的位置。因此,能够更有效地应用通过树脂防止金属膏到达第2区域的结构。
在上述的方法中,树脂可以是UV硬化型树脂或热硬化型树脂。这些树脂大多是在比金属膏的硬化温度低的温度下容易剥离的树脂。因此,作为树脂选择在比金属膏的硬化温度低的温度下容易剥离的树脂,由此能够通过进行安装的工序中的加热而充分地使第2区域的树脂剥离。
在上述的方法中,安装基板中的第2区域的周围的区域的材料可以是氧化铝或氮化铝。树脂容易从这些材料剥离。因此,即使在进行包覆的工序中用树脂包覆至安装基板的主面的露出区域为止的情况下,也能够通过进行安装的工序中的加热使树脂从主面容易地剥离。
在上述的方法中,在去除的工序中,也可以将树脂与树脂上的金属膏的一部分一起去除。在进行涂敷的工序前也可以还具有下述工序,即,以第1温度对安装基板进行加热,由此使树脂硬化。也可以在加热工序中,以比第1温度高的第2温度对安装基板进行加热而使金属膏硬化。也可以在包覆的工序中,以树脂不会将第1区域包覆的方式用树脂将第2区域包覆。
[本发明的实施方式的详细内容]
以下,参照附图对本发明的实施方式所涉及的制造电子设备的方法的具体例进行说明。此外,本发明不受这些例示限定,而是由权利要求书示出,包含与权利要求书等同的内容及其范围内的全部变更。在下面的说明中,对相同要素或具有相同功能的要素标注相同标号,有时省略重复的说明。
(第1实施方式)
图1是表示本发明的第1实施方式所涉及的电子设备1的结构的斜视图。如图1所示,电子设备1具有绝缘性的安装基板2和安装于安装基板2上的半导体芯片3(电子部件)。安装基板2例如呈矩形板状,具有安装了半导体芯片3的主面2a。安装基板2例如由氧化铝或氮化铝构成。在安装基板2的主面2a设置有两个电极焊盘4、5。
电极焊盘4、5是通过由具有导电性的材料进行金属化而形成的。作为电极焊盘4、5的材料的具体例而举出金(Au)。电极焊盘4、5的材料也可以是银(Ag)。一个电极焊盘4是本实施方式中的第1区域的一个例子,形成有用于安装半导体芯片3的配线图案。另一个电极焊盘5是本实施方式中的第2区域的一个例子,形成有用于导线键合的配线图案。在本实施方式中,电极焊盘4、5在主面2a上彼此分离。即,电极焊盘4是在主面2a上与电极焊盘5电分离的区域。
半导体芯片3例如通过银膏(Ag膏)6这样的金属膏而安装于电极焊盘4。Ag膏6具有Ag填料和环氧树脂类的粘结剂。粘结剂例如是热硬化型树脂。
半导体芯片3包含第1面3a和与第1面3a相反侧的第2面3b。第1面3a是朝向与安装基板2相反侧的面。在第1面3a例如通过Au金属化等形成有电极3p(第1电极)。电极3p通过由Au线构成的导线W1(键合导线)而与电极焊盘5电连接。第2面3b是朝向安装基板2的主面2a的面。在第2面3b例如通过Au金属化等形成有电极3q(第2电极)。电极3q通过Ag膏6而与电极焊盘4电连接。半导体芯片3的第1面3a及第2面3b的尺寸各自例如为纵300μm、横700μm。
图2A至图4B是用于对第1实施方式所涉及的电子设备1的制造方法进行说明的斜视图。首先,如图2A所示,准备设置有电极焊盘4、5的安装基板2(第1工序;进行准备的工序)。接下来,如图2B所示,用熔融的状态的树脂7将电极焊盘5包覆(第2工序;进行包覆的工序)。此时,以树脂7不会将电极焊盘4包覆的方式,用树脂7将电极焊盘5包覆。具体地说,通过进行树脂7的灌封等而将树脂7涂敷于电极焊盘5。例如,从避免电极焊盘5的露出的观点出发,也可以用树脂7包覆至电极焊盘5的周围的区域为止。但是,只要至少用树脂7将电极焊盘5包覆即可。例如,树脂7为环氧树脂类的UV硬化型树脂。但是,作为树脂7也可以使用热硬化型树脂。
接下来,如图2C所示,通过对安装基板2进行加热而使树脂7硬化。具体地说,将安装基板2移送至加热器块8上,通过加热器块8对安装基板2进行加热。例如,在将安装基板2搭载于加热器块8的上表面8a的状态下使加热器块8的上表面8a上升至第1温度(例如120度)为止。安装基板2在将上表面8a设为第1温度的状态下直至经过规定时间(例如60分钟)为止进行等待。然后,从加热器块8上移送安装基板2,对安装基板2进行冷却。
在安装基板2被冷却后,如图3A所示,将熔融状态的Ag膏6涂敷于电极焊盘4(第3工序;进行涂敷的工序)。具体地说,在电极焊盘4中的对半导体芯片3进行安装的区域进行Ag膏6的灌封或冲压。此时,有时涂敷于电极焊盘4的Ag膏6流动,泄漏扩散至电极焊盘4的周围。
接下来,通过Ag膏6在电极焊盘4对半导体芯片3进行安装(第4工序;进行安装的工序)。第4工序包含载置工序和加热工序。在载置工序中,如图3B所示,在涂敷于电极焊盘4的Ag膏6上载置半导体芯片3。此时,在第1面3a朝向与安装基板2相反侧、第2面3b经由Ag膏6而朝向电极焊盘4的状态下,将半导体芯片3载置于安装基板2上。
在加热工序中,如图3C所示,在涂敷于电极焊盘4的Ag膏6上载置有半导体芯片3的状态下,对安装基板2进行加热而使Ag膏6硬化。具体地说,将安装基板2再次移送至加热器块8上,通过加热器块8对安装基板2进行加热。例如在将安装基板2搭载于加热器块8的上表面8a的状态下,使加热器块8的上表面8a上升至比第1温度高的第2温度(例如180度)为止。然后,在上表面8a为第2温度的状态下等待规定时间(例如60分钟)。由此,Ag膏6硬化。
在加热工序中,树脂7从电极焊盘5剥离。其原因可想到如果树脂7成为高温,则与安装基板2的表面(例如氧化铝)相比会大幅地收缩(或者膨胀)。在本实施方式的例子中,如表1所示,树脂7在Ag膏6的硬化温度下特别容易剥离。表1示出了按照各温度的树脂7的剥离程度和Ag膏6的硬化程度之间的关系。此时,如果树脂7从电极焊盘5剥离,则Ag膏6中的附着于树脂7的部分也会与树脂7一起剥离。
【表1】
温度 树脂 Ag膏
120℃ 完全硬化 未硬化
140℃ 剥离小 硬化小
160℃ 剥离中 硬化中
180℃ 完全剥离 完全硬化
接下来,如图4A所示,将包覆了电极焊盘5的树脂7去除(第5工序;进行去除的工序)。在第5工序中,例如使用镊子或吹风机等将通过加热工序从电极焊盘5剥离的状态的树脂7去除。此时,与树脂7一起剥离的Ag膏6也被去除。由此,电极焊盘5露出。
接下来,如图4B所示,将导线W1的一端通过键合与电极焊盘5连接(第6工序;进行连接的工序)。将导线W1的另一端通过键合与半导体芯片3的电极3p连接。由此,电极3p和电极焊盘5通过导线键合而连接。通过以上方式,半导体芯片3向电子设备1的安装完成,制造出电子设备1。
然后,也可以进行电子设备1向其他电子设备的连接等。例如将电极焊盘4中的没有涂敷Ag膏6的区域和其他电子设备通过导线W2进行电连接。在上述第2工序中,也可以将与导线W2的一端连接的区域用树脂7进一步包覆。
对以上说明的电子设备1的制造方法的作用效果进行说明。在本实施方式所涉及的电子设备1的制造方法中,在将半导体芯片3向电极焊盘4安装时使用Ag膏6。Ag膏6的通用性高、密接性也高。因此,能够使用通用性高的材料而确保半导体芯片3和电极焊盘4的密接性。
在这里,对如上所述的使用Ag膏6的情况下的对比例所涉及的制造方法进行说明。图11A至图11D是用于说明对比例所涉及的电子设备1X的制造方法的斜视图。首先,如图11A所示,准备设置有电极焊盘4、5的安装基板2。该工序与上述第1工序同样地进行。接下来,如图11B所示,将熔融状态的Ag膏6涂敷于电极焊盘4。在这里,与上述第3工序同样地,在电极焊盘4中的对半导体芯片3进行安装的区域进行Ag膏6的灌封或冲压。此时,有时涂敷于电极焊盘4的Ag膏6流动,泄漏扩散至电极焊盘4的周围。
接下来,如图11C所示,通过Ag膏6在电极焊盘4安装半导体芯片3。该工序与上述第4工序同样地进行。由此,Ag膏6硬化。另一方面,以熔融状态泄漏扩散至电极焊盘4的周围的Ag膏6也直接硬化。因此,有时通过硬化的Ag膏6将电极焊盘5覆盖。
如图11D所示,在该状态下,如果将电极3p和电极焊盘5通过导线W1进行电连接,则会将导线W1的一端与Ag膏6连接。但是,在如上所述地制造出的电子设备1X中,电极焊盘4、5的绝缘性受损,因此例如在电极3q和电极焊盘5各自被施加彼此不同的电位的情况下,成为动作不良的原因。
假设在不具有电极焊盘4的结构中,也有可能由于附着于电极焊盘5的Ag膏6而使通过导线键合产生的密接性降低等,在导线键合时发生不良。其原因在于,Ag膏6的粘结剂由于热而会收缩,伴随收缩而产生的外部气体附着于Ag膏6的表面。并且,这是因为,通过粘结剂在Ag膏6中引起渗出现象。
与此相对,在本实施方式所涉及的电子设备1的制造方法中,在向电极焊盘4涂敷Ag膏6时,电极焊盘5由树脂7包覆。由此,即使在Ag膏6没有收容于电极焊盘4内的情况下,试图附着于电极焊盘5的Ag膏6也会附着于树脂7。由此,对Ag膏6向电极焊盘5附着的情况进行抑制。包覆电极焊盘5的树脂7在安装半导体芯片3后Ag膏6成为不易流动的状态后在第5工序中被去除。在这里,在第4工序中,利用用于使Ag膏6硬化的安装基板2的加热而使树脂7从电极焊盘5剥离,因此能够在第5工序中简单地将树脂7去除。由此,Ag膏6中的附着于树脂7的部分与树脂7一起被去除。因此,在树脂7的去除过程中及去除后,均会抑制Ag膏6向从树脂7露出的电极焊盘5附着的情况。由此,能够抑制在导线键合时发生不良。通过以上方式,能够提高半导体芯片3及电极焊盘4的电连接的可靠性和电极3p及电极焊盘5的电连接的可靠性这两者。
半导体芯片3包含:第1面3a,其形成有电极3p;以及第2面3b,其朝向与第1面3a相反侧,形成有电极3q。电极焊盘4是与电极焊盘5电分离的导电性的区域。在第4工序中,电极3q经由Ag膏6与电极焊盘4连接,由此将半导体芯片3安装于电极焊盘4。在该情况下也会通过树脂7防止涂敷于电极焊盘4的Ag膏6到达电极焊盘5,因此能够避免电极焊盘4、5的绝缘性受损。由此,能够避免动作不良。
将电极3p和电极焊盘5通过导线键合进行连接。在该结构中,电极焊盘4和电极焊盘5配置于比较近的位置。因此,能够更有效地应用通过树脂7防止Ag膏6到达电极焊盘5的结构。
树脂7是UV硬化型树脂或热硬化型树脂。这些材料大多是在比Ag膏6的硬化温度低的温度下容易剥离的材料。因此,通过作为树脂7而选择在比Ag膏6的硬化温度低的温度下容易剥离的树脂,从而能够通过第4工序(参照图3C)中的加热而充分地使电极焊盘5的树脂7剥离。作为金属膏,除了Ag膏6以外,也能够使用由硬化温度比树脂7的剥离温度高的材料构成的膏。作为除了Ag膏6以外的金属膏的具体例,举出金膏(Au膏)、铜膏(Cu膏)及焊料(锡铅)膏等。
安装基板2中的电极焊盘5的周围的区域的材料为氧化铝或氮化铝。树脂7由于容易从这些材料剥离,因此即使在第2工序(参照图2B)中用树脂7包覆至安装基板2的主面2a的露出区域的情况下,也能够通过第4工序中的加热而从主面2a使树脂7容易地剥离。
(第2实施方式)
接下来,作为第2实施方式,对包含上述第1实施方式所涉及的电子设备1的制造方法在内的受光模块1A的制造方法进行说明。图5是表示第2实施方式所涉及的受光模块1A的结构的剖视图,示出了沿入射光的光轴的剖面。如图5所示,受光模块1A具有:光插座10,其与光纤连接;以及受光部20,其固定于光插座10。光插座10具有光纤插芯(插芯套管)12、金属部件14、套筒16和外轮廓部件(外壳)18。光纤插芯12具有套管11和光纤13。
套管11是具有圆筒形状(或者圆柱形状)的部件。套管11的中心轴线沿方向A1延伸,套管11的与该中心轴线垂直的剖面为圆形。套管11具有在方向A1上排列的基端面11a及前端面11b。前端面11b是与连接于光插座10的光连接器的套管进行物理接触的面,例如研磨为球面状。基端面11a是与前端面11b相反侧的面,与在该光插座10安装的受光部20相对。基端面11a相对于与套管11的中心轴线垂直的面而稍微地(例如8°左右)倾斜。套管11还具有圆柱面的外周面11c。
套管11还具有光纤保持孔11d。光纤保持孔11d沿方向A1延伸,形成于套管11的中心轴上。光纤保持孔11d的剖面为圆形状,其内径稍大于光纤13的外径。光纤保持孔11d的一个开口包含于前端面11b,光纤保持孔11d的另一个开口包含于基端面11a。即,光纤保持孔11d沿方向A1将套管11的基端面11a和前端面11b之间贯通。套管11例如为氧化锆(ZrO2)制。由韧性及杨氏模量高的氧化锆构成套管11,由此能够在前端面11b适当地进行物理接触。
光纤13例如为单模光纤,是树脂包覆层被去除后的裸纤。光纤13例如为石英制。光纤13将方向A1设为长度方向(光轴方向)而延伸,具有一端13a及另一端13b。光纤13***至光纤保持孔11d。而且,一端13a从前端面11b侧的光纤保持孔11d的开口露出,另一端13b从基端面11a侧的光纤保持孔11d的开口露出。一端13a与连接于光插座10的光连接器侧的光纤的一端接触。另一端13b与受光部20的光电二极管21(后面记述)光学地耦合。光纤13的外径例如为125μm。
金属部件14是具有在方向A1延伸的贯通孔14a,在贯通孔14a内对光纤插芯12进行保持的部件。金属部件14例如由不锈钢这样的金属材料构成。金属部件14具有沿方向A1延伸的圆筒形状。金属部件14具有基端面14b及前端面14c以及外周面14d。基端面14b及前端面14c在方向A1上排列,贯通孔14a将基端面14b和前端面14c之间贯通。与方向A1垂直的贯通孔14a的剖面为圆形。基端面14b与受光部20的封装件22(后面记述)相对。光纤插芯12沿方向A1被压入至金属部件14的贯通孔14a。即,套管11的外周面11c与贯通孔14a的内表面相接,由此光纤插芯12被固定于金属部件14。
套筒16是沿方向A1延伸的圆筒状的部件,例如为陶瓷制。在一个例子中,套筒16由与套管11相同的材料(例如氧化锆)构成。套筒16的内径与光纤插芯12的外径大致相等。套筒16具有在方向A1上排列的基端16a及前端16b。套筒16具有外周面16c及内周面16d。从套筒16的基端16a侧的开口***了光纤插芯12。换言之,套筒16的基端16a侧的一部分***至套管11的外周面11c和金属部件14的间隙。因此,套筒16的外周面16c与金属部件14相接,套筒16的内周面16d与套管11的外周面11c相接。从套筒16的前端16b侧的开口***光连接器套管。套管11的前端面11b和光连接器套管的前端面在套筒16内彼此接触。由此,由套管11保持的光纤13和由光连接器套管保持的光纤以高的耦合效率而彼此光耦合。
外轮廓部件18是固定于金属部件14并且与光连接器连接的部件。外轮廓部件18是沿方向A1延伸的圆筒状的部件,例如为金属制或者不锈钢等合金制。外轮廓部件18具有凸缘部18a和沿方向A1延伸的贯通孔18d。外轮廓部件18具有在方向A1上排列的基端面18b及前端部18c。凸缘部18a是朝向外轮廓部件18的外侧凸出的圆盘状的部分。凸缘部18a设置于外轮廓部件18的基端面18b侧,在本实施方式中凸缘部18a的一个面构成基端面18b。贯通孔18d将基端面18b和前端部18c之间贯通。与方向A1垂直的贯通孔18d的剖面为圆形。贯通孔18d的中心轴线与光纤插芯12及金属部件14的中心轴线重合。外轮廓部件18包含基端面18b侧的第1部分18e和前端部18c侧的第2部分18f而作为贯通孔18d的一部分。第1部分18e从基端面18b沿方向A1延伸至第2部分18f。第2部分18f从前端部18c沿方向A1延伸至第1部分18e。而且,第1部分18e及第2部分18f在套筒16的前端16b和前端部18c之间彼此连结(连通)。第1部分18e的内径与套筒16的外周面16c的外径大致相等或稍大。第2部分18f的内径稍大于套筒16的内周面16d的内径。如上所述,第1部分18e的内径大于第2部分18f的内径,因此在第1部分18e和第2部分18f之间形成有台阶面18g。台阶面18g与套筒16的前端16b相对。
受光部20相当于第1实施方式的电子设备1。受光部20具有光电二极管21(受光元件)、封装件22、透镜23、芯柱(Stem)24、支承件25、集成电路芯片26及多个引线管脚27。
芯柱24相当于第1实施方式的安装基板2。芯柱24是大致圆形的平板状的绝缘性部件,具有平坦的主面24a。主面24a与连接于光插座10的光纤的光轴(即光纤13的光轴)交叉。在一个例子中,主面24a相对于与光插座10连接的光纤的光轴(光纤13的光轴)垂直。芯柱24例如由氧化铝或者氮化铝等陶瓷材料构成。
封装件22为大致圆筒状的金属部件。封装件22的中心轴沿光纤13的光轴。光纤13的光轴方向上的封装件22的基端侧的一端22a经由圆环状的部件29而固定于芯柱24的主面24a。具体地说,圆环状的部件29具有该光轴方向上的一端面29a及另一端面29b。封装件22的基端侧的一端22a固接于部件29的一端面29a,芯柱24的主面24a固接于部件29的另一端面29b。光纤13的光轴方向上的封装件22的前端侧的一端22b经由圆筒状的部件19而固定于金属部件14。具体地说,从部件19的前端侧的一端***金属部件14,将金属部件14的外周面和部件19的内周面彼此固接。封装件22的前端侧的一端22b固接于部件19的基端侧的面。封装件22例如由铁镍合金这样的材料构成。
多个引线管脚27是在与芯柱24的主面24a交叉的方向延伸的棒状的金属部件。多个引线管脚27将芯柱24贯通而设置,固定于芯柱24。多个引线管脚27相对于在由封装件22及芯柱24构成的空间内配置的光电二极管21及集成电路芯片26进行电信号及电源电力的收发。
透镜23保持于封装件22的内侧,相对于封装件22的内周面经由树脂23a进行固定。透镜23是由光透过部件构成的聚光透镜,配置于光纤13的光轴上。透镜23将从光纤13的另一端13b射出的光朝向光电二极管21附近聚光。为了防止来自光电二极管21的返回光,透镜23的光轴相对于光纤13的光轴而稍微偏移。
光电二极管21经由透镜23与光纤13的另一端13b光学地耦合,接收来自与光插座10连接的光纤的光而输出与该光的强度相对应的大小的电流信号。光电二极管21搭载于绝缘性的支承件25上,支承件25配置于集成电路芯片26上。即,光电二极管21经由支承件25搭载于集成电路芯片26上。集成电路芯片26是接收来自光电二极管21的电流信号,将该电流信号变换为电压信号的半导体IC。
在这里,图6是将受光部20的光电二极管21附近的结构放大而表示的侧视图。如图6所示,集成电路芯片26具有第3面26b及与第3面26b相反侧的第4面26a。第4面26a及第3面26b在光纤13的光轴方向排列,沿与该光轴方向交叉(例如正交)的平面延伸。集成电路芯片26在第4面26a与芯柱24的主面24a相对。支承件25具有第1面25b及与第1面25b相反侧的第2面25a。支承件25在第2面25a与集成电路芯片26的第3面26b相对。光电二极管21具有主面21a及与主面21a相反侧的相反面21b,从主面21a接收光。支承件25以第1面25b与光电二极管21的相反面21b相对的方式在第1面25b上搭载光电二极管21。
图7是将封装件22及透镜23去除后的受光部20的俯视图。如图7所示,在芯柱24的主面24a上设置有被规定为基准电位(接地电位)的GND图案24b。在芯柱24的周缘部设置有多个引线管脚27所包含的引线管脚27a至引线管脚27f。芯柱24具有多个绝缘区域24c,该多个绝缘区域24c用于将主面24a上的GND图案24b和周缘部的引线管脚27a至引线管脚27f电分离。多个绝缘区域24c各自是引线管脚27a至引线管脚27f的周围的区域。在GND图案24b安装有电容器41、42、44、45。GND图案24b具有3个开口,在从各开口露出的主面24a设置有导电性的GND块43。
在这里,GND图案24b是本实施方式中的第1区域的一个例子,作为第1实施方式的电极焊盘4起作用。引线管脚27a至引线管脚27f各自的上表面是本实施方式中的第2区域的一个例子,作为第1实施方式的电极焊盘5起作用。电容器41、42、44、45各自是本实施方式中的电子部件的一个例子,作为第1实施方式的半导体芯片3起作用。
集成电路芯片26具有多个电极28。在本实施方式中,各电极28是电极焊盘。多个电极28包含电极28a至电极28o。电极28a至电极28c与光电二极管21电连接。具体地说,电极28a、28c与光电二极管21的阴极电极连接,将偏置电压施加至光电二极管21。电极28b与光电二极管21的阳极电极连接,接收从光电二极管21输出的电流信号。电极28d从受光模块1A的外部输入向光电二极管21的偏置电压。
电极28d经由键合导线而与电容器41的一个电极电连接。电容器41的该一个电极相当于第1实施方式的电极3p,经由键合导线而与引线管脚27d电连接。电容器41的另一个电极经由导电性粘接剂而与GND图案24b电连接。电容器41的该另一个电极相当于第1实施方式的电极3q。在本实施方式中,作为导电性粘接剂采用第1实施方式的Ag膏6。在下面的说明中也是同样的。
电极28e、28f从受光模块1A的外部输入向集成电路芯片26的电源电压。电极28e、28f经由键合导线而与电容器42的一个电极(相当于第1实施方式的电极3p)电连接。电容器42的该一个电极经由键合导线而与引线管脚27a电连接。电容器42的另一个电极(相当于第1实施方式的电极3q)经由导电性粘接剂而与GND图案24b电连接。电极28g经由键合导线而与电容器44的一个电极(相当于第1实施方式的电极3p)电连接。电容器44的该一个电极经由键合导线而与引线管脚27b电连接。电容器44的另一个电极(相当于第1实施方式的电极3q)经由导电性粘接剂而与GND图案24b电连接。
电极28h经由键合导线而与电容器45的一个电极(相当于第1实施方式的电极3p)电连接。电容器45的该一个电极经由键合导线而与引线管脚27c电连接。电容器45的另一个电极(相当于第1实施方式的电极3q)经由导电性粘接剂而与GND图案24b电连接。电极28i、28j将基于来自光电二极管21的电流信号而生成的电压信号向受光模块1A的外部输出。一个电极28i经由键合导线而与引线管脚27e电连接。另一个电极28j经由键合导线而与其他引线管脚27f电连接。
多个电极28中的电极28k至电极28o对集成电路芯片26的基准电位(接地电位)进行规定。电极28k至电极28o经由键合导线及GND块43而与GND图案24b电连接。在其他电极28包含有电流监视器用的电极焊盘及增益调整用的电极焊盘等。
接下来,对本实施方式所涉及的受光模块1A的制造方法的一个例子进行说明。下面,参照图8及图9对制造受光部20的方法的一个例子具体地进行说明。图8及图9是用于对第2实施方式所涉及的受光模块1A的制造方法进行说明的俯视图。首先,与第1实施方式的第1工序同样地,准备芯柱24。在芯柱24的主面24a预先设置有GND图案24b。在芯柱24的周缘部预先设置有多个引线管脚27a至引线管脚27f。也可以在此处准备的芯柱24的主面24a上还安装有设置了多个电极28的集成电路芯片26。
接下来,与第1实施方式的第2工序同样地,用熔融的状态的多个树脂7分别将引线管脚27a至引线管脚27f的各上表面包覆。在这里,从避免引线管脚27a至引线管脚27f的露出的观点出发,可以以包覆至绝缘区域24c的方式涂敷树脂7。在该状态下,与第1实施方式同样地,通过对芯柱24进行加热而使各树脂7硬化。在各树脂7硬化后,对芯柱24进行冷却。在芯柱24冷却后,与第1实施方式的第3工序同样地,将熔融状态的Ag膏6涂敷于GND图案24b。具体地说,在GND图案24b中的分别安装电容器41、42、44、45的多个区域进行Ag膏6的灌封或冲压。
接下来,在GND图案24b安装电容器41、42、44、45。首先,与第1实施方式的第4工序中的载置工序同样地,在涂敷于GND图案24b的多个Ag膏6上分别载置电容器41、42、44、45。例如电容器41一上述一个电极朝向芯柱24的相反侧、上述另一个电极经由Ag膏6而朝向GND图案24b的状态载置于芯柱24上。关于电容器42、44、45也是同样的。接下来,与第1实施方式的第4工序中的加热工序同样地,在电容器41、42、44、45各自载置于多个Ag膏6上的状态下,对芯柱24进行加热而使该多个Ag膏6硬化。由此,多个树脂7各自从引线管脚27a至引线管脚27f及多个绝缘区域24c剥离。而且,与第1实施方式的第5工序同样地将剥离的各树脂7去除,由此电容器41、42、44、45向芯柱24的安装完成(参照图8)。
接下来,与第1实施方式的第6工序同样地,进行通过导线W1实施的导线键合。如图9所示,在本实施方式中,将电容器41和引线管脚27d导线键合,将电容器42和引线管脚27a导线键合,将电容器44和引线管脚27b导线键合,将电容器45和引线管脚27c导线键合。由此,电容器41及引线管脚27d经由导线W1进行电连接。电容器42及引线管脚27a、电容器44及引线管脚27b、电容器45及引线管脚27c各自电气性地经由导线W1电连接。
在本实施方式中,将多个电极28的一部分和上述电子部件导线键合。具体地说,将电极28d和电容器41导线键合,将电极28e、28f和电容器42导线键合,将电极28g和电容器44导线键合,将电极28h和电容器45导线键合。而且,将电极28i和引线管脚27e导线键合,将电极28j和引线管脚27f导线键合。并且,将电极28k至电极28o和对应的GND块43导线键合。多个电极28的一部分和上述电子部件的导线键合可以在用熔融的状态的多个树脂7分别将引线管脚27a至引线管脚27f的各上表面包覆之前进行。
接下来,在集成电路芯片26上对搭载有光电二极管21的支承件25进行搭载。而且,将电极28a至电极28c和设置于支承件25上并且与光电二极管21连接的多个配线图案分别导线键合。通过以上方式,包含电容器41、42、44、45在内的多个电子部件向芯柱24的安装完成。接下来,在芯柱24安装封装件22及透镜23而完成受光部20的制造。通过将该受光部20固定于光插座10,从而制造受光模块1A。
在以上说明的受光模块1A的制造方法中,进行第1实施方式的全部各工序,因此得到与第1实施方式相同的作用效果。特别地,在向GND图案24b(第1区域)涂敷Ag膏6时,引线管脚27a至引线管脚27f的上表面由树脂7包覆。因此,能够抑制在导线键合时发生不良。
(变形例)
以上的实施方式对本发明所涉及的电子设备的制造方法的一个实施方式进行了说明。本发明所涉及的电子设备的制造方法可以是将上述的各实施方式任意地变更后的制造方法。
例如,在第1实施方式中,对第1区域是具有导电性的电极焊盘4的例子进行了说明,但第1区域并不限定于是具有导电性的区域。另外,在第1实施方式中,在作为电子部件的半导体芯片3的第2面3b形成有电极3q,但电子部件并不限定于在第2面3b形成有电极3q。换言之,电子部件中的没有进行金属化的面也可以通过Ag膏6而粘接固定于安装基板2。图10A是表示变形例所涉及的电子设备1B的结构的斜视图。电子设备1B与电子设备1的不同点在于,取代安装基板2而具有安装基板2B,取代半导体芯片3而具有半导体芯片3B。下面,对不同点进行说明。
安装基板2B与安装基板2B的不同点在于,在主面2a没有设置电极焊盘4。在电子设备1B中,由氧化铝或氮化铝构成的安装基板2B的主面2a中的一部分相当于第1区域。具体地说,电子设备1B中的第1区域是主面2a中的对半导体芯片3进行配置的部分及其周围的部分、且没有配置电极焊盘5的部分。电子设备1B中的第1区域可以是除了配置有电极焊盘5的区域和其周围以外的部分。半导体芯片3B与半导体芯片3的不同点在于,在第1面3a形成有电极3p、3q这两者,在第2面3b没有形成电极3q。电极3p、3q在第1面3a中彼此电分离地配置。半导体芯片3B可以是TIA(Trans Impedance Amp)。
例如,在是第2面3b没有进行金属化的半导体芯片3B的情况下,如果通过焊料、金锡等钎料进行安装,则有时不能充分地得到密接性。与此相对,通过Ag膏6进行安装,由此确保充分的密接性。另外,在制造该电子设备1B时也在电极焊盘5由树脂7包覆的状态下在主面2a(第1区域)涂敷Ag膏6,由此能够抑制在导线键合时发生不良。
在第1实施方式中,电极3p和电极焊盘5进行了导线键合,但也可以是电极3p和电极焊盘5不进行电连接。图10B是表示变形例所涉及的电子设备1C的结构的斜视图。电子设备1C与电子设备1的不同点在于,还具有导线W3。在电子设备1C中,导线W1的另一端没有与电极3p连接,而是与外部的另一电子部件(未图示)等连接。导线W3的一端通过导线键合而与电极3p连接。导线W3的另一端没有与电极焊盘5连接,而是与外部的其他电子部件(未图示)等连接。在制造该电子设备1C时也在电极焊盘5由树脂7包覆的状态下在电极焊盘4(第1区域)涂敷Ag膏6,由此能够抑制在通过导线W1进行的导线键合时发生不良。
标号的说明
1、1B、1C…电子设备
1A…受光模块
2、2B…安装基板
2a…主面
3、3B…半导体芯片(电子部件)
3a…第1面
3b…第2面
3p…电极(第1电极)
3q…电极(第2电极)
4…电极焊盘(第1区域)
5…电极焊盘(第2区域)
6…Ag膏(金属膏)
7…树脂
8…加热器块
8a…上表面
10…光插座
11…套管
11a…基端面
11b…前端面
11c…外周面
11d…光纤保持孔
12…光纤插芯
13…光纤
13a…一端
13b…另一端
14…金属部件
14a…贯通孔
14b…基端面
14c…前端面
14d…外周面
16…套筒
16a…基端
16b…前端
16c…外周面
16d…内周面
18…外轮廓部件
18a…凸缘部
18b…基端面
18c…前端部
18d…贯通孔
18e…第1部分
18f…第2部分
18g…台阶面
19…部件
20…受光部
21…光电二极管(受光元件)
21a…主面
21b…相反面
22…封装件
23…透镜
23a…树脂
24…芯柱
24a…主面
24b…GND图案
24c…绝缘区域
25…支承件
25a…第2面
25b…第1面
26…集成电路芯片
26a…第4面
26b…第3面
27a至27f…引线管脚
28、28a至28o…电极
29…部件
41、42、44、45…电容器
43…GND块
W1、W2、W3…导线(键合导线)。

Claims (10)

1.一种制造电子设备的方法,其具有:
准备安装基板的工序,该安装基板设置有用于安装电子部件的第1区域和导电性的第2区域;
用树脂将所述第2区域包覆的工序;
在所述第1区域对金属膏进行涂敷的工序;
通过所述金属膏在所述第1区域对所述电子部件进行安装的工序;以及
将包覆所述第2区域的所述树脂去除的工序,
所述进行安装的工序包含加热工序,即,在涂敷于所述第1区域的所述金属膏上载置所述电子部件的状态下,对所述安装基板进行加热而使所述金属膏硬化,
在所述去除的工序中,将通过所述加热工序从所述第2区域剥离的状态的所述树脂去除。
2.根据权利要求1所述的制造电子设备的方法,其中,
还具有将键合导线的一端与所述第2区域进行连接的工序。
3.根据权利要求1或2所述的制造电子设备的方法,其中,
所述电子部件包含形成有第1电极的第1面和朝向与所述第1面相反侧并形成有第2电极的第2面,
所述第1区域是与所述第2区域电分离的导电性的区域,
在所述进行安装的工序中,所述第2电极经由所述金属膏而与所述第1区域连接,由此在所述第1区域对所述电子部件进行安装。
4.根据权利要求3所述的制造电子设备的方法,其中,
将所述第1电极和所述第2区域通过导线键合进行连接。
5.根据权利要求1至4中任一项所述的制造电子设备的方法,其中,
所述树脂是UV硬化型树脂或热硬化型树脂。
6.根据权利要求1至4中任一项所述的制造电子设备的方法,其中,
所述安装基板中的所述第2区域的周围的区域的材料是氧化铝或氮化铝。
7.根据权利要求1至6中任一项所述的制造电子设备的方法,其中,
在所述去除的工序中,将所述树脂与所述树脂上的所述金属膏的一部分一起去除。
8.根据权利要求1至7中任一项所述的制造电子设备的方法,其中,
在所述进行涂敷的工序前还具有下述工序,即,以第1温度对所述安装基板进行加热,由此使所述树脂硬化。
9.根据权利要求8所述的制造电子设备的方法,其中,
在所述加热工序中,以比所述第1温度高的第2温度对所述安装基板进行加热而使所述金属膏硬化。
10.根据权利要求1至9中任一项所述的制造电子设备的方法,其中,
在所述包覆的工序中,以所述树脂不会将所述第1区域包覆的方式用所述树脂将所述第2区域包覆。
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1198873A (zh) * 1996-08-09 1998-11-11 松下电工株式会社 对独立导体电路进行电镀的工艺
CN1426103A (zh) * 2001-12-14 2003-06-25 矽品精密工业股份有限公司 可设置无源元件的芯片承载件
CN101355857A (zh) * 2007-07-25 2009-01-28 Tdk株式会社 电子部件内置基板及其制造方法
WO2010125858A1 (ja) * 2009-04-29 2010-11-04 株式会社 村田製作所 樹脂多層回路基板及び樹脂多層回路基板の製造方法
CN103295923A (zh) * 2012-03-02 2013-09-11 瑞萨电子株式会社 制造半导体器件的方法和半导体器件
US20130286565A1 (en) * 2012-04-27 2013-10-31 Canon Kabushiki Kaisha Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus
JP2014099536A (ja) * 2012-11-15 2014-05-29 Dainippon Printing Co Ltd リードフレームの製造方法、半導体装置の製造方法、リードフレーム基材、および半導体装置
JP2016032076A (ja) * 2014-07-30 2016-03-07 株式会社加藤電器製作所 電子デバイスの製造方法及び電子デバイス
US20160268167A1 (en) * 2013-11-06 2016-09-15 Sharp Kabushiki Kaisha Production method for semiconductor element, and semiconductor element
CN106463473A (zh) * 2014-06-26 2017-02-22 凸版印刷株式会社 配线基板、半导体装置以及半导体装置的制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4093818B2 (ja) 2002-08-07 2008-06-04 三洋電機株式会社 半導体装置の製造方法
JP2005005681A (ja) 2003-05-20 2005-01-06 Sharp Corp 半導体発光装置およびその製造方法
JP6116413B2 (ja) * 2013-07-09 2017-04-19 三菱電機株式会社 電力用半導体装置の製造方法
JP6214576B2 (ja) * 2015-01-08 2017-10-18 三菱電機株式会社 半導体デバイスの製造方法
JP6636846B2 (ja) 2016-04-14 2020-01-29 ローム株式会社 半導体装置および半導体装置の製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1198873A (zh) * 1996-08-09 1998-11-11 松下电工株式会社 对独立导体电路进行电镀的工艺
CN1426103A (zh) * 2001-12-14 2003-06-25 矽品精密工业股份有限公司 可设置无源元件的芯片承载件
CN101355857A (zh) * 2007-07-25 2009-01-28 Tdk株式会社 电子部件内置基板及其制造方法
WO2010125858A1 (ja) * 2009-04-29 2010-11-04 株式会社 村田製作所 樹脂多層回路基板及び樹脂多層回路基板の製造方法
CN103295923A (zh) * 2012-03-02 2013-09-11 瑞萨电子株式会社 制造半导体器件的方法和半导体器件
US20130286565A1 (en) * 2012-04-27 2013-10-31 Canon Kabushiki Kaisha Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus
JP2014099536A (ja) * 2012-11-15 2014-05-29 Dainippon Printing Co Ltd リードフレームの製造方法、半導体装置の製造方法、リードフレーム基材、および半導体装置
US20160268167A1 (en) * 2013-11-06 2016-09-15 Sharp Kabushiki Kaisha Production method for semiconductor element, and semiconductor element
CN106463473A (zh) * 2014-06-26 2017-02-22 凸版印刷株式会社 配线基板、半导体装置以及半导体装置的制造方法
JP2016032076A (ja) * 2014-07-30 2016-03-07 株式会社加藤電器製作所 電子デバイスの製造方法及び電子デバイス

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