CN112953503A - High-linearity grid voltage bootstrap switch circuit - Google Patents

High-linearity grid voltage bootstrap switch circuit Download PDF

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CN112953503A
CN112953503A CN202110133246.6A CN202110133246A CN112953503A CN 112953503 A CN112953503 A CN 112953503A CN 202110133246 A CN202110133246 A CN 202110133246A CN 112953503 A CN112953503 A CN 112953503A
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nmos
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CN112953503B (en
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唐鹤
韦祖迎
周绍虎
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University of Electronic Science and Technology of China
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    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only

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Abstract

The invention relates to a gate voltage bootstrap switch circuit with high linearity, which disconnects the source end of a fourth NMOS tube from the source end of a first NMOS, and then grounds the source end of the fourth NMOS tube, thereby eliminating the correlation between the parasitic capacitance of the fourth NMOS tube and an input signal, reducing the nonlinear capacitance in the circuit and improving the linearity of the whole circuit, wherein the parasitic capacitance of the fourth NMOS tube is not connected with the lower electrode plate of the first capacitor any more; meanwhile, in order to improve the reliability of the circuit, the auxiliary module is introduced, so that in the sampling stage, before the clock signal is at a high level and the first PMOS tube is conducted, the grid voltage of the first PMOS tube is pulled down to the ground voltage through the auxiliary module so as to conduct the first PMOS tube, and then the connection between the auxiliary module and the first PMOS tube is disconnected, so that the grid voltage of the first PMOS tube is not pulled down to the ground any more and follows the voltage of the input signal of the grid voltage bootstrap switch circuit, the normal function of the circuit is ensured, and the first PMOS tube is ensured not to bear excessive voltage drop.

Description

High-linearity grid voltage bootstrap switch circuit
Technical Field
The invention belongs to the technical field of analog integrated circuits, and relates to a high-linearity grid voltage bootstrap switch circuit which can be used for a sample-and-hold circuit, is particularly suitable for a sample-and-hold circuit formed by SAR ADC and CDAC, and samples and holds an input signal for subsequent circuit processing.
Background
With the progress of integrated circuit technology and the development of communication industry, the processing of signals tends to be more and more digitalized, because digital signals have the advantages of strong anti-interference capability, easy integration, low power consumption, low cost and the like. Real-world signals, such as temperature, sound, etc., are typically continuous signals in analog form. Analog-to-digital converters (ADCs) are an indispensable part of integrated circuits as an important bridge between analog and digital signals.
The process of converting continuous input signals into direct current signals in the ADC is called sample and hold, and is realized by controlling the on and off of a sampling switch. Various non-ideal factors exist in the sampling switch, which affect the accuracy of the sampled signal, thereby introducing non-linear errors, and the errors of the sampled signal directly affect the precision of the whole ADC. Therefore, in the process of designing the ADC, the design of the sampling switch is an extremely important part, and a switch with a small influence on the accuracy should be selected, and the gate voltage bootstrap switch becomes an important choice for the sampling switch because of its high linearity.
Fig. 1 is a circuit topology diagram of a conventional gate voltage bootstrapped switch. The sampling circuit comprises a sampling switch tube Ms, a bootstrap capacitor Cb, 6 NMOS tubes MN1, MN2, MN3, MN4, MN5 and MN6, and three PMOS tubes MP1, MP2 and MP3, wherein the sampling capacitor Cs is provided by a circuit connected behind a grid voltage bootstrap switch. The clock signal CK and the inverted clock signal CKB are used for controlling the working stage of the grid voltage bootstrap switch.
The working principle of the traditional grid voltage bootstrap switch is as follows:
a sampling stage: the clock signal CK is at a high level, the inverted signal CKB of the clock signal is at a low level, so that the fourth NMOS transistor MN4 is turned on, the third PMOS transistor MP3 is turned off, and the gate voltage of the first PMOS transistor MP1 is pulled low to turn on the first PMOS transistor MP1, so that the first NMOS transistor MN1 and the sampling switch transistor Ms are turned on, the input signal Vin is transmitted to the lower plate of the bootstrap capacitor Cb, the bootstrap capacitor Cb stores the charge amount VDD Cb charged in the holding stage, so the voltage at the point G is VDD + Vin, and the source voltage of the sampling switch transistor Ms is Vin, so the gate-source voltage of the sampling switch transistor Ms is fixed to the power voltage VDD in the sampling stage.
A maintaining stage: the clock signal CK is at a low level, the third PMOS transistor MP3 is turned on, the fourth NMOS transistor MN4 is turned off, the gate voltage of the first PMOS transistor MP1 is pulled to VDD, so that the first PMOS transistor MP1 is in an off state, the inverted signal CKB of the clock signal is at a high level, so that the third NMOS transistor MN3 is turned on, meanwhile, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are also turned on, the voltage at the point G is discharged to ground, so that the second PMOS transistor MP2MP2 is turned on, and the turn-on of the second PMOS transistor MP2 and the third NMOS transistor MN3 charges the voltage Cb on the bootstrap capacitor to VDD; the voltage at the point G is pulled down to the ground voltage, so the sampling switch tube Ms and the first NMOS tube MN1 are turned off, and the output voltage Vout keeps the sampled voltage unchanged.
The on-resistance of the sampling switch can be formulated as:
Figure BDA0002926102440000021
wherein munFor carrier mobility, CoxIs the unit area gate oxide layer capacitance of the sampling switch tube Ms, W/L is the width-length ratio of the sampling switch tube Ms, VGSFor sampling the gate-source voltage, V, of the switching tube MsTHThe conduction threshold voltage of the sampling switch tube Ms is obtained.
The grid voltage bootstrapped switch enables the grid source voltage V of the sampling switch tube MsGSThe voltage is fixed to VDD in the sampling stage, so that the on-resistance of the voltage is almost unchanged, and the sampling switch tube V is reducedGSNon-linear distortion caused by the variation. However, the tube is not ideal and there are various parasitic parameters, such as parasitic capacitance, that introduce non-linear distortion that affects linearity. The parasitic capacitance of the fourth NMOS transistor MN4 greatly affects the linearity of the circuit, because when the clock signal CK is at a high level, the gate voltage of the fourth NMOS transistor MN4 is the power voltage VDD, and the source and drain voltages are the input voltage Vin, the gate-source capacitance and the gate-drain capacitance of the fourth NMOS transistor MN4 are input-dependent, when the inputs are different, the values of the gate-source capacitance and the gate-drain capacitance are also different, and the parasitic capacitance of the fourth NMOS transistor MN4 is connected to the lower plate of the bootstrap capacitor Cb, which all introduce significant nonlinearity and limit the linearity of the whole circuit.
Disclosure of Invention
Aiming at the linearity problem caused by the fourth NMOS tube in the traditional gate voltage bootstrap switch, the invention provides a gate voltage bootstrap switch circuit with high linearity, wherein the source electrode of the fourth NMOS tube MN4 is connected to the ground voltage, so that the correlation between the gate source capacitor and the gate drain capacitor of the fourth NMOS tube MN4 and the input signal Vin can be eliminated, the parasitic capacitor of the fourth NMOS tube MN4 is not connected with the lower pole plate of the bootstrap capacitor Cb any more, and the linearity of the circuit is further improved; in addition, an auxiliary module is introduced to ensure that the gate-source voltage drop and the gate-drain voltage drop of the first PMOS transistor MP1 are not subjected to too high voltage drop.
The technical scheme of the invention is as follows:
a high-linearity grid voltage bootstrap switch circuit comprises a first capacitor, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a sampling switch tube, wherein the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube and connected with a clock signal, and the source electrode of the third PMOS tube is connected with the source electrode of the second PMOS tube and the grid electrode of the fifth NMOS tube and connected with a power supply voltage; the grid electrode of the sixth NMOS tube is connected with the grid electrode of the third NMOS tube and is connected with the inverted signal of the clock signal, the source electrode of the sixth NMOS tube is connected with the source electrode of the third NMOS tube and is grounded, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the sampling switch tube, the drain electrode of the fifth NMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube, the drain electrode of the first NMOS tube is connected with the source electrode of the sampling switch tube and is connected with an input signal of the grid voltage bootstrap switch circuit, and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the third NMOS tube and one end of the first capacitor; the drain electrode of the sampling switch tube outputs an output signal of the grid voltage bootstrap switch circuit; the substrate and the source electrode of the first PMOS tube are connected with the substrate and the drain electrode of the second PMOS tube and connected with the other end of the first capacitor; the grid electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube;
the source electrode of the fourth NMOS tube is grounded; the grid voltage bootstrap switch circuit further comprises an auxiliary module arranged between the drain electrode of the third PMOS tube and the drain electrode of the fourth NMOS tube, and the auxiliary module is used for controlling the grid voltage of the first PMOS tube; when the clock signal is at a high level, the third PMOS tube is cut off, the fourth NMOS tube is conducted, before the first PMOS tube is conducted, the grid voltage of the first PMOS tube is pulled down to the ground voltage through the auxiliary module to conduct the first PMOS tube, and then the connection between the auxiliary module and the first PMOS tube is disconnected, so that the grid voltage of the first PMOS tube follows the voltage of the input signal of the grid voltage bootstrap switch circuit; when the clock signal is at a low level, the third PMOS tube is switched on, the fourth NMOS tube is switched off, and the grid voltage of the first PMOS tube is pulled up by the auxiliary module to switch off the first PMOS tube.
Specifically, the auxiliary module comprises a fourth PMOS transistor, a source electrode of the fourth PMOS transistor is connected to a drain electrode of the third PMOS transistor and a gate electrode of the first PMOS transistor, a drain electrode of the fourth PMOS transistor is connected to a drain electrode of the fourth NMOS transistor, and a gate electrode of the fourth PMOS transistor is connected to a first node, so that a source electrode of the fifth NMOS transistor and a drain electrode of the sixth NMOS transistor are the first node; when the clock signal is at a high level, before the first PMOS tube is conducted, the voltage of the first node is the ground voltage to conduct the fourth PMOS tube, the conducted fourth PMOS tube and the conducted fourth NMOS tube pull down the grid voltage of the first PMOS tube to the ground voltage, the first PMOS tube is conducted, the voltage of the first node is pulled up to turn off the fourth PMOS tube, and the grid voltage of the first PMOS tube is ensured to follow the voltage of the input signal of the grid voltage bootstrap switch circuit.
The invention has the beneficial effects that: according to the invention, the source electrode of the fourth NMOS tube is grounded, so that the parasitic capacitance of the fourth NMOS tube is no longer related to the input signal and is no longer connected with the lower pole plate of the first capacitor Cb, the nonlinear capacitance in the circuit is reduced, and the linearity of the whole circuit is improved; in addition, the auxiliary module is introduced, so that the gate source voltage or the gate drain voltage of the first PMOS tube is prevented from bearing the voltage drop exceeding the power supply voltage VDD, and the reliability of the circuit is improved.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a schematic diagram of a conventional gate voltage bootstrapped switch circuit.
Fig. 2 is a schematic structural diagram of a high linearity gate voltage bootstrap switch circuit in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, the gate voltage bootstrapped switch circuit with high linearity provided by the present invention includes a first capacitor Cb (the first capacitor Cb is the bootstrapped capacitor in fig. 1), a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a sampling switch transistor Ms and an auxiliary module, wherein the connection similar to the conventional structure is: the grid electrode of the third PMOS tube MP3 is connected with the grid electrode of the fourth NMOS tube MN4 and is connected with a clock signal CK, and the source electrode of the third PMOS tube MP3 is connected with the source electrode of the second PMOS tube MP2 and the grid electrode of the fifth NMOS tube MN5 and is connected with a power supply voltage VDD; the grid electrode of the sixth NMOS transistor MN6 is connected with the grid electrode of the third NMOS transistor MN3 and is connected with the inverted signal CKB of the clock signal, the source electrode of the sixth NMOS transistor MN6 is connected with the source electrode of the third NMOS transistor MN3 and is grounded, and the drain electrode of the sixth NMOS transistor MN6 is connected with the source electrode of the fifth NMOS transistor MN 5; the grid electrode of the first NMOS tube MN1 is connected with the grid electrode of the second NMOS tube MN2, the grid electrode of the sampling switch tube Ms, the drain electrode of the fifth NMOS tube MN5, the drain electrode of the first PMOS tube MP1 and the grid electrode of the second PMOS tube MP2, the drain electrode of the first NMOS tube MN1 is connected with the source electrode of the sampling switch tube Ms and is connected with the input signal Vin of the grid voltage bootstrap switch circuit, and the source electrode of the first NMOS tube MN2, the drain electrode of the third NMOS tube MN3 and one end of the first capacitor Cb; the drain electrode of the sampling switch tube Ms outputs a grid voltage output signal Vout of the bootstrap switch circuit; the substrate and the source of the first PMOS transistor MP1 are connected with the substrate and the drain of the second PMOS transistor MP2 and connected with the other end of the first capacitor Cb; the gate of the first PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN 2.
In a conventional gate voltage bootstrap switch circuit, the source electrode of the fourth NMOS transistor is connected to the source electrode of the first NMOS transistor, which results in that the gate-source capacitance and the gate-drain capacitance of the fourth NMOS transistor MN4 are related to the input signal Vin, a change in the input signal Vin may result in a change in the gate-source capacitance and the gate-drain capacitance of the fourth NMOS transistor MN4, and the parasitic capacitance of the fourth NMOS transistor MN4 is connected to the lower plate of the bootstrap capacitor Cb, which destroys the linear characteristic of the circuit. Based on this, in the gate voltage bootstrap switch circuit provided by the present invention, the source of the fourth NMOS transistor MN4 is grounded, so that the gate-source capacitance and the gate-drain capacitance of the fourth NMOS transistor MN4 are no longer related to the input signal Vin, and the parasitic capacitance of the fourth NMOS transistor MN4 is no longer connected to the lower plate of the bootstrap capacitance Cb, thereby improving the linear characteristic of the circuit.
However, since the source of the fourth NMOS transistor MN4 is grounded, and the gate voltage of the first PMOS transistor MP1 is pulled down to ground during the sampling period, which may cause the gate-source voltage drop and the gate-drain voltage drop of the first PMOS transistor MP1 to be too high, the present invention further introduces an auxiliary module disposed between the drain of the third PMOS transistor MP3 and the drain of the fourth NMOS transistor MN4, where the auxiliary module is used to control the gate voltage of the first PMOS transistor MP 1; in the sampling stage, the clock signal CK is at a high level, the third PMOS transistor MP3 is turned off, the fourth NMOS transistor MN4 is turned on, before the first PMOS transistor MP1 is turned on, the auxiliary module pulls down the gate voltage of the first PMOS transistor MP1 to the ground voltage to turn on the first PMOS transistor MP1, and then the auxiliary module is disconnected from the first PMOS transistor MP1, so that the gate voltage of the first PMOS transistor MP1 is not pulled down to the ground any more, but follows the voltage of the input signal Vin of the gate voltage bootstrap switch circuit, and it is ensured that the first PMOS transistor MP1 does not bear an excessive voltage drop; in the hold stage, the clock signal CK is at a low level, the third PMOS transistor MP3 is turned on, the fourth NMOS transistor MN4 is turned off, and the auxiliary block pulls up the gate voltage of the first PMOS transistor MP1 to turn off the first PMOS transistor MP 1.
A specific implementation structure of the auxiliary module is provided in some embodiments, and those skilled in the art should understand that other structures capable of implementing the auxiliary module can also be applied to the present invention, and the embodiment does not limit the auxiliary structure. As shown in fig. 2, the auxiliary module in this embodiment includes a fourth PMOS transistor MP4, a source of the fourth PMOS transistor MP4 is connected to a drain of the third PMOS transistor MP3 and a gate of the first PMOS transistor MP1, a drain of the fourth PMOS transistor MP4 is connected to a drain of the fourth NMOS transistor MN4, and a gate of the fourth PMOS transistor MP1 is connected to a first node X, such that a source of the fifth NMOS transistor MN5 and a drain of the sixth NMOS transistor MN6 are set as the first node X; when the clock signal CK is at a high level, before the first PMOS transistor MP1 is turned on, the voltage of the first node X is the ground voltage to turn on the fourth PMOS transistor MP4, the turned-on fourth PMOS transistor MP4 and the turned-on fourth NMOS transistor MN4 pull down the gate voltage of the first PMOS transistor MP1 to the ground voltage, and the first PMOS transistor MP1 is turned on, so that the voltage of the first node X is pulled up to turn off the fourth PMOS transistor MP4, thereby ensuring that the gate voltage of the first PMOS transistor MP1 follows the voltage of the gate voltage bootstrap switch circuit input signal Vin.
The working process of the embodiment is described in detail as follows:
when the clock signal CK is at a high level, the gate voltage bootstrapped switch circuit is in a sampling phase, before the first PMOS transistor MP1 is not turned on, the G-point voltage (i.e. the drain terminal of the fifth NMOS transistor) and the X-point voltage are pulled to the ground voltage by the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, so that the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are turned on, the third PMOS transistor MP3 is turned off, the gate voltage of the first PMOS transistor MP1 is pulled to the ground voltage, the first PMOS transistor MP1 is turned on, so that the G-point is connected to one end of the first capacitor Cb, in some embodiments, the end of the first capacitor Cb connected to the first PMOS transistor 58mp 86525 is an upper plate, the end of the first capacitor Cb connected to the first NMOS transistor MN1 is a lower plate, i.e. the G-point is connected to the upper plate of the first capacitor Cb, the G-point voltage is raised to the upper plate of the first capacitor Cb, so that the first NMOS transistor MN4, the second NMOS transistor MN2 and the first capacitor MN 49324 are turned on, so that the first NMOS transistor MN1 is connected to the first capacitor MN Vin, since the total charge stored in the first capacitor Cb is not changed, the upper plate voltage of the first capacitor Cb is VDD + Vin, that is, the G point voltage is VDD + Vin, so that the gate-source voltages of the sampling switch tube Ms, the first NMOS tube MN1, and the second NMOS tube MN2 are the power supply voltage VDD, and therefore the on-resistance of the sampling switch tube Ms is almost unchanged.
When the clock signal CK is at a low level, the gate voltage bootstrapped switch circuit is in a hold stage, the third PMOS transistor MP3 is turned on, the gate potential of the first PMOS transistor MP1 is pulled high to turn off the first PMOS transistor MP1, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN5 are turned on, and the point G is discharged to the ground potential, so that the sampling switch transistor Ms, the first NMOS transistor MN1 and the second NMOS transistor MN2 are all turned off, the output is kept unchanged, and the second PMOS transistor MP2 and the third NMOS transistor MN3 are all turned on to charge the voltage on the first capacitor Cb to the power supply voltage VDD.
In the conventional structure, when the clock signal CK is at a high level, the gate voltage of the fourth NMOS transistor MN4 is the power voltage VDD, and the source and drain thereof are the input voltage Vin, so the gate-source capacitance and the gate-drain capacitance of the fourth NMOS transistor MN4 are related to the input voltage Vin and are connected to the lower plate of the first capacitor Cb, and when the input voltage Vin is different, the values of the gate-source capacitance and the gate-drain capacitance are also different, which introduces significant nonlinearity to the circuit and limits the linearity of the whole circuit. Compared with the traditional structure, the high-linearity grid voltage bootstrap switch circuit provided by the invention has the advantages that the source electrode of the fourth NMOS tube MN4 controlled by the clock signal CK is not connected with the lower pole plate of the first capacitor Cb any more but is grounded, so that the parasitic capacitance of the fourth NMOS tube MN4, such as the grid source capacitance and the grid drain capacitance, is not connected with the first capacitor Cb any more, the parasitic capacitance is not related to input any more, the nonlinear capacitance in the circuit is reduced, and the linearity of the circuit is obviously improved.
The design of the gate voltage bootstrap switch circuit also needs to ensure the reliability, i.e. the gate source voltage, the gate drain voltage and the drain source voltage of the transistor cannot bear the excessive voltage, so the fourth PMOS transistor MP4 is introduced in the present embodiment. In the sampling phase, the inverted signal CKB of the clock signal is at a low level, and the sixth NMOS transistor MN6 is turned off, so that no current flows through the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, and the gate voltage of the fifth NMOS transistor MN5 is the power voltage VDD, so that the source voltage, i.e., the voltage at the X point (the gate voltage of the fourth PMOS transistor MP 4) is also the power voltage VDD, so that the fourth PMOS transistor MP4 is turned off, and the gate-source voltage and the gate-drain voltage of the fourth PMOS transistor MP4 cannot bear a voltage drop exceeding the power voltage VDD. Because the second NMOS transistor MN2 is turned on, the gate voltage of the first PMOS transistor MP1 is the input voltage Vin, the gate-source voltage and the gate-drain voltage of the first PMOS transistor are both the power voltage VDD and cannot bear a voltage drop exceeding the power voltage VDD, the gate-source voltage, the gate-drain voltage and the drain-source voltage of the fourth NMOS transistor cannot bear a voltage drop exceeding VDD, and the gate-source voltage, the gate-drain voltage and the drain-source voltage of other transistors are not bear a voltage drop exceeding the power voltage VDD as in the conventional structure, which ensures the reliability of the high-linearity gate voltage bootstrap switch circuit provided by the present invention.
The above embodiments are only used to illustrate the technical solution of the present invention and not to limit the present invention, and the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. It will be understood by those skilled in the art that various modifications and equivalent arrangements may be made without departing from the spirit and scope of the present invention and it should be understood that the present invention encompasses the full ambit of the claims appended hereto. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.

Claims (2)

1. A high-linearity grid voltage bootstrap switch circuit comprises a first capacitor, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a sampling switch tube, wherein the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth NMOS tube and connected with a clock signal, and the source electrode of the third PMOS tube is connected with the source electrode of the second PMOS tube and the grid electrode of the fifth NMOS tube and connected with a power supply voltage; the grid electrode of the sixth NMOS tube is connected with the grid electrode of the third NMOS tube and is connected with the inverted signal of the clock signal, the source electrode of the sixth NMOS tube is connected with the source electrode of the third NMOS tube and is grounded, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube; the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the sampling switch tube, the drain electrode of the fifth NMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube, the drain electrode of the first NMOS tube is connected with the source electrode of the sampling switch tube and is connected with an input signal of the grid voltage bootstrap switch circuit, and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the drain electrode of the third NMOS tube and one end of the first capacitor; the drain electrode of the sampling switch tube outputs an output signal of the grid voltage bootstrap switch circuit; the substrate and the source electrode of the first PMOS tube are connected with the substrate and the drain electrode of the second PMOS tube and connected with the other end of the first capacitor; the grid electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube;
the source electrode of the fourth NMOS tube is grounded; the grid voltage bootstrap switch circuit further comprises an auxiliary module arranged between the drain electrode of the third PMOS tube and the drain electrode of the fourth NMOS tube, and the auxiliary module is used for controlling the grid voltage of the first PMOS tube; when the clock signal is at a high level, the third PMOS tube is cut off, the fourth NMOS tube is conducted, before the first PMOS tube is conducted, the grid voltage of the first PMOS tube is pulled down to the ground voltage through the auxiliary module to conduct the first PMOS tube, and then the connection between the auxiliary module and the first PMOS tube is disconnected, so that the grid voltage of the first PMOS tube follows the voltage of the input signal of the grid voltage bootstrap switch circuit; when the clock signal is at a low level, the third PMOS tube is switched on, the fourth NMOS tube is switched off, and the grid voltage of the first PMOS tube is pulled up by the auxiliary module to switch off the first PMOS tube.
2. The high-linearity gate voltage bootstrapped switch circuit of claim 1, wherein the auxiliary module comprises a fourth PMOS transistor, a source of the fourth PMOS transistor is connected to a drain of the third PMOS transistor and a gate of the first PMOS transistor, a drain of the fourth PMOS transistor is connected to a drain of a fourth NMOS transistor, a gate of the fourth PMOS transistor is connected to a first node, and a source of the fifth NMOS transistor and a drain of the sixth NMOS transistor are the first node; when the clock signal is at a high level, before the first PMOS tube is conducted, the voltage of the first node is the ground voltage to conduct the fourth PMOS tube, the conducted fourth PMOS tube and the conducted fourth NMOS tube pull down the grid voltage of the first PMOS tube to the ground voltage, the first PMOS tube is conducted, the voltage of the first node is pulled up to turn off the fourth PMOS tube, and the grid voltage of the first PMOS tube is ensured to follow the voltage of the input signal of the grid voltage bootstrap switch circuit.
CN202110133246.6A 2021-02-01 2021-02-01 High-linearity grid voltage bootstrap switch circuit Expired - Fee Related CN112953503B (en)

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Cited By (4)

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CN113726321A (en) * 2021-09-06 2021-11-30 联合微电子中心有限责任公司 Bootstrap switch circuit and analog-to-digital converter
WO2023137790A1 (en) * 2022-01-24 2023-07-27 福州大学 High-linearity bootstrapped switch circuit for sensor, and control method therefor
CN116886094A (en) * 2023-07-24 2023-10-13 同济大学 Bootstrap switch sampling circuit
CN117674830A (en) * 2023-10-25 2024-03-08 隔空微电子(深圳)有限公司 Voltage signal conversion module and phase-locked loop structure

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