CN216625715U - Floating type dynamic latch comparator and successive approximation type analog-to-digital converter - Google Patents
Floating type dynamic latch comparator and successive approximation type analog-to-digital converter Download PDFInfo
- Publication number
- CN216625715U CN216625715U CN202123382549.6U CN202123382549U CN216625715U CN 216625715 U CN216625715 U CN 216625715U CN 202123382549 U CN202123382549 U CN 202123382549U CN 216625715 U CN216625715 U CN 216625715U
- Authority
- CN
- China
- Prior art keywords
- dynamic latch
- power supply
- tube
- comparator
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The embodiment of the application provides a floating type dynamic latch comparator and a successive approximation type analog-to-digital converter, wherein the floating type dynamic latch comparator comprises: the dynamic latch comparison unit and the energy storage unit are connected with a power supply end and a power supply ground end of the dynamic latch comparison unit, and a signal input end and a signal output end are respectively configured to input a sampling voltage and output a voltage comparison result; the input end of the energy storage unit is connected with a power supply, the output end of the energy storage unit is connected with the dynamic latch comparison unit, and the energy storage unit is used for enabling the power supply to charge a storage capacitor in the energy storage unit during voltage sampling and switching to the storage capacitor to discharge so as to provide required working voltage for the dynamic latch comparison unit during voltage comparison. The design can effectively solve the problem of the change of the overdrive voltage caused by the gradual reduction of the input common-mode voltage, and further can maintain the characteristics of the comparator unchanged.
Description
Technical Field
The application relates to the technical field of comparator circuits, in particular to an aerostatic dynamic latching comparator and a successive approximation type analog-to-digital converter.
Background
At present, successive approximation type analog-to-digital converters (SAR ADCs) gradually become mainstream designs in analog-to-digital converter technology due to the comprehensive advantages of high speed, high precision, low power consumption and the like, wherein a monotone decreasing type capacitance switch array conversion scheme is also mainstream, because the monotone decreasing type capacitance switch scheme uses a small number of switches and is high in capacitance switching speed, the sampling frequency of the ADCs can be improved, and meanwhile, the lower power consumption and the chip area are kept. However, the voltage input to the later-stage comparator is monotonically decreased, so that the input common-mode voltage of the comparator changes the overdrive voltage of an input tube in the comparator, and further the characteristic of the comparator is changed.
SUMMERY OF THE UTILITY MODEL
In view of this, the present disclosure provides a floating-type dynamic latch comparator and a successive approximation type analog-to-digital converter, which can maintain the overdrive voltage of the input tube of the comparator unchanged, thereby maintaining the characteristics of the comparator.
In a first aspect, an embodiment of the present application provides a floating-type dynamic latch comparator, including:
the dynamic latch comparison unit is provided with a power supply end and a power supply ground end which are connected to the energy storage unit, and a signal input end and a signal output end which are respectively configured to input a sampling voltage and output a voltage comparison result;
the input end of the energy storage unit is connected with a power supply, the output end of the energy storage unit is connected with the dynamic latch comparison unit, and the energy storage unit is used for enabling the power supply to charge a storage capacitor in the energy storage unit during voltage sampling and enabling the storage capacitor to discharge to provide required working voltage for the dynamic latch comparison unit during voltage comparison.
In some embodiments, the energy storage unit includes a switching device or a resistive device connected to the storage capacitor, where one end of the switching device or the resistive device is connected to the power supply, and the other end of the switching device or the resistive device is connected to the storage capacitor.
In some embodiments, the switching device is an MOS transistor, a source of the MOS transistor is connected to the positive electrode of the power supply, a drain of the MOS transistor is simultaneously connected to a power supply terminal of the dynamic latch comparator and the positive electrode of the storage capacitor, and a gate of the MOS transistor is used as a control terminal for receiving an on-off control signal.
In some embodiments, the resistive device includes a first resistor and/or a second resistor, one end of the first resistor is connected to the positive electrode of the power supply, and the other end of the first resistor is connected to the power supply terminal of the dynamic latch comparator and the positive electrode of the storage capacitor;
one end of the second resistor is connected with the negative electrode of the power supply, and the other end of the second resistor is connected with the negative electrode of the storage capacitor and the power ground end of the dynamic latch comparison unit.
In some embodiments, the switching device is a first diode and/or a second diode, an anode of the first diode is connected to an anode of the power supply, and a cathode of the first diode is connected to a power supply terminal of the dynamic latch comparing unit and an anode of the storage capacitor;
and the anode of the second diode is connected with the cathode of the power supply, and the cathode of the second diode is connected with the power ground end of the dynamic latch comparison unit and the cathode of the storage capacitor.
In some embodiments, the dynamic latching compare unit is a Strong-ARM type latching comparator, a linear preamplifier, or a two-tailed dynamic comparator.
In some embodiments, the Strong-ARM latch comparator comprises first to eleventh switching tubes, the first switching tube is used as a clock control tube, the second to third switching tubes are used as differential input tubes, the fourth to seventh switching tubes are used as common-gate structure differential output tubes, the eighth to ninth switching tubes are used as first reset pair tubes, and the tenth to eleventh switching tubes are used as second reset pair tubes;
the clock control tube, the differential input tube and the common-gate structure differential output tube are sequentially connected, the first reset pair tube is respectively connected with the drain electrode of the second switch tube and the drain electrodes of the fourth and sixth switch tubes in the common-gate structure differential output tube, and the second reset pair tube is respectively connected with the drain electrode of the third switch tube and the drain electrodes of the fifth and seventh switch tubes in the common-gate structure differential output tube;
if the differential input tube is a PMOS tube, the source electrode of the clock control tube and the common source electrode of the common-gate structure differential output tube are respectively used as the power supply end and the power supply ground end.
In some embodiments, if the differential input transistor is an NMOS transistor, the common source of the common-gate differential output transistor and the source of the clock control transistor are respectively used as the power supply terminal and the power ground terminal.
In a second aspect, an embodiment of the present application provides a successive approximation type analog-to-digital converter, including: the method comprises the following steps: the sampling and holding circuit, the floating type dynamic latching comparator, the switch logic and the conversion circuit; the sampling hold circuit and the conversion circuit are both connected to the input end of the floating type dynamic latching comparator, the output end of the floating type dynamic latching comparator is connected with the input end of the switch logic, and the capacitance switching control end of the conversion circuit is connected with the output end of the switch logic.
The embodiment of the application has the following beneficial effects:
the floating type dynamic latch comparator comprises a dynamic latch comparing unit and an energy storage unit, wherein a power supply end and a power supply ground end of the dynamic latch comparing unit are connected to the energy storage unit, and a signal input end and a signal output end are respectively configured to input a sampling voltage and output a voltage comparison result; the input end of the energy storage unit is connected with a power supply, the output end of the energy storage unit is connected with the dynamic latch comparison unit, and the energy storage unit is used for enabling the power supply to charge a storage capacitor in the energy storage unit during voltage sampling and switching to the storage capacitor to discharge so as to provide required working voltage for the dynamic latch comparison unit during voltage comparison. The dynamic latch comparing unit is designed to connect the power supply voltage and/or the power supply ground voltage to the storage capacitor for supplying power when the voltages are compared, and the power supply voltage provided by the storage capacitor gradually drops and the power supply ground voltage gradually rises during each comparison, so that the change of the overdrive voltage caused by the gradual reduction of the input common-mode voltage of the dynamic latch comparing unit is counteracted, and the characteristics of the comparator are kept unchanged.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 shows a schematic diagram of an input common-mode voltage variation of a comparator in a monotonically decreasing SAR ADC;
fig. 2 is a schematic structural diagram of a floating-type dynamic latch comparator according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing an architecture of a Strong-ARM type latch comparator according to an embodiment of the present application;
FIG. 4 is a schematic diagram showing another structure of a latch comparator of Strong-ARM type according to an embodiment of the present application;
fig. 5 shows a schematic structural diagram of a successive approximation type analog-to-digital converter according to an embodiment of the present application.
Description of the main element symbols:
100-floating type dynamic latch comparator; 110-a dynamic latch compare unit; 120-an energy storage unit;
200-successive approximation type analog-to-digital converter; 210-a sample and hold circuit; 220-dynamic latch compare circuit; 230-switching logic; 240-conversion circuit.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present application, are intended to indicate only specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments.
Some terms mentioned in the embodiments of the present application are explained herein.
SAR ADC: a successive approximation type analog-to-digital converter;
the Dynamic Latch Comparator is a Comparator circuit which utilizes a positive feedback loop to compare the magnitude of input voltage;
VCOM: the input common mode voltage is the average voltage value of the two input signal voltages. VCOM ═ (Vinp + Vinn)/2;
VOD: the overdrive voltage is the difference between the gate-source voltage VGS and the threshold voltage Vth of the MOS transistor.
For convenience of understanding, fig. 1 is a voltage variation waveform diagram of the input signal of the dynamic latch comparator in the monotonically decreasing SAR ADC at successive comparisons. It can be seen that the input common mode voltage of the two input signals (Vop and Von) of the dynamic latch comparator decreases gradually, and under the condition that the power supply is not changed all the time, the overdrive voltage flowing through the differential input tube of the comparator also changes, thereby affecting the performance of the dynamic latch comparator. Also, the higher the overdrive voltage, the faster the comparison speed will be, but the greater the noise generated.
To solve at least one of the above problems, referring to fig. 2, an embodiment of the present invention provides a floating-type dynamic latch comparator 100, which can be applied to a conversion system such as a monotonic decreasing SAR ADC, and which utilizes a circuit design with a smart structure and low cost to solve the problem that the input common-mode voltage of the conventional dynamic latch comparator changes.
Exemplarily, the floating-type dynamic latch comparator 100 includes two major parts, namely a dynamic latch comparing unit 110 and an energy storing unit 120, wherein the dynamic latch comparing unit 110 is mainly used for implementing the functions of dynamic latch and comparison, and here, may be some commonly used dynamic latch comparators, such as but not limited to a Strong-ARM latch comparator, a linear preamplifier, or a double tail dynamic comparator (double tail type). The energy storage unit 120 is mainly used to discharge the storage capacitor therein during the voltage comparison period of the dynamic latch comparing unit 110, so as to provide the required working voltage for the dynamic latch comparing unit 110. It can be understood that the floating-type dynamic latch comparator 100 is obtained by adding the energy storage unit 120 to improve the dynamic latch comparator.
As shown in fig. 2, the input terminal of the energy storage unit 120 is connected to a power supply, the output terminal is connected to the dynamic latch comparing unit 110, the power terminal and the power ground terminal of the dynamic latch comparing unit 110 are connected to the energy storage unit 120, and the signal input terminal and the signal output terminal of the dynamic latch comparing unit 110 are respectively configured to input the sampling voltage and the output voltage comparison result. In the embodiment of the present application, the energy storage unit 120 further includes a switching device for implementing voltage switching, for example, the switching device may be a MOS transistor, a diode, or other devices with switching characteristics. Specifically, a PMOS transistor or an NMOS transistor may be used, which is not limited herein.
For convenience of understanding, the structure and operation of the floating-ARM dynamic latch comparator 100 will be described below by taking a Strong-ARM type latch comparator as an example.
In one embodiment, as shown in fig. 3 or fig. 4, the dynamic latch comparing unit 110 includes first to eleventh switching tubes Q1 to Q11, specifically, the first switching tube Q1 is used as a clock control tube, the second to third switching tubes Q2 to Q3 are used as differential input tubes, the fourth to seventh switching tubes Q4 to Q7 are used as common-gate differential output tubes, the eighth to ninth switching tubes Q8 to Q9 are used as first reset pair tubes, and the tenth to eleventh switching tubes Q10 to Q11 are used as second reset pair tubes; the clock control tube, the differential input tube and the common-gate structure differential output tube are sequentially connected, the first reset pair tube is respectively connected with the drain electrode of the second switch tube Q2 and the drain electrodes of the fourth switch tube Q4 and the sixth switch tube Q6 in the common-gate structure differential output tube, and the second reset pair tube is respectively connected with the drain electrode of the third switch tube Q3 and the drain electrodes of the fifth switch tube Q5 and the seventh switch tube Q7 in the common-gate structure differential output tube.
As shown in fig. 3, the differential input transistor at this time is a PMOS transistor, and specifically, the gate of the first switch transistor Q1 is used for receiving the CLK clock signal, the source thereof is connected to the power source terminal and is also connected to the storage capacitor, and the drain thereof is connected to the sources of the second switch transistor Q2 and the third switch transistor Q3. The gates of the second switching tube Q2 and the third switching tube Q3 are respectively used for receiving input voltages Vinp and Vinn, and the drains are used for being connected to the sources of the fourth switching tube Q4 and the fifth switching tube Q5. For the common-gate structure differential output tube, the gates of the fourth switching tube Q4 and the sixth switching tube Q6 are connected, and the gates of the fifth switching tube Q5 and the seventh switching tube Q7 are connected to be used as a first output end and a second output end respectively; the sources of the sixth switching tube Q6 and the seventh switching tube Q7 are connected to the power ground. In addition, the sources of the eighth switch Q8 and the ninth switch Q9 in the first reset pair transistor, and the sources of the tenth switch Q10 and the eleventh switch Q11 in the second reset pair transistor are all connected to the power ground.
Based on the above structure using PMOS transistor as the differential input transistor, if MOS transistor is used to switch the storage capacitor and the power supply, as shown in fig. 3, the source of MOS transistor M1 is connected to the positive electrode of the power supply, the drain is connected to both the power source terminal of the dynamic latch comparing unit 110 and the positive electrode of the storage capacitor, and the gate is used as the control terminal for accessing an on-off control signal. For example, the on-off control signal may be associated with a comparison clock signal. It can be understood that, during each ADC sampling period, the on-off control signal is a conducting signal for conducting the MOS transistor, so that the power supply supplies power to the dynamic latch comparing unit 110 and charges the storage capacitor at the same time. And during each ADC comparison period, the on-off control signal is used to turn off the MOS transistor to disconnect the power supply terminal of the dynamic latch comparing unit 110 from the power supply. In the ADC comparison period (CLKB is 1), the dynamic latch comparison unit 110 compares the input voltage once, and resets the comparison unit when CLKB is 0. Since the current is drawn from the storage capacitor C1 for each comparison, the voltage on the storage capacitor C1 is gradually decreased, and thus the overdrive voltage of the differential input transistor in the dynamic latch comparator 110 can be maintained though the input common mode voltage is gradually decreased.
It is understood that, in addition to the above-mentioned switching device, the energy storage unit 120 may also use a device such as a resistor instead of the switching device. For example, in one embodiment, a resistor is used to replace the MOS transistor, specifically, one end of the resistor is connected to the positive electrode of the power supply, and the other end of the resistor is connected to both the power supply terminal of the dynamic latch comparator 110 and the positive electrode of the storage capacitor. The resistor can be a resistor with a large resistance value. It will be appreciated that the resistor may limit the rate of charging of the storage capacitor during the comparison, so that the voltage on the storage capacitor gradually decreases during the comparison. As another alternative, a resistor may also be disposed between the power ground and the negative electrode of the power supply. Or, besides one resistor is arranged between the power supply end and the positive electrode of the power supply, another resistor can be arranged between the power ground end and the negative electrode of the power supply, so as to achieve the equivalent effect of simultaneously disconnecting the power supply voltage and the power ground of the comparison unit and the power supply.
Still taking the above-mentioned Strong-ARM latch comparator as an example, the structure of the NMOS transistor as the differential input transistor will be described here. As shown in fig. 4, at this time, the common source of the common-gate differential output tube of the dynamic latch comparing unit 110 and the source of the clock control tube are respectively used as a power source terminal and a power source ground terminal, and the energy storage unit 120 includes a first resistor R1 and a second resistor R2, wherein the first resistor R1 is disposed between the power source ground terminal and the power source cathode, and the second resistor R2 is disposed between the power source ground terminal and the power source cathode.
Thus, when the storage capacitor C1 is charged through the resistor during ADC sampling; during the ADC comparison period (CLKB is 1), the dynamic latch comparator 110 compares the input voltage once, and resets the comparator when CLKB is 0. Since the current is drawn from the storage capacitor C1 for each comparison, a larger resistance can be selected to limit the charging speed of the power supply to the storage capacitor C1, which causes the voltage on the storage capacitor C1 to decrease gradually, so that the overdrive voltage of the differential input transistor in the dynamic latch comparing unit 110 can be maintained unchanged although the input common mode voltage decreases gradually.
It will be appreciated that instead of the MOS transistor, the resistor, etc. described above, other devices with internal resistance, such as a diode, etc., may be used instead, and that a diode with higher internal resistance is preferably used instead of the MOS transistor or the resistor. For example, if a diode is used instead of the first resistor, the anode of the diode is connected to the positive electrode of the power supply, and the cathode of the diode is connected to both the power supply terminal of the dynamic latch comparator 110 and the positive electrode of the storage capacitor. Similarly, another diode may be used instead of the second resistor and the like.
In the embodiment of the present application, the floating-type dynamic latch comparator 100 provides the operating power supply of the dynamic latch comparing unit 110 only by the storage capacitor by providing the storage capacitor between the power supply terminal of the dynamic latch comparing unit 110 and the power supply source, and disconnecting the power supply terminal (e.g., VCC pin) and/or the power ground terminal (e.g., GND pin) of the dynamic latch comparing unit 110 from the power supply source for providing the required operating voltage during each comparison. In addition, at other stages, such as the stage of sampling the voltage signal for input into the dynamic latch comparing unit 110, the power supply is used to charge the storage capacitor, so as to ensure that the dynamic latch comparing unit 110 can draw a corresponding current from the storage capacitor at each comparison.
It should be appreciated that, since the power supply voltage and/or the ground voltage of the floating-type dynamic latch comparator 100 are disconnected, external noise interference can be isolated and the comparison accuracy can be improved. In addition, the amplification factor of the differential input tubes of the comparator can be increased, because the input common mode voltage is unchanged and the current flowing into the comparator is also unchanged at the beginning of amplification of the comparator, the current flowing into one of the differential input tubes is increased and the current flowing into the other input tube is inevitably reduced, and as shown in fig. 3 or fig. 4, when the sum of the currents I1+ I2 is unchanged, I1 is increased and I2 is reduced, so the amplification gain is correspondingly increased.
The floating type dynamic latch comparator in the embodiment of the application is designed in such a way that when the dynamic latch comparator unit is used for voltage comparison, the power supply voltage and/or the power supply ground voltage are/is connected to the storage capacitor to supply power, and the power supply voltage provided by the storage capacitor gradually drops and the power supply ground voltage gradually rises during each comparison, so that the change of the overdrive voltage caused by the gradual reduction of the input common mode voltage of the dynamic latch comparator unit is counteracted, and the characteristic of the comparator is kept unchanged. In addition, because the input common mode voltage of the dynamic latch comparison unit is kept unchanged, the constant driving speed and noise can be kept, and the amplification factor of the differential input tube can be increased. In addition, the switching is realized by adopting passive devices such as a diode, a resistor, an MOS tube and the like, so that the generation of other interference signals can be reduced, and the power consumption and the cost are further saved.
Referring to fig. 5, an embodiment of the present invention further provides a successive approximation type analog-to-digital converter 200, especially a SAR ADC having a monotonically decreasing characteristic, which can effectively solve the problem that a comparator unit in the prior art changes characteristics due to a change of an input common mode voltage.
Illustratively, the successive approximation analog-to-digital converter 200 includes a sample-and-hold circuit 210, a dynamic latch comparator circuit 220, a switch logic 230 and a conversion circuit 240, and it is noted that the dynamic latch comparator circuit 220 here will be a floating type dynamic latch comparator as described in the above embodiments. The switch logic 230 mainly includes a multi-bit successive approximation register and a corresponding switch control circuit, and the conversion circuit 240 is also called a DAC circuit. Specifically, the sample-and-hold circuit 210 and the converting circuit 240 are both connected to the input terminal of the dynamic latch comparing circuit 220, the output terminal of the dynamic latch comparing circuit 220 is connected to the input terminal of the switch logic 230, and the capacitance switching control terminal of the converting circuit 240 is connected to the output terminal of the switch logic 230.
In the working process, the sampling hold circuit 210 samples the input voltage signal to obtain a sampling voltage, and then the sampling voltage and the output voltage of the conversion circuit 240 are input to the dynamic latch comparison circuit 220 for comparison, and the comparison result is transmitted to the successive approximation register in the switch logic 230, and the successive approximation register outputs the comparison result on one hand, and on the other hand, controls the conversion switch in the DAC circuit through the switch control circuit so as to perform the conversion of the next bit.
It is to be understood that the options described above in embodiment 1 regarding the floating-type dynamic latch comparator are also applicable to this embodiment, and therefore, the description will not be repeated here.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.
Claims (9)
1. A floating-type dynamic latch comparator, comprising:
the dynamic latch comparison unit is provided with a power supply end and a power supply ground end which are connected to the energy storage unit, and a signal input end and a signal output end which are respectively configured to input a sampling voltage and output a voltage comparison result;
the input end of the energy storage unit is connected with a power supply, the output end of the energy storage unit is connected with the dynamic latch comparison unit, and the energy storage unit is used for enabling the power supply to charge a storage capacitor in the energy storage unit during voltage sampling and enabling the storage capacitor to discharge to provide required working voltage for the dynamic latch comparison unit during voltage comparison.
2. The floating-type dynamic latch comparator according to claim 1, wherein the energy storage unit comprises a switching device or a resistive device connected to the storage capacitor, one end of the switching device or the resistive device is connected to the power supply, and the other end of the switching device or the resistive device is connected to the storage capacitor.
3. The floating-type dynamic latch comparator according to claim 2, wherein the switching device is an MOS transistor, a source of the MOS transistor is connected to the positive electrode of the power supply, a drain of the MOS transistor is connected to both the power supply terminal of the dynamic latch comparator and the positive electrode of the storage capacitor, and a gate of the MOS transistor is used as a control terminal for receiving an on-off control signal.
4. The floating-type dynamic latch comparator according to claim 2, wherein the resistive device comprises a first resistor and/or a second resistor, one end of the first resistor is connected to the positive electrode of the power supply, and the other end of the first resistor is connected to the power supply terminal of the dynamic latch comparator and the positive electrode of the storage capacitor;
one end of the second resistor is connected with the negative electrode of the power supply, and the other end of the second resistor is connected with the negative electrode of the storage capacitor and the power ground end of the dynamic latch comparison unit.
5. The floating-type dynamic latch comparator according to claim 2, wherein the resistive device is a first diode and/or a second diode, an anode of the first diode is connected to an anode of the power supply, and a cathode of the first diode is connected to a power supply terminal of the dynamic latch comparator unit and an anode of the storage capacitor;
and the anode of the second diode is connected with the cathode of the power supply, and the cathode of the second diode is connected with the power ground end of the dynamic latch comparison unit and the cathode of the storage capacitor.
6. The floating-type dynamic latch comparator according to any one of claims 1 to 5, wherein the dynamic latch comparing unit is a Strong-ARM type latch comparator, a linear preamplifier, or a two-tailed dynamic comparator.
7. The floating-type dynamic latch comparator according to claim 6, wherein the Strong-ARM latch comparator includes first to eleventh switching tubes, the first switching tube is used as a clock control tube, the second to third switching tubes are used as differential input tubes, the fourth to seventh switching tubes are used as common-gate differential output tubes, the eighth to ninth switching tubes are used as first reset pair tubes, and the tenth to eleventh switching tubes are used as second reset pair tubes;
the clock control tube, the differential input tube and the common-gate structure differential output tube are sequentially connected, the first reset pair tube is respectively connected with the drain electrode of the second switch tube and the drain electrodes of a fourth switch tube and a sixth switch tube in the common-gate structure differential output tube, and the second reset pair tube is respectively connected with the drain electrode of the third switch tube and the drain electrodes of a fifth switch tube and a seventh switch tube in the common-gate structure differential output tube;
when the differential input tube is a PMOS tube, the source electrode of the clock control tube and the common source electrode of the common-gate structure differential output tube are respectively used as the power supply end and the power supply ground end.
8. The floating-type dynamic latch comparator according to claim 7, wherein if the differential input transistor is an NMOS transistor, the common source of the cascode differential output transistor and the source of the clock control transistor are respectively used as the power source terminal and the power ground terminal.
9. A successive approximation analog-to-digital converter, comprising: a sample-and-hold circuit, a floating-type dynamic latch comparator as claimed in any one of claims 1 to 8, switching logic and a conversion circuit; the sampling hold circuit and the conversion circuit are both connected to the input end of the floating type dynamic latching comparator, the output end of the floating type dynamic latching comparator is connected with the input end of the switch logic, and the capacitance switching control end of the conversion circuit is connected with the output end of the switch logic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123382549.6U CN216625715U (en) | 2021-12-29 | 2021-12-29 | Floating type dynamic latch comparator and successive approximation type analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123382549.6U CN216625715U (en) | 2021-12-29 | 2021-12-29 | Floating type dynamic latch comparator and successive approximation type analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216625715U true CN216625715U (en) | 2022-05-27 |
Family
ID=81685993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123382549.6U Active CN216625715U (en) | 2021-12-29 | 2021-12-29 | Floating type dynamic latch comparator and successive approximation type analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216625715U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115276619A (en) * | 2022-09-28 | 2022-11-01 | 奉加微电子（昆山）有限公司 | Dynamic comparator, analog-to-digital converter and electronic equipment |
| CN116094502A (en) * | 2023-03-31 | 2023-05-09 | 深圳市九天睿芯科技有限公司 | Dynamic comparator, analog-to-digital converter and electronic equipment |
-
2021
- 2021-12-29 CN CN202123382549.6U patent/CN216625715U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115276619A (en) * | 2022-09-28 | 2022-11-01 | 奉加微电子（昆山）有限公司 | Dynamic comparator, analog-to-digital converter and electronic equipment |
| CN115276619B (en) * | 2022-09-28 | 2023-02-17 | 奉加微电子（昆山）有限公司 | Dynamic comparator, analog-to-digital converter and electronic equipment |
| CN116094502A (en) * | 2023-03-31 | 2023-05-09 | 深圳市九天睿芯科技有限公司 | Dynamic comparator, analog-to-digital converter and electronic equipment |
| CN116094502B (en) * | 2023-03-31 | 2023-06-09 | 深圳市九天睿芯科技有限公司 | Dynamic comparator, analog-to-digital converter and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Cho et al. | A 10 b, 20 Msample/s, 35 mW pipeline A/D converter | |
| US7015841B2 (en) | Analog to digital converter circuit of successive approximation type operating at low voltage | |
| Wu et al. | A 1-V 100-MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture | |
| CN101277112B (en) | Low-power consumption assembly line a/d converter by sharing operation amplifier | |
| CN216625715U (en) | Floating type dynamic latch comparator and successive approximation type analog-to-digital converter | |
| US7652600B2 (en) | A/D converter comprising a voltage comparator device | |
| CN111200402B (en) | High-linearity dynamic residual error amplifier circuit capable of improving gain | |
| CN112953503B (en) | High-linearity grid voltage bootstrap switch circuit | |
| CN106921391B (en) | System-level error correction SAR analog-to-digital converter | |
| CN111865320B (en) | Low-power-consumption successive approximation type analog-to-digital converter | |
| CN111245413B (en) | High-speed high-linearity grid voltage bootstrap switch circuit | |
| CN111865319A (en) | Ultra-low power consumption successive approximation type analog-to-digital converter based on four-input comparator | |
| CN110034762B (en) | Sampling frequency adjustable analog-digital converter | |
| CN1561000B (en) | Pipeline structure analogue/digital converter of controlling input common-mode drift | |
| US10461763B2 (en) | Double data rate time interpolating quantizer with reduced kickback noise | |
| TWI492547B (en) | Successive approximation analog-to-digital converter | |
| JP4757104B2 (en) | Semiconductor integrated circuit | |
| CN115412077A (en) | High-speed low-power consumption prepositive latch comparator | |
| CN115421552A (en) | Dynamic bias low-power-consumption integrator based on capacitor serving as floating voltage source | |
| CN113014264A (en) | Analog-digital converter with multi-mode selection | |
| US20230163777A1 (en) | Comparator and analog to digital converter | |
| CN112910447A (en) | Low-power-consumption comparator circuit with rail-to-rail input swing amplitude | |
| CN111865314A (en) | Analog front end circuit of analog-to-digital converter | |
| CN214675121U (en) | Analog-digital converter with multi-mode selection | |
| CN116911235B (en) | Over-sampling bootstrap switch isolation driving sampling hold circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |